Silicon Programming--Intro. to HDLs 1
Hardware description languages: introduction
• intellectual property (IP)
• introduction to VHDL and Verilog
• entities and architectural bodies
• behavioral and structural views
• examples
Silicon Programming--Intro. to HDLs 2
hardware description languages (HDL's): HDL isa language to describe hardware, just like it says;typically a HDL tries to use programming-language-type syntax and constructs to describe hardware,allowing the user to avoid schematic diagrams
Silicon Programming--Intro. to HDLs 3
Some things HDL's must deal with:
parallel activity (e.g., in a half adder, both theXOR and AND gates receive inputssimultaneously)
vector inputs (e.g., in an 8-bit adder, the inputsare each 8 bits and the output is 9 bits)
timing--both sequential and combinationallogic (e.g., in a register the interaction betweenthe clock input and the state changes must bedescribed)
levels of abstraction ideally will support both analysis and
synthesis for hardware components/systems
Silicon Programming--Intro. to HDLs 4
intellectual property (IP): HDL's are an effectiveway to describe components in which the internalworkings ("intellectual property") are proprietary butthe interface to other components must be public
"popular" HDL's: VHDL, Verilog
Silicon Programming--Intro. to HDLs 5
Two main HDLs: VHDL / Verilog
•VHDL--Very High Speed Integrated Circuit (VHSIC) Hardware Description LanguageStandards--IEEE 1076-1987;1076-1993; Ada-like languageAdditions--VHDL-AMS--Analog & Mixed Signal
•Verilog—1985; proprietary to Cadence until 1990 (“open Verilog”)C-like languageAdditions—Verilog-AMS—Analog & Mixed Signal
NOTE: this course is NOT designed to make you a VHDL or Verilog expert! The Altera tools (as well as other synthesis tools) work best with simpler HDL constructs (e.g., structural representations, modeest levels of nesting)
Silicon Programming--Intro. to HDLs 6
VHDL:
Behavioral, Structural, and "dataflow" views supported
Physical views generally not supported--VHDL descriptions do not encompass the low-level physical details of a design, in particular
VHDL descriptions can be (and usually are) "technology independent"; this supports REUSABILITY
VHDL is like "a programming language", but it describes hardware
therefore it must support CONCURRENCY of events
Silicon Programming--Intro. to HDLs 7
what can VHDL be used for?
design entry
simulation ("analysis"): VHDL simulator is anexample of a "discrete event simulator"
E1 E11 E2 E12 E3 E4 E111
synthesis: VHDL description can be turned intoa circuit layout by powerful "silicon compilers"
Silicon Programming--Intro. to HDLs 8
ex: half-adder
a
s
b
c
Inputs: a,b--"bits"
Outputs: s,c--"bits"
"boxes" sum and carry workconcurrently to perform atransformation. Within eachthere is a delay which depends onthe physical implementationchosen.
"sum"
"carry"
"higher level of abstraction":
a s
b c
"combining modules":
a s
b c a1 s1
b1 c1
"connecting signal"
"half adder"
(h.a.)
h.a.h.a.
Silicon Programming--Intro. to HDLs 9
VHDL--each component consists of:
entity--interface to the "outside world"
architecture--"what's inside"
there may be several architectures
for the same entity
Silicon Programming--Intro. to HDLs 10
example:
entity: a sum
b carry
entity half_adder is
port (a,b,: in std_logic; --alternative type "bit"
sum,carry: out std_logic);
end half_adder;
"half adder"
(h.a.)
Note: keywords, comment, “entity” syntax
Silicon Programming--Intro. to HDLs 11
type: "std_logic"
0:forcing 0; 1: forcing 1; -:don't care;
(U:unitialized;x:forcing unknown;z:high imped.
W:weak unknown;L:weak 0;H:weak 1)
requires (in Altera):
LIBRARY IEEE;
USE IEEE STD_LOGIC_1164.ALL;
Silicon Programming--Intro. to HDLs 12
"architecture": what's inside
some sample architectures:
architecture concurrent_behavior of half_adder is
--this is a behavioral description ("delay" = 5 ns here)
--it does NOT imply that XOR or AND gates will beused
-- in the implementation
begin
sum <= (a xor b) after 5 ns;
carry <= (a and b) after 5 ns;
end concurrent_behavior;
architecture structural of half_adder is
--this is a structural description
component XOR
port (X1,X2: in std_logic; O: out std_logic);
end component;
component AND
port (X1,X2: in std_logic; O: out std_logic);
end component;
begin
G1: XOR
port map (A,B,SUM);
G2: AND
port map (A,B,CARRY);
end structural;
a b
sum
carry
???
Silicon Programming--Intro. to HDLs 13
another example: "process" models:
architecture behavior of half_adder isbeginsum_proc: process(a,b)
begin if (a = b) then
sum <= '0' after 5 ns; else
sum <= (a or b) after 5 ns; end if;end process sum_proc;
carry_proc: process (a,b)begin
case a iswhen '0' =>
carry <= a after 5 ns;when '1' =>
carry <= b after 5 ns;when others =>
carry <= 'X' after 5 ns;end case;
end process carry_proc;end behavior;
a b
sum
carry
???
Silicon Programming--Intro. to HDLs 14
entity full_adder is
port(in1,in2,c_in: in std_logic;
sum,c_out: out std_logic);
end full_adder;
architecture dataflow of full_adder is
signal s1,s2,s3: std_logic;
constant gate_delay: Time := 5 ns;
begin
L1: s1 <= (in1 xor in2) after gate_delay;
L2: s2 <= (c_in and s1) after gate_delay;
L3: s3 <= (in1 and in2) after gate_delay);
L4: sum <= (s1 xor c_in) after gate_delay;
L5: c_out <= (s2 or s3) after gate_delay;
end dataflow;
Full adder example:
Silicon Programming--Intro. to HDLs 15
using two half addersfor a full adder:
architecture behavioral of full_adder issignal s1,s2,s3: std_logic;constant delay :Time:= 5 ns;
begin
HA1: process(in1,in2)--first half adderbegins1 <= (in1 xor in2) after delay;s3 <= (in1 and in2) after delay;end process HA1;
HA2: process(s1,c_in)--second half adderbeginsum <= (s1 xor c_in) after delay;s2 <= (s1 and c_in) after delay;end process HA2;
OR1: process(s2,s3) --compute carry-outbeginc_out <= (s2 or s3) after delay;end process OR1;
end behavioral;
Silicon Programming--Intro. to HDLs 16
example: multiplexor ENTITY my_mux IS
PORT (sel: IN BIT_VECTOR (0 TO 1);
a,b,c,d: IN BIT_VECTOR (0 TO 3);
y: OUT BIT_VECTOR (0 TO 3);
END my_mux;
ARCHITECTURE mux1 OF my_mux IS
BEGIN
y <= a WHEN sel="00" ELSE
b WHEN sel="01" ELSE
c WHEN sel ="10" ELSE
d WHEN OTHERS;
END mux1;
Silicon Programming--Intro. to HDLs 17
Some sequential logic examples:
--flip-flop:
--DFF (positive edge triggered,
--asynchronous --reset and enable):
entity DFF isport (D, clock, reset, enable:in std_logic; Q1: out std_logic);
end DFF;
architecture behavior of DFF is begin
process (reset, clock)begin if reset = '1' then
Q1 <= '0'; elseif (clock 'event and clock='1') then
if enable='1' thenQ1 <= D;
end if; end if;
end process;end behavior;
Silicon Programming--Intro. to HDLs 18
example of state machine:
reset 1X X0
X1
0X
output: 1 from state B, 0 from A and C
entity st_mach is
port (clock, reset, in1, in2:in std_logic;
out1: out std_logic);
end st_mach;
B
CA
architecture A of st_mach istype state_type is (state_a,state_b,state_c);signal state: state_type;
beginprocess (reset, clock)
begin if reset = '1' then
state <= state_a; elseif (clock 'event and clock='1') then
case state iswhen state_a =>
if in1='0' thenstate <= state_b;
elsestate <= state_c;
end if;when state_b =>
state <= state_c;when state_c =>
if in2 ='1' thenstate <= state_a;
end if;when others =>
state <= state_a; end case;
end if;end process;
with state selectout1 <= '0' when state_a;
'1' when state_b;'0' when state_c;
end A;
Silicon Programming--Intro. to HDLs 19
an example of a counter (Ashenden):
library ieee;
use ieee.std_logic_1164.all; entity count2 is generic (prop_delay : Time := 10 ns); port (clock : in bit; q1, q0 : out bit); end count2; --"generic": allows parameterization --in this case the "default" value is 10 ns
Silicon Programming--Intro. to HDLs 20
--behavioral description:
architecture behaviour of count2 is
begin count_up: process (clock) --process is sensitive to changes in --the input "clock" variable count_value : natural := 0; begin if clock = '1' then --"level-triggered" count_value := (count_value + 1)
mod 4; q0 <= bit'val(count_value mod 2)
after prop_delay; q1 <= bit'val(count_value / 2) after
prop_delay; end if; end process count_up; end behaviour;
--structural description: architecture structure of count2 is --define components component t_flipflop port (ck : in bit; q : out bit); end component; component inverter port (a : in bit; y : out bit); end component; --define connecting signals signal ff0, ff1, inv_ff0 : bit; begin --instantiate copies of components and --connect them bit_0 : t_flipflop port map(ck => clock, q => ff0); inv : inverter port map (a => ff0, y => inv_ff0); bit_1 : t_flipflop port map(ck=>inv_ff0,q => ff1); q0 <= ff0; q1 <= ff1; end structure;
Silicon Programming--Intro. to HDLs 21
more examples: Max+2--max2work--VHDLsubdirectory contains many useful VHDL examples
register example (from Altera--uses "lpm" library):
library ieee;
use ieee std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
entity reg24lpm is
port(d: in std_logic_vector(23 downto 0);
clk: in std_logic;
q: out std_logic_vector(23 downto 0);
end reg24lpm;
Silicon Programming--Intro. to HDLs 22
--architecture uses 2 12-bit components;
--other choices are also possible ( 3 8-bit
--components, e.g.)
--to see all options for "lpm_ff", search for
--lpm_ff in the Altera help
architecture a of reg24lpm is
begin
reg12a: lpm_ff
generic map (lpm_width => 12)
port map(data=>d(11downto 0),
clock=>clk, q => q(11 downto 0);
reg12b: lpm_ff
generic map (lpm_width => 12)
port map(data=>d(23 downto12),
clock=>clk,
q=> q(23 downto 12);
end a;
Silicon Programming--Intro. to HDLs 23
example of ram:ram256x8.vhd
library ieee;
use ieee std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library work;
use work.ram_constants.all;
entity ram256x8 is
port(data:in std_logic_vector(7 downto 0);
address: in std_logic_vector(7 downto 0):
we, inclock, outclock: in std_logic;
q: out std_logic_vector(7 downto 0));
end ram256x8;
Silicon Programming--Intro. to HDLs 24
architecture example of ram256x8 is
begin
inst_l: lpm_ram_dq
generic map (lpm_widthad => 8,
lpm_width => 8)
port map (data => data, address =>
address, we => we,
inclock => inclock, outclock
=> outclock, q => q);
end example;
Silicon Programming--Intro. to HDLs 25
Verilog:
The following is taken from the introduction by Dan Hyde at:
http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html
Other references can be found at:
http://www.verilog.net/docs.html
Architectural, behavioral, gate, and switch levels supported
Gate level: logic elements (structural)
Switch level: transistor level
Verilog program can be used for design, simulation, synthesis
Basic construct: module
Verilog program consists of interconnected modules
Usually a “top” module encapsulates all the others
Silicon Programming--Intro. to HDLs 26
Some simple examples of combinational logic:
// NAND gate (behavioral model)module NAND(in1, in2, out);
input in1, in2; output out; assign out = ~(in1 & in2);
endmodule
//AND gate (structural module)module AND(in1, in2, out);
input in1, in2; output out; wire w1; NAND NAND1(in1, in2, w1); NAND NAND2(w1, w1, out);
endmodule
Silicon Programming--Intro. to HDLs 27
A simple sequential logic example—what does it do?(Note “control statements” initial and always—these will run concurrently)
module simple; reg [0:7] A, B; reg C;
//stop execution after 20 time stepsinitial begin: stop_at // Will stop the execution after 20 simulation units. #20; $stop; end
//so these statements at time 0A = 0; $monitor(" %0d %b %b %b", $time, A, B, C); end
//main_process will loop until simulation is over (#1 means do at each step)always begin: main_process #1 A = A + 1;#1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; end
endmodule
Silicon Programming--Intro. to HDLs 28
Assignment:•Default is that new assignment is made whenever inputs change:
assign out = ~( in1 & in2)•Blocking and nonblocking statements:
Blocking: =; works like a “regular” programming language;Nonblocking: <=; does all right-hand assignment simultaneously
module blocking; reg [0:7] A, B; initial begin: init1
A = 3; #1 A = A + 1;
B = A + 1; $display("Blocking: A= %b B= %b", A, B );
A = 3; #1 A <= A + 1;
B <= A + 1; #1 $display("Non-blocking: A= %b B= %b", A, B );
end endmodule
output: Blocking: A= 00000100 B= 00000101 Non-blocking: A= 00000100 B= 00000100
Silicon Programming--Intro. to HDLs 29
Tasks and functionsVerilog has tasks, which are like procedures (do not return a value)Verilog also has functions, which must execute and return a value in 1 time stepA task can invoke a function; a function cannot invoke a task
Example:module tasks; task add;
input a, b; output c; reg R; begin
R = 1; if (a == b) c = 1 & R; else c = 0;
end endtask
initial begin: init1 reg p; add(1, 0, p); //invoke the task $display("p= %b", p);
end
endmodule (A similar function can also be defined)
Silicon Programming--Intro. to HDLs 30
Timing:
Like VHDL, Verilog uses discrete event simulation
The following can advance timing (order of events may not be predictable):
1. gate or wire delay, if specified.
2. a delay control, introduced by the # symbol.
3. an event control, introduced by the @ symbol.
4. the wait statement.
Silicon Programming--Intro. to HDLs 31
Examples:
Delay control:
#10: A = A + 1; //delay 10 units before executing the assignment
Event control:
@r begin // controlled by any value change in reg rA = B&C;
end
@(posedge clock2) A = B&C; // controlled by positive edge of clock2
@(negedge clock3) A = B&C; // controlled by negative edge of clock3
forever @(negedge clock) begin
A = B&C; end
Silicon Programming--Intro. to HDLs 32
Control by a specific event:
@(event6) begin
<some procedural code>
end
To trigger the event: -> event6
Wait statement: wait until condition becomes true (level sensitive):
wait (A == 3)
begin
A = B&C;
end
Silicon Programming--Intro. to HDLs 33
Fork / join: allow multiple threadsExample:fork: three
begin // code for thread 1
end
begin // code for thread 2
end
begin // code for thread 3
end join
All 3 threads execute concurrently; when all are finished, jump to statement after “join”