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8086 Pin diagram

8086 is a 40 pin DIPusing MOS technology. Ithas 2 GNDs as circuit

complexity demands alarge amount of currentflowing through thecircuits, and multiplegrounds help indissipating theaccumulated heat etc.8086 works on twomodes of operationnamely, Maximum Modeand Minimum Mode.

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Power Connections

1

19

20

40GND

CLK

GND

VCC

8086

Pin Description:GND Pin no. 1, 20

GroundCLK Pin no. 19 Type IClock: provides the basictiming for the processor andbus controller. It is

asymmetric with a 33% dutycycle to provide optimizedinternal timing.VCC Pin no. 40VCC: +5V power supply pin

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Address/ Data Lines

10

11

12

13

14

15

16

39AD14

AD13

AD12

AD11

AD10AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

8086

2

3

4

5

67

8

9

AD15

Continued

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Pin Description

AD15-AD0 Pin no. 2-16, 39 Type I/O

Address Data bus: These lines constitute the timemultiplexed memory/ IO address (T1) and data (T2, T3, TW,T4) bus. A0 is analogous to BHE* for the lower byte of thedata bus, pins D7-D0. It is low when a byte is to betransferred on the lower portion of the bus in memory or I/O

operations. Eight bit oriented devices tied to the lower halfwould normally use A0 to condition chip select functions.These lines are active HIGH and float to 3-state OFF duringinterrupt acknowledge and local bus hold acknowledge.

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Address Lines

8086

35

36

37

38

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4A3

A2

A1

A0

A1539

10

11

1213

14

15

16

2

3

4

5

6

7

8

9

Continued

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A19/S6, A18/S5, A17/S4, A16/S3 Pin no. 35-38 TypeO

Address / Status: During T1 these are the four mostsignificant address lines for memory operations. During I/Ooperations these lines are low. During memory and I/O

operations, status information is available on these linesduring T2, T3, TW and T4. The status of the interruptenable FLAG bit (S5) is updated at the beginning of eachCLK cycle. A17/S4 and A16/S3 are encoded as shown.

Continued

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A17/S4 A16/S3 Characteristics

0 (LOW) 0 Alternate Data

0 1 Stack

1(HIGH) 0 Code or None

1 1 Data

S6 is 0 (LOW)

This information indicates which relocation register ispresently being used for data accessing.These lines float to 3-state OFF during local bus hold

acknowledge.

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Status Pins S0-S7

26

27

28

34

35

36

37

38

8086 S7

S6

S5

S4

S3

Continued

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Pin Description

Status: active during T4, T1 and T2 and is returned to thepassive state (1,1,1) during T3 or during TW when READYis HIGH. This status is used by the 8288 Bus Controller togenerate all memory and I/O access control signals. Anychange by , or during T4 is used to indicate the beginning

of a bus cycle and the return to the passive state in T3 orTW is used to indicate the end of a bus cycle.

, ,- Pin no. 26, 27, 28 TypeO

Continued

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These signals float to 3-state OFF in hold acknowledge.These status lines are encoded as shown.

S2* S1* S0* Characteristics

0(LOW) 0 0 Interrupt acknowledge

0 0 1 Read I/O Port

0 1 0 Write I/O Port

0 1 1 Halt

1(HIGH) 0 0 Code Access

1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive

Continued

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Status DetailsIndication

0 0 0 Interrupt Acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive

Continued

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S4 S3 Indications

0 0 Alternate data

0 1 Stack

1 0 Code or none

1 1 Data

Continued

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----- Value of Interrupt Enable flag

----- Always low (logical) indicating 8086 ison the bus. If it is tristated another busmaster has taken control of the system bus.

----- Used by 8087 numeric coprocessor todetermine whether the CPU is a 8086 or8088

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Interrupts

17

18

8086

NMI

INTR

Pin Description:NMI Pin no. 17 Type INon Maskable Interrupt: an edgetriggered input which causes a type 2

interrupt. A subroutine is vectored tovia an interrupt vector lookup tablelocated in system memory. NMI is notmaskable internally by software. Atransition from a LOW to HIGH

initiates the interrupt at the end of thecurrent instruction. This input isinternally synchronized.

Continued

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INTR Pin No. 18 Type IInterrupt Request: is a level triggered input which is

sampled during the last clock cycle of each instruction todetermine if the processor should enter into an interruptacknowledge operation. A subroutine is vectored to via aninterrupt vector lookup table located in system memory. Itcan be internally masked by software resetting the interrupt

enable bit. INTR is internally synchronized. This signal isactive HIGH.

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Min mode signals

8086

HLDA

HOLD

ALE

VCC

26

27

28

24

25

29

30

31

33

Continued

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Pin Description

HOLD, HLDA Pin no. 31, 30 Type I/OHOLD: indicates that another master is requesting a localbus hold. To be acknowledged, HOLD must be activeHIGH. The processor receiving the hold request will issueHLDA (HIGH) as an acknowledgement in the middle of a T1clock cycle. Simultaneous with the issuance of HLDA theprocessor will float the local bus and control lines. AfterHOLD is detected as being LOW, the processor will LOWer

the HLDA, and when the processor needs to run anothercycle, it will again drive the local bus and control lines.The same rules as apply regarding when the local bus willbe released.HOLD is not an asynchronous input. External

synchronization should be provided if the system can nototherwise uarantee the setu time.

Continued

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WR* - Pin no. 29 Type OWrite: indicates that the processor is performing a writememory or write I/O cycle, depending on the state of theM/IO* signal. WR* is active forT2, T3 and TW of any write

cycle. It is active LOW, and floats to 3-state OFF in local bushold acknowledge.

M/IO* - Pin no. 28 type O

Status line: logically equivalent to S2 in the maximum mode.It is used to distinguish a memory access from an I/Oaccess. M/IO* becomes valid in the T4 preceding a buscycle and remains valid until the final T4 of the cycle(M=HIGH), IO=LOW). M/IO* floats to 3-state OFF in local

bus hold acknowledge.

Continued

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DT/R* - Pin no. 27 Type OData Transmit / Receive: needed in minimum system thatdesires to use an 8286/8287 data bus transceiver. It is used tocontrol the direction of data flow through the transceiver.Logically DT/R* is equivalent to S1* in the maximum mode,and its timing is the same as for M/IO*. (T=HIGH, R=LOW).This signal floats to 3-state OFF in local bus holdacknowledge.

DEN* - Pin no. 26 Type OData Enable: provided as an output enable for the 8286/8287in a minimum system which uses the transceiver. DEN* isactive LOW during each memory and I/O access and for INTAcycles. For a read or INTA* cycle it is active from the middle of

T2 until the middle ofT4, while for a write cycle it is active*

Continued

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ALE Pin no. 25 Type OAddress Latch Enable: provided by the processor to latch theaddress into the 8282/8283 address latch. It is a HIGH pulseactive during T1 of any bus cycle. Note that ALE is neverfloated.

INTA

* - Pin no. 24 Type OINTA* is used as a read strobe for interrupt acknowledgecycles. It is active LOW during T2, T3 and TW of eachinterrupt acknowledge cycle.

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Max mode signals

8086

GND

26

27

28

24

25

29

30

31

33

QS0

QS1

Continued

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Pin Description:RQ*/GT0*, RQ*/GT1* - Pin no. 30, 31 Type I/O

Request /Grant: pins are used by other local bus masters toforce the processor to release the local bus at the end of theprocessors current bus cycle. Each pin is bidirectional withRQ*/GT0* having higher priority than RQ*/GT1*. RQ*/GT* hasan internal pull up resistor so may be left unconnected. The

request/grant sequence is as follows:

Continued

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1. A pulse of1 CLK wide from another local bus masterindicates a local bus request (hold) to the 8086 (pulse 1)

2. During a T4 orT1 clock cycle, a pulse 1 CLK wide from the

8086 to the requesting master (pulse 2), indicates that the8086 has allowed the local bus to float and that it will enterthe hold acknowledge state at the next CLK. The CPUsbus interface unit is disconnected logically from the localbus during hold acknowledge.

3. A pulse 1 CLK wide from the requesting master indicates tothe 8086 (pulse 3) that the hold request is about to endand that the 8086 can reclaim the local bus at the nextCLK. Continued

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Each master-master exchange of the local bus is a sequenceof 3 pulses. There must be one dead CLK cycle after eachbus exchange. Pulses are active LOW.

If the request is made while the CPU is performing a memorycycle, it will release the local bus during T4 of the cycle whenall the following conditions are met: Request occurs on or before T2. Current cycle is not the low byte of a word (on an odd

address) Current cycle is not the first acknowledge of an interrupt

acknowledge sequence. A locked instruction is not currently executing. Continued

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LOCK* - Pin no. 29 Type OLOCK* : output indicates that other system bus masters are notto gain control of the system bus while LOCK* is active LOW.The LOCK* signal is activated by the LOCK prefix instruction

and remains active until the completion of the next instruction.This signal is active LOW, and floats to 3-state OFF in holdacknowledge.QS1, QS0 Pin no. 24, 25 Type OQueue Status: the queue status is valid during the CLK cycle

after which the queue operation is performed.QS1 and QS0 provide status to allow external tracking of theinternal 8086 instruction queue.

Continued

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QS1 QS0 Characteristics

0(LOW) 0 No operation

0 1 First Byte of Op Code fromQueue

1 (HIGH) 0 Empty the Queue

1 1 Subsequent byte from Queue

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Common Signals

Continued

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Pin Description:

RD* - Pin no. 34, Type ORead: Read strobe indicates that the processor is performing a memory ofI/O read cycle, depending on the state of the S2 pin. This signal is used toread devices which reside on the 8086 local bus. RD* is active LOW duringT2, T3 and TW of any read cycle, and is guaranteed to remain HIGH in T2until the 8086 local bus has floated.This signal floats to 3-state OFF in hold acknowledge.

READY Pin no. 22, Type I

READY: is the acknowledgement from the addressed memory or I/O devicethat it will complete the data transfer. The READY signal from memory / IO issynchronized by the 8284A Clock Generator to form READY. This signal isactive HIGH. The 8086 READY input is not synchronized. Correct operationis not guaranteed if the setup and hold times are not met.

Continued

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TEST* - Pin No 23 Type ITEST* : input is examined by the Wait instruction. If the TEST* input isLOW execution continues, otherwise the processor waits in an idle state.This input is synchronized internally during each clock cycle on the leadingedge of CLK.

RESET Pin no. 21 Type IReset: causes the processor to immediately terminate its present activity.

The signal must be active HIGH for at least four clock cycles. It restartsexecution, as described in the instruction set description, when RESETreturns LOW. RESET is internally synchronized.

Continued

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BHE*/S7- Pin No. 34 Type OBus High Enable / Status: During T1 the Bus High Enable signal (BHE*)should be used to enable data onto the most significant half of the data bus,pins D15-D8. Eight bit oriented devices tied to the upper half of the bus wouldnormally use BHE* to condition chip select functions. BHE* is LOW during T1for read, write, and interrupt acknowledge cycles when a byte is to be

transferred on the high portion of the bus. The S,7 status information isavailable during T2, T3 and T4. The signal is active LOW and floats to 3-stateOFF in hold. It is LOW during T1 for the first interrupt acknowledge cycle.

BHE* A0 Characteristics

0 0 Whole word

0 1 Upper byte from / to odd address

1 0 Lower byte from / to even address

1 1 None Continued

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MN/MX* - Pin no. 33 Type - IMinimum / Maximum: indicates what mode the processoris to operate in.

If the local bus is idle when the request is made the twopossible events will follow: Local bus will be released during the next clock. A memory cycle will start within 3 clocks. Now the four

rulesfor a currently active memory cycle apply with conditionnumber1 already satisfied.