L22 03April03 1
Semiconductor Device Modeling and CharacterizationEE5342, Lecture 22Spring 2003
Professor Ronald L. [email protected]
http://www.uta.edu/ronc/
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Ideal 2-terminalMOS capacitor/diode
x
-xox
0SiO2
silicon substrate
Vgate
Vsu
b
conducting gate,area =
LW
tsub
0y
L
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Band models (approx. scale)
Eo
Ec
Ev
qox
~ 0.95 eV
metal silicon dioxide p-type s/c
qm= 4.1 eV for Al
Eo
EF
m
EFp
Eo
Ec
Ev
EFi
qs,p
qSi= 4.05eV
Eg,ox
~ 8 eV
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Flat band condition (approx. scale)
Ec,Ox
Ev
Al SiO2p-Si
q(m-ox)= 3.15 eV
EF
m EFp
Ec
Ev
EFi
q(ox-Si)=3.1eV
Eg,ox
~8eV
cond band-flat for
VVV8.0
V
eV8.0EE
Then
eV85.0EE
If
sg
MS
fpfmFB
fpfm
fpc
qfp= 3.95e
V
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Equivalent circuitfor Flat-Band•Surface effect analogous to the
extr Debye length = LD,extr = [Vt/(qNa)]1/2
•Debye cap, C’D,extr = Si/LD,extr
•Oxide cap, C’Ox = Ox/xOx
•Net C is the series combOxextr,Dtot 'C1
'C1
'C1
C’Ox
C’D,extr
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Accumulation for Vgate< VFB
SiO2
p-type Si
Vgate<
VFB
Vsub = 0
EOx,x<0
x
-xox
0
tsu
b
x,OxSi
Ox
Si
SiSix,OxOx
Ox
Oxx,Ox
E31
E
39.37.11
EE
0xV
E
holes
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Accumulationp-Si, Vgs < VFBFig 10.4a*
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Equivalent circuitfor accumulation• Accum depth analogous to the
accum Debye length = LD,acc = [Vt/(qps)]1/2
• Accum cap, C’acc = Si/LD,acc
• Oxide cap, C’Ox = Ox/xOx
• Net C is the series combOxacctot 'C1
'C1
'C1
C’Ox
C’acc
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Depletion for p-Si, Vgate> VFB
SiO2
p-type Si
Vgate>
VFB
Vsub = 0
EOx,x> 0
x
-xox
0
tsu
b
x,OxSi
Ox
Si
SiSix,OxOx
Ox
Oxx,Ox
E31
E
39.37.11
EE
0xV
E
AcceptorsDepl Reg
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Depletion forp-Si, Vgate> VFBFig 10.4b*
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Equivalent circuitfor depletion•Depl depth given by the usual
formula = xdepl = [2Si(Vbb)/(qNa)]1/2
•Depl cap, C’depl = Si/xdepl
•Oxide cap, C’Ox = Ox/xOx
•Net C is the series comb
Oxdepltot 'C1
'C1
'C1
C’Ox
C’depl
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Inversion for p-SiVgate>VTh>VFB
Vgate>
VFB
Vsub = 0
EOx,x> 0
inversion for
threshold above
E Induced
depletes 0
E Induced
0xV
E
Si
Si
Ox
Oxx,Ox
Acceptors
Depl Reg
e- e- e- e- e-
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Inversion for p-SiVgate>VTh>VFBFig 10.5*
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Approximation concept“Onset of Strong Inv”• OSI = Onset of Strong Inversion occurs
when ns = Na = ppo and VG = VTh
• Assume ns = 0 for VG < VTh
• Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh
• Cd,min = Si/xd,max for VG > VTh
• Assume ns > 0 for VG > VTh
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MOS Bands at OSIp-substr = n-channelFig 10.9*
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Equivalent circuitabove OSI•Depl depth given by the maximum
depl = xd,max = [2Si|2p|/(qNa)]1/2
•Depl cap, C’d,min = Si/xd,max
•Oxide cap, C’Ox = Ox/xOx
•Net C is the series comb
Ox,mindtot 'C1
'C1
'C1
C’Ox
C’d,min
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MOS surface states**p- substr = n-channel
VGS s Surf chg Carr Den
VGS < VFB < 0 s < 0 Accum. ps > Na
VGS = VFB < 0 s = Neutral ps = Na
VFB < VGS s > 0 Depletion ps < Na
VFB < VGS < VTh s = |p| I ntrinsic ns = ps = ni
VGS < VTh s > |p| Weak inv ni< ns < Na
VGS = VTh s = 2|p| O.S.I . ns = Na
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n-substr accumulation (p-channel)Fig 10.7a*
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n-substrate depletion(p-channel)Fig 10.7b*
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n-substrate inversion(p-channel)Fig 10.7*
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Band models (approx. scale)
Eo
Ec
Ev
qox
~ 0.95 eV
metal silicon dioxide p-type s/c
qm= 4.28 eV for Al
Eo
EF
m
EFp
Eo
Ec
Ev
EFi
qs,p
qSi= 4.0eV
Eg,ox
~ 8 eV
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Flat band with oxidecharge (approx. scale)
Ev
Al SiO2p-Si
EF
m
Ec,Ox
Eg,ox
~8eV EFp
Ec
Ev
EFi
'Ox
'ss
msOxmsFB
Ox
Oxc
Ox
'ss
x
ssm
ss
CQ
VV
xV
dxdE
q1Q
E
surface gate the on
is Q'Q' charge
a cond FB at then
bound, Ox/Si the at
is Q' charge a If
q(fp-ox)q(Vox
)q(m-
ox)
q(VFB
) VFB= VG-VB, when Si bands
are flat
Ex
+<--Vox-->-
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References
* Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997.
**Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986