1
CMOSCMOS INTEGRATED CIRCUIT DESIGN TECHNIQUESINTEGRATED CIRCUIT DESIGN TECHNIQUES
University of University of IoanninaIoannina
Scan TestingScan TestingScan TestingScan Testing
Dept. of Computer Science and EngineeringDept. of Computer Science and Engineering
Y. Tsiatouhas
OverviewOverview
1.1. Scan testing: design and applicationScan testing: design and application
CMOS Integrated Circuit Design TechniquesCMOS Integrated Circuit Design Techniques
2.2. At speed testingAt speed testing
3.3. The scanThe scan‐‐set design techniqueset design technique
4.4. Scan testing power issuesScan testing power issues
5.5. The scanThe scan‐‐hold design techniquehold design technique
Scan Testing 2
g qg q
6.6. Level sensitive scan designLevel sensitive scan design
7.7. Broadcast and Illinois scan designBroadcast and Illinois scan designVLSI Systems
and Computer Architecture Lab
2
Sequential Circuits TestingSequential Circuits Testing
outputs = f(inputs, state)
In sequential circuits the initial state(register’s values) is not by default known.Consequently, the sensitization of faults
InputsOutputsCombinational Combinational
LogicLogic
and the propagation of the correspondingerroneous responses may turn to be a hardtask.A solution is to use techniques for theproper initialization of the circuit state toknown values.
• Application of proper test vectorsequences and/or the use of Set/Reset
Scan Testing 3
RegistersRegisters
““StateState””Clock
sequences and/or the use of Set/Resetsignals to setup the required state.
• Development of efficient techniques toset the initial state and observe thesubsequent state after the response ofthe circuit.
General Scan Testing SchemeGeneral Scan Testing Scheme
Scan‐In
LogicLogicRegistersRegisters
Scan‐Out
Inputs Outputs
ClockScanScan
RegisterRegister
Scan Testing 4
The memory elements (latches or Flip‐Flops) in a design are properly connected to forma unified shift register (scan register or chain). This way the internal state of the circuit isdetermined (controlled) by shifting in (scan‐in) to the scan register the required test datato be applied to the combinational logic. Moreover, the existing internal state (previouslogic response) can be observed by shifting out (scan‐out) the data stored into the scanregister.
3
Scan Testing Design Scan Testing Design (Ι)(Ι)
PI POCombinationalCombinationalLogicLogic
Primary Inputs
Primary Outputs
RegisterRegister
PI PO
S I
Original Circuit
Full Scan
Pseudo‐Primary Outputs
PPI PPO
CombinationalCombinationalLogicLogic
Scan Testing 5
Scan‐In
Scan‐Out
Pseudo‐Primary Inputs
ScanScanRegisterRegister
Partial ScanMultiple Scan Chains
Scan Testing Design Scan Testing Design (Ι(ΙII))
PI PO
RegisterRegister
PI PO
S I N
Scan‐In_1
Scan‐Out_1
ScanScanRegisterRegister
CombinationalCombinationalLogicLogic
CombinationalCombinationalLogicLogic
Scan Testing 6
Scan‐In
Scan‐Out
Scan‐In_N
Scan‐Out_N
ScanScanRegisterRegister
ScanScanRegisterRegister
.
.
.
4
Scan Path Design (I)Scan Path Design (I)nputs X1 Z1
utputs
CombinationalCombinational
Scan Chain
Primary In
. . . . . .X2
XK
Z2
ZN
. . .
SI
0
1
0
1
0
1
0
1
SOD Q
CLK
D Q
CLK
D Q
CLK1 2 M
MUX
MUX
MUX
MUX
“1”
Primary Ou
Scan FF D Flip‐Flop
CombinationalCombinationalLogicLogic
Scan Testing 7
Scan ModeSE=“1”
CLK
SE“1”
X1 Z1
nputs
utputs
CombinationalCombinational
Scan Path Design (II)Scan Path Design (II)
. . . . . .X2
XK
Z2
ZN
. . .
SI
0
1
0
1
0
1
0
1
SOD Q
CLK
D Q
CLK
D Q
CLK1 2 M
MUX
MUX
MUX
MUX
Scan Chain“0”
Primary In
Primary OuCombinationalCombinational
LogicLogic
Scan Testing 8
CLK
SE
Normal ModeSE=“0”
“0”
5
Test Sequences During Scan TestingTest Sequences During Scan Testing
. . .
ary Inputs . .
Test Vector
Prima
SI
. .
Outputs
clock cycles.
.1st sequence 2nd sequence 3rd sequence 4th sequence Νth sequence (Ν+1)th sequence. . .
Test Response
Scan Testing 9
.
Primary O
SO
clock cycles
. . .
Scan ApplicationScan Application (Ι)(Ι)
Scan cells testing1
SE = “1”
Scan‐in of alternating“0” and “1” from the SI input
2
3 Μ+1 clock cycles
Scan Testing 10
Response observationat the SO output
4
Μ = # of scan cells
6
Logic testing5
Scan ApplicationScan Application (Ι(ΙII))
g g
SE = “1”: Test data scan‐infrom the SI inputs
Μ clock cycles (scan‐in cycles)6
7 SE = “0”: Test patternapplication from the PI inputs
Scan Testing 11
Single clock pulse andresponse observation at the POs
single clock cycle (capture cycle)8
SE = “1”: New test data
Scan ApplicationScan Application (Ι(ΙIIII))
scan‐in from the SIsand simultaneous scan‐out of the test responses from the SOs
9
10
Μ clock cycles
Exists anothertest vector;
YES7
Scan Testing 12
11 End
No
7
D Q Out2D QIn2
D Q
CLK
In1D Q
CLKside path
Out11 1
1
Delay Fault TestingDelay Fault Testing
0
1
1 D Q
CLK
CLK
Out2D Q
CLK
In2
CLK
Logic
path under test
A path delay fault requires a pair of subsequent test vectors to be detected. The first test vector initializes the circuit while the second test vector activates the path under test.
V1 = <10>V2 = <11> ← Path ac va on test vector
← Ini alizing test vector
0 1
Scan Testing 13
The first test vector initializes the circuit while the second test vector activates the path under test.
tCLK
InitializingVector
Application
LaunchActivationVector
TestResponseCapture
How scan testing facilities can be exploited for delay fault testing ?
At speed clocking!
At Speed Scan Testing (I)At Speed Scan Testing (I)
. . . . . .
X1
X2
XK
Z1
Z2
ZN
(Skewed(Skewed‐‐load or Launchload or Launch‐‐onon‐‐shift Technique)shift Technique)
CombinationalCombinationalLogicLogic
XK ZN
. . .
CLK
SI0
1
0
1
0
1
0
1
SO
SE
D Q
CLK
D Q
CLK
D Q
CLK1 2 M
MUX
MUX
MUX
MUX
Scan Chain
unch
pture
Scan Testing 14
CLK
tSE
Shift Shift Lau
Cap Shift
Fast Transition
Delay fault oriented scan testing technique
Shift
8
At Speed Scan Testing (II)At Speed Scan Testing (II)
. . . . . .
X1
X2
XK
Z1
Z2
ZN
(Double Capture or Launch(Double Capture or Launch‐‐onon‐‐Capture Technique)Capture Technique)
CombinationalCombinationalLogicLogic
XK ZN
. . .
CLK
SI0
1
0
1
0
1
0
1
SO
SE
D Q
CLK
D Q
CLK
D Q
CLK1 2 M
MUX
MUX
MUX
MUX
Scan Chain
unch
pture
Scan Testing 15
CLK
tSE
Shift Shift
DeadTime
Lau
Cap Shift
Delay fault oriented scan testing technique
Fast Clock Pulses GenerationFast Clock Pulses Generation
D Q
Q1 Q2 Q3 Q4 Q5
SE
Scan_CLK1 2 3 4 5
00
11
0
1
CLK
PLL
PLL_CLK
Shift Register
Scan_CLK
Clock_Gating
Scan Testing 16
_
t
SE
PLL_CLK
CLK
Clock_Gating
9
The ClockedThe Clocked‐‐Scan TechniqueScan Technique
PI PO
X1
X2
Z1
Z2CombinationalCombinational
LogicLogicPI PO. . . . . .
XK ZN
SO
D Q
1SI
DCK
SCKSI
Flip‐Flop
DCK
D Q
2
DCK
SCKSI
D Q
M
DCK
SCKSI
. . .
Scan Testing 17
SCK
PI PO. . . . . .
X1
X2
X
Z1
Z2
Z
TheThe ScanScan‐‐Set Technique (I)Set Technique (I)
CombinationalCombinationalLogicLogic
XK ZN
. . .
SCLK
00
11
0
1
00
11
0
1
00
11
0
1
SE1
D Q
CLK
D Q
CLK
D Q
CLK1 2 M
“0”
Scan Testing 18
SO
. . .
TCLK
SI
00
11
0
1
00
11
0
1
00
11
0
1
SE2
D Q
CLK1
D Q
CLK2
D Q
CLKM
Test Data Scan‐InSE1=“0” ‐ SE2=“1”
“1”
10
PI PO. . . . . .
X1
X2
X
Z1
Z2
Z
TheThe ScanScan‐‐Set Technique (II)Set Technique (II)
CombinationalCombinationalLogicLogic
XK ZN
. . .
SCLK
00
11
0
1
00
11
0
1
00
11
0
1
SE1
D Q
CLK
D Q
CLK
D Q
CLK1 2 M
“1”
Scan Testing 19
SO
. . .
TCLK
SI
00
11
0
1
00
11
0
1
00
11
0
1
SE2
D Q
CLK1
D Q
CLK2
D Q
CLKM
Test Data ApplicationSE1=“1” ‐ SE2=“0”
“0”
PI PO. . . . . .
X1
X2
X
Z1
Z2
Z
TheThe ScanScan‐‐Set Technique (III)Set Technique (III)
CombinationalCombinationalLogicLogic
XK ZN
. . .
SCLK
00
11
0
1
00
11
0
1
00
11
0
1
SE1
D Q
CLK
D Q
CLK
D Q
CLK1 2 M
“0”
Scan Testing 20
SO
. . .
TCLK
SI
00
11
0
1
00
11
0
1
00
11
0
1
SE2
D Q
CLK1
D Q
CLK2
D Q
CLKM
Test Response CaptureSE1=“0” ‐ SE2=“0”
“0”
11
TheThe ScanScan‐‐Set Technique (IV)Set Technique (IV)
PI PO. . . . . .
X1
X2
X
Z1
Z2
Z
CombinationalCombinationalLogicLogic
XK ZN
. . .
SCLK
00
11
0
1
00
11
0
1
00
11
0
1
SE1
D Q
CLK
D Q
CLK
D Q
CLK1 2 M
“0”
Scan Testing 21
SO
. . .
TCLK
SI
00
11
0
1
00
11
0
1
00
11
0
1
SE2
D Q
CLK1
D Q
CLK2
D Q
CLKM
Test Response Scan‐OutSE1=“0” ‐ SE2=“1”
“1”
Dual FlipDual Flip‐‐Flops Scan ArchitectureFlops Scan Architecture
SID1
Scan FF
from scan FF MasterLatch
Slave L t h
C
SCB
SCA
Flip‐Flop
Q
C2
to scan FF
Latch Latch
D QC1
D2
SO
System FFD1 Slave
LatchC1
Q
SCA
CUPTURE
UPDATE
Scan Testing 22
from logicto logicD
Master Latch
D Q
Q
C2
D2
Q
CLK
C
Intel
12
Scan Testing ImpactScan Testing Impact
•Silicon area and pin count cost.
•Speed performance degradation.
•Test application time cost.
•Excess power consumption (usually outside circuit’sspecifications) during the scan‐in/out operations and thecapture of the test response in the scan chain.
Scan Testing 23
p p
Scan Chain
1 0 0 0 1 00 1 1 0 1 0
Test Vector Response
0
Scan Chain Shift Power Consumption (I)Scan Chain Shift Power Consumption (I)
CaptureCapture
0 1 0 0 0 10 1 1 0 1 0
1 0 1 0 0 00 1 1 0 1 0
0 1 0 1 0 00 1 1 0 1 0
1 0 1 0 1 00 1 0 0 1 0
Cycle 1Cycle 1
Cycle 2Cycle 2
Cycle 3Cycle 3
Cycle 4Cycle 4
Scan Testing 24
1 1 0 1 0 10 0 0 0 1 0
1 0 1 0 1 0
0 1 1 0 1 0 1 0 0 0 1 0
yy
Cycle 5Cycle 5
Cycle 6Cycle 6
13
Scan Chain
0 1 1 0 1 0
Test Vector Response
0
Scan Chain Shift Power Consumption (II)Scan Chain Shift Power Consumption (II)
1 0 0 0 1 0
# Transitions0 1 1 0 1 0
1 0 1 0 0 00 1 1 0 1 0
0 1 0 1 0 00 1 1 0 1 0
1 0 1 0 1 00 1 0 0 1 0
0 1 0 0 0 1 # Transitions = Distance from 1st scan‐out bit
Scan Testing 25
1 1 0 1 0 10 0 0 0 1 0
1 0 1 0 1 0
0 1 1 0 1 0 1 0 0 0 1 0
# Transitions = L – (Distance from 1st scan‐in bit)
L = scan chain length
h
Previous Test VectorPrevious Scan Chain State
New Response
Scan Chain Capture Power ConsumptionScan Chain Capture Power Consumption
0 1 1 1 0 1
1 0 1 0 0 0
Scan ChainPrevious Scan Chain State
Scan Chain
1 0 1 0 0 0 New Scan Chain State
Power consumption during scan testing procedures is a major concern since it can be severaltimes higher than this during the normal mode of operation. This can affect the reliability of
Scan Testing 26
g g p ythe circuit under test (CUT) due to overheat and electromigration phenomena.The excessive switching activity of the CUT during the scan operations may violate the powersupply IR and Ldi/dt drop limitations and increase the probability of noise induced testfailures. In addition, the elevated temperature can degrade the speed performance of theCUT and result to erroneous test responses that will invalidate the testing process and leadto yield loss.
14
XX‐‐bit Assignmentbit Assignment
•A large number of bits in a test cube that is generated byan ATPG tool are don’t care bits (X‐bits).
• In order to apply a test cube for circuit testing, specificvalues must be assigned to the X‐bits (test vectorformation). This task is called X‐filling.
•The X‐filling process can be oriented for shift and/orcapture power reduction.
Scan Testing 27
Low Power ScanLow Power Scan
0
from logic to logic
Scan FFDI
Original Topology
CLK
SI1
SE
D Q
CLK
MUX
to scan FFfrom scan FF
Use of Data Gating (φραγμός δεδομένων)t h i t th t t f th ll i
Original Topology
SE
from logic
to logic
Scan FF
DI
Scan Testing 28
techniques at the output of the scan cells inorder to eliminate the signal transitions atthe inputs of the combinational logic duringthe scan‐in/out operations.Dynamic power reduction.
CLK
SI
0
1
D Q
CLK
MUX
to scan FF
DI
from scan FF
15
ScanScan‐‐Hold FlipHold Flip‐‐FlopFlop
0
from logic to logic
Scan FFDI
Original Topology
CLK
SI1
SE
D Q
CLK
MUX
to scan FFfrom scan FF
FF
from logic to logic
Scan‐Hold FFDI
Original Topology
Scan Testing 29
Delay testing oriented Flip‐Flop!
+ Dynamic power reduction.
CLK
SI
0
1
SE
D Q
CLK
MUX
to scan‐hold FF
DI
from scan‐hold FFHold
FF LatchD Q
C
TheThe ScanScan‐‐Hold TechniqueHold Technique
PI PO
X1
X2
Z1
Z2CombinationalCombinational
LogicLogicPI PO. . . . . .
XK ZN
SO
D
Q
1
SI
D
C
ASI
ScanFF
D
Q
2
D
C
ASI
D
Q
M
D
C
ASI
. . .
ScanFF
ScanFF
Scan Testing 30
Hold
D
Q
Latch
C
SE
CLK
D
Q
Latch
C
D
Q
Latch
C
Intel
Scan‐Hold FF
16
Level Sensitive Scan Design (I)Level Sensitive Scan Design (I)
PI PO
X1
X2
Z1
Z2CombinationalCombinational
LogicLogicPI PO. . . . . .
XK ZN
SO
D
Q
1
SI
D
C
ASI
L1
D
Q
2
D
C
ASI
L1
D
Q
M
D
C
ASI
L1. . .
Scan Testing 31
B
D
Q
L2
B
A
C
D
Q
L2
B
D
Q
L2
B
LSSD DesignIBM
Latches Pair
Level Sensitive Scan Design (II)Level Sensitive Scan Design (II)
PI PO
X1
X2
Z1
Z2CombinationalCombinational
LogicLogicPI PO. . . . . .
XK ZN
D
Q
1
SI
D
C
ASI
L1
D
Q
2
D
C
ASI
L1
D
Q
M
D
C
ASI
L1. . .
Scan Testing 32
SO
B
D
Q
L2
B
A
C2
D
Q
L2
B
D
Q
L2
B
LSSD DesignIBM
Latches PairC1 . . .
17
Level Sensitive Scan Design (III)Level Sensitive Scan Design (III)
D Q
CLK
D
CLK
Q_FF
Edge Triggeredl l
D Q
CLK
D
CLK
Q_Latch
D Latch
D‐Latch and D‐Flip‐Flop operation
D
CLK
Q_Latch
Q_FF
D Flip‐Flop
Scan Testing 33
Non overlapping clocks
C ή A
t
BSI
Latches Pair
Test Data CompressionTest Data Compression
Typically, ATPG tools generate test vectors where only 1% to 5% of the bits have specified values!
On the other hand, test data volume is a major concern for the available bandwidth and the
.
.
.compressor
Compactor
Scan Chains
CompressedTestData
CompactedResponse
Stim
uli
st Responses
ATEs’ storage capabilities.
Test Patterns
Scan Testing 34
.
Dec C
CUTCUT
Low Cost ATE Tes
ChipChipComparator
Expected Responses
18
Linear DecompressionLinear Decompression
X1
Z9 Z5 Z1
Decompressor
Scan Chains
8753211 XXXXXZ 65217 XXXXZ 413 XXZ
652110 XXXXZ 416 XXZ 32 XZ
9419 XXXZ 735 XXZ 521 XXZ
107312 XXXZ 8528 XXXZ 614 XXZ
X2
X3
Z9 Z5 Z1
Z10 Z6 Z2
Z11 Z7 Z3
X9 X5X7
Scan Testing 35
X4
Z12 Z8 Z4X10 X6X8
XOR
Broadcast & Illinois Scan DesignBroadcast & Illinois Scan Design
SI
SC1 SC2 SCn. . .
B d t S D i
C1 C2 Cn. . .
Broadcast Scan Design
Segment 1SI
SO4
B‐S_Mode
0
SO3SO2SO1
Combinational Logic C
Scan Testing 36
g
Segment 2
Segment 3
Segment 40
1
Illinois Scan Design
0
1
0
1
Combinational Logic C
19
Reconfigurable Broadcast Scan DesignReconfigurable Broadcast Scan Design
0
Pin1 Pin2 Pin3 Pin4 Control
Scan_Chain 1
1
0
1
0
1
Scan_Chain 2
Scan_Chain 3
DynamicReconfiguration
Scan Testing 37
0
1
Scan_Chain 4
Scan_Chain 5
Scan_Chain 6
Space CompactionSpace Compaction
SCO1 SCO2 SCO3 SCO4 SCO5 SCO6 SCO7 SCO8
Scan
‐Chain 1
Scan
‐Chain 2
Scan
‐Chain 3
Scan
‐Chain 4
Scan
‐Chain 5
Scan
‐Chain 6
Scan
‐Chain 7
Scan
‐Chain 8
Scan‐chains’ outputs
Scan Testing 38
Linear Phase
Compactor
Out1 Out2 Out3 Out4X‐Compact
20
RandomRandom––Access Scan DesignAccess Scan Design
PI PO. . . . . .
X1X2
XK
Z1Z2
ZN
Combinational LogicCombinational Logic
Q
N
SC
SC
...
SC
SC
...
SC
SC
...
Row (X) Decoder
…
…
CLK
SI
SO
Scan Cell
Scan Testing 39
D
Q
CLKSE
SI
SC
0
1SI
TM
AS CLK
Q
SC SC SC
Column (Y) Decoder
Address Shift Register
R
…SO
AI
SI
Reordering of Scan Chain FlipReordering of Scan Chain Flip‐‐FlopsFlops (Ι)(Ι)
44FFFF8FF8FF
Typical Scan Chain
50Test
Vectors
300Test
Vectors
2FF
2FF
50 TV 300TV
ΙΝ
Scan Testing 40
SO2FF2FF44FFFF
Test Application: 300(20+1)+20 = 6320 clock cycles“Random” register
connection
1st Alternative Test Application: 300(14+1)+8 = 4508 clock cyclesImprovement
29% !
21
SI 44FFFF8FF8FF
2nd Alternative Scan Testing Application
Reordering of Scan Chain FlipReordering of Scan Chain Flip‐‐FlopsFlops ((IIII))
50Test
Vectors
300Test
Vectors
2FF
2FF ΙΝ
Scan Testing 41
SO
Test Application:
2FF2FF44FFFF
50(14+1) = 750 clock cycles
250(12+1)+8 = 3258 clock cycles
4008 clock cycles
Improvement37% !
SI44FFFF8FF8FF
3rd Alternative Scan Testing Application with cell reordering
Reordering of Scan Chain FlipReordering of Scan Chain Flip‐‐FlopsFlops ((IIIIII))
50ΔιανύσματαΕλέγχου
300ΔιανύσματαΕλέγχου
2FF
2FF ΙΝ
Scan Testing 42
SO
Test Application: 50(18+1) = 950 clock cycles
250(4+1)+4 = 1254 clock cycles
2204 clock cycles
2FF2FF44FFFF
Improvement65% !
In addition, test powerreduction is achieved!
22
ReferencesReferences
• “Principles of Testing Electronics Systems,” S. Mourad and Y. Zorian, John Wiley& Sons, 2000.
• “Essentials of Electronic Testing: for Digital Memory and Mixed‐Signal VLSI• Essentials of Electronic Testing: for Digital, Memory and Mixed‐Signal VLSICircuits,” M. Bushnell and V. Agrawal, Kluwer Academic Publishers, 2000.
• “Power‐Constrained Testing of VLSI Circuits,” N. Nicolici and B. Al‐Hashimi,Kluwer Academic Publishers, 2003.
• “Digital Systems Testing and Testable Design,” M. Abramovici, M. Breuer and A.Friedman, Computer Science Press, 1990.
• “System‐on‐Chip Test Architectures,” L‐T Wang, C. Stroud and N. Touba,Morgan‐Kaufmann, 2008.
Scan Testing 43
• “VLSI Test Principles and Architectures,” L‐T Wang, C‐W. Wu and X. Wen,Morgan‐Kaufmann, 2006.