Scouting Intellectual Properties in the Age of “More Than Moore”
Dr. Kevin Hess
Central Texas Electronics Association Symposium
Austin, TX – Feb 11, 2016
2Patent technics
How to identify strategic patents for acquisition
within a technology domain – 3D IC?
• IP Landscapes and Taxonomies
• Context for 3D IC Case Study
• Methodology of Searching
• Case Study and Analysis
3Patent technics
An IP Landscape is a populated taxonomy used
to address questions about patents in a
technology domain…
• What solutions exist to technical issues in a domain?
• Who are the key innovators (…competitors)?
• What is the investment trend in the space?
• Were there any inflection points in the domain?
• Where are the acquisition opportunities for patents?
4Patent technics
Taxonomies are hierarchical frameworks for classifying
solutions within a technology domain…• Comparing patent sets (portfolios)
• Identifying innovation opportunities (white space, gaps)
• Finding critical innovations (singular solutions)
Taxonomies can be structured in many ways…• Physical features of a product
• Attributes of a product or process
• Steps of a process
• Stages in a supply chain
5Patent technics
Pushing the limits of Moore’s Law…
Source: IEEE CPMT Webinar: Photonics in Heterogeneous 3D-SiP: A Key to Maintaining the Pace of Progress; W.R.Bottoms; 4 Feb 2016.
6Patent technics
Planar devices are at the cost inversion… (physics)
Source: IEEE CPMT Webinar: Photonics in Heterogeneous 3D-SiP: A Key to Maintaining the Pace of Progress; W.R.Bottoms; 4 Feb 2016.
7Patent technics
Source: IEEE CPMT Webinar: Photonics in Heterogeneous 3D-SiP: A Key to Maintaining the Pace of Progress; W.R.Bottoms; 4 Feb 2016.
Planar devices are at the cost inversion… (physics)
8Patent technics
FPGAs… Xilinx Virtex-7 (2011)
…Altera Stratix 10 (2015)
(2.5D - microbumps, TSV, interposer… )
Sources: www.xilinx.com; www.altera.com
(Intel EMIB - microbumps, Si bridges… )
9Patent technics
Processors... improved processor-memory bandwidth
Source: IEEE CPMT Webinar: Photonics in Heterogeneous 3D-SiP: A Key to Maintaining the Pace of Progress; W.R.Bottoms; 4 Feb 2016.
10Patent technics
Processor Systems… AMD Fiji GPU (2015)
SK Hynix DRAM HBM >
(Micro bumps, TSV, Interposer… )
Sources:www.amd.com;http://www.eetimes.com/auth
or.asp?section_id=36&doc_id=1327254
11Patent technics
Memory…
• Samsung
• SK Hynix HBM
• Micron HMC(not 3D VNAND Flash)
Source: IEEE CPMT Webinar: Photonics in Heterogeneous 3D-SiP: A Key to Maintaining the Pace of Progress; W.R.Bottoms; 4 Feb 2016.
12Patent technics
Presentation at JEDEC
Committee JC42.6 Mobile
Memory Forum, June 2011.
Source: JEDEC Standard JESD229-2. August 2014.
DRAM - JEDEC JESD229-2 “Wide I/O 2” (Aug 2014)[Micron HMC, SI2… alliances, working groups, etc.]
13Patent technics
Presentation at JEDEC Committee JC42.6 Mobile Memory Forum, June 2011.
JEDEC Publication 95, Design Registration 4.26, Micropillar Grid Array (Dec 2011)
DRAM - JEDEC JESD229-2 “Wide I/O 2” (Aug 2014)
14Patent technics
A patent acquisition to support licensing or defensive position should focus
on a common, critical feature or element of the system of interest. Ideally,
the solution is prescribed by a design standard.
For 3D (and 2.5D) IC, products and design standards use micro-bumps or -
pillars for die or interposer interconnect.
Therefore, interconnect is a topic of interest for investment.
The first step is to construct a landscape taxonomy against which to assess
where there are key solutions (patents) available.
15Patent technics
Taxonomy subtopics describe
the physical features and
functions of a 3D IC system
that support the high level
interconnect topic.
3D IC Interconnect
Simple illustrative taxonomy for 3D IC based on structures.
Devices (die, chips, memory, processors)
Format (bumps, pillars)
Layout (array, grid)
Materials (solder, copper)
Function (communications, signal)
System (3D, multiple die)
16Patent technics
Building a patent set should employ at least two approaches, or lenses:
− Keyword Booleans are essential as a starting point; provide context; can
be focused on fields – title, abstract, claims.
− Class codes are generally broad; misclassification happens; require at
least one additional “lens”.
− Citations* provide peer group information; multi-level cites can return
adjacent and contemporaneous innovations.
*Requires source information to start.
citationsclasses
keywords
− Semantic matching* returns conceptually
similar documents; can be based on any text
document - patents, product descriptions,
technical articles, standards, etc. (augment
with focus keywords).
17Patent technics
*Strength filters are comparative algorithms for
screening criteria such as indicators of patent
quality, as well as assignee revenue.
Initial patent set defined by keyword and semantic searches. Then refined
based on filters for patent quality and context of acquisition.
Keywords
Semantic
Review
Cite Mining
Data Set
Filtering Algorithms*
Solutions, Trends, Players
Acquisition
CandidatesRefined Data Set
Second Iteration
First Iteration
18Patent technics
Taxonomy nodes converted to keyword phrases. The result set
includes overlap between KW search strings… (25585)
k(ij) Definition String Results*
K(1,1) Device1 (die or chip or semiconductor or silicon or IC or "integrated circuit") 3917
K(1,2) Device2 (memory or processor or CPU or MPU or GPU or DRAM or Flash) 1735
K(1,3) Format1 (bump or pillar or column or post or micropillar or microbump or "micro-bump" or "micro-pillar") 3537
K(1,4) Format2 (flipchip or "flip chip" or "flip-chip") 614
K(1,5) Layout (array or grid or interposer or interposed) 3828
K(1,6) Materials (metal or alloy or solder or copper) 3898
K(1,7) Function (interconnect* or connect* or communicat* or signal or redistribution) 4139
K(1,8) System1 (3d or 3-d or 3-dimensional or z-direction or z-axis or vertical or stacked) 3380
K(1,9) System2 ("chip-to-chip" or multidie or multichip or "multi-die" or "multi-chip" or "multiple chips"~2 or
"multiple die"~2 or "two die"~3 or "two chips"~3)537
K(1,10) NOT Wirebond (wirebond or "wire bond") na
* Matches versus final pool resulting from Boolean of keyword terms (overlap).
19Patent technics
Logical “OR” of the keyword string results, refined search
field, patent jurisdiction, and document status.
Code String Limitations Results
K1a ((die or chip or semiconductor or silicon or IC or "integrated circuit")
OR (memory or processor or CPU or MPU or GPU or DRAM or Flash)) AND
((bump or pillar or column or post or micropillar or microbump or "micro-bump" or
"micro-pillar") OR (flipchip or "flip chip" or "flip-chip")) AND ((array or grid or
interposer or interposed)) AND ((metal or alloy or solder or copper)) AND
((interconnect* or connect* or communicat* or signal or redistribution)) AND ((3d
or 3-d or 3-dimensional or z-direction or z-axis or vertical or stacked) OR
("chip-to-chip" or multidie or multichip or "multi-die" or "multi-chip" or "multiple
chips"~2 or "multiple die"~2 or "two die"~3 or "two chips"~3)) NOT ((wirebond or
"wire bond"))
TAC, WW 8977
K1b As above. Claims only, WW 5291
K1c As above. TAC, USG&A 4510
K1d As above. Claims only, USG&A 2290
K1e As above. TAC&B, WW
K1f As above. TAC&B, USG&A
Keyword Boolean yields 4510 hits for US Grants and Apps.
* TAC – search against title, abstract, and claims.
20Patent technics
Semantic matching to interconnect description provided in the JEDEC
Publication “Micropillar Grid Array”…
“((die or chip or semiconductor or IC or "integrated circuit") OR
(memory or processor or CPU or MPU or GPU or DRAM or Flash))”
with added keyword string search to ensure context…
Returns 945 results, 74 overlapping the initial KW search hits.
21Patent technics
Summary of Semantic Search ResultsCode Semantic Source Context Limitations Results
S1 JEDEC Micropillar Grid Array Definitions (2011)
http://www.jedec.org/sites/default/files/docs/JESD229.pdf
Device1 OR Device2 USG&A 945
S2 Samsung Press Release Wide IO DRAM (2011)
http://www.samsung.com/global/business/semiconductor/ne
ws-events/press-releases/detail?newsId=4028
Device1 OR Device2 USG&A 991
S3 Micron Hybrid Memory Cube Technology Description
http://www.hybridmemorycube.org/news.html
Device1 OR Device2 USG&A 919
KW JEDEC Samsung HMC
K1 S1 S2 S3
K1 - 74 32 34
S1 - 14 26
S2 - 330
S3 -
K1 + S1, S2, S3 = 6553 patents, 4010 families
Negligible overlap between the keyword and
semantic searches was observed. The
overlap between semantic searches was
marginal, except for S2:S3.
Semantic search yielded 2495 unique hits.
22Patent technics
Top 50 Assignees – Patent Counts (bar) and Revenue (line)
Top companies with larger holdings have significant revenue; not likely to
represent patent acquisition opportunities.
23Patent technics
Top 50 - Patent Count (size) and Revenue (color scale)
Number of large companies, many one might expect in this space.
Confirms companies noted in the market orientation for 3D IC.
Several “zero revenue” patent holding companies highlighted.
24Patent technics
Landscape of Derived Topics and Top 5 Assignees
Largest holders have patents across the landscape.
Few areas untouched by the top 5.
Alignment with initial taxonomy.
Patents per cell: 9
25Patent technics
The priority to filing ratio for grants suggests early patent families created follow-on
filings - one indicator of patent value; later patents less fundamental.
Priority Year
Filing Year
Early Development18 Month Publication Delay
26Patent technics
The initial patent set (6553) is too large to identify acquisition prospects.
Innography’s CustomStrength™ feature provides a means for ranking by
intrinsic and extrinsic factors (i.e., patent maturity, examination length,
forward and backward citations).
Code criteria for “patent quality” and filter the larger data set for just the
patents of interest.
Innography provides an example CS filter based on the oft-quoted
“Valuable Patents” paper by Allison, et al. (2003):
“if((fwdcites/age) > 1, 1, 0) + if(cites > 18, 0, if(cites > 5, 1, 0)) + if(age > 10, 1, 0) +
if(life > 1, 1, 0) + if(inventors > 3, 1, 0) + if((publishyear - filedyear) > 4, 1, 0) +
if(claims > 25, 1, 0) + if(litigation > 0, 1, 0)”
Valuable Patents paper: http://www.law.gmu.edu/faculty/papers/docs/03-31.pdf
27Patent technics
Patent acquisition for licensing - proposed factors to define patent
quality and acquisition likelihood:
• Forward citation count at least equals numeric age (1 cite/yr)
• Backward citation count of at least 5
• At least 7 yrs since priority and 5 yrs before expiration
• Prosecution length at least 4 yrs
• Not used in litigation
• Asset owned by small entity (<$10M revenue proxy)
Ranking algorithm from above criteria (max score of 7):“if (revenue <10000000,1,0) + if((fwdcites/age) > 1, 1, 0) + if(cites > 5, 1, 0) + if(age >= 7,
1, 0) + if(life >= 5, 1, 0) + if((publishyear - priorityyear) > 4, 1, 0) + if(litigation > 0,0,1)”
28Patent technics
The initial starting set (K1 + S1, S2, S3) contained 6553 unique patents.
Using the patent quality and acquisition scoring algorithm and setting a
threshold at 70% of max score of 7 points (composite scores of 5-7
points) as the cut off. Initial data set is reduced to a subset of 358
patents.
Of the 358 patents, several exemplary documents were found that
represent potential acquisition opportunities.
29Patent technics
Patent Count (size) and Revenue (<$10m reported)
Diverse neighborhood…
Patent aggregators suggest an active patent space.
Research groups and universities now prominent – potential source.
Refine further by removing large holding companies – Round Rock Research, etc.
30Patent technics
Patent Count and Litigation Record – Top 30
Top 30 companies with no
significant reported revenue and
patents flagged by the maturity,
citations, examination filters.
Company records flag patent
holders involved in any litigations.
These assignees are less likely to
sell patents.
31Patent technics
Landscape of Derived Topics and Top 5 Assignees
Focus areas better resolved for the top 5
assignees. Some hints as to company IP
strategy.
Patents per cell: 2
32Patent technics
Elm Technology Corp. (US)
“Three Dimensional Structure
Integrated Circuits”
Priority: Apr 1997
33Patent technics
Advanpack Solutions (SG)
“Pillar Connections for
Semiconductor Chips and Method
of Manufacture”
Priority: Apr 2000
34Patent technics
Megica Corporation (TW)
“Low Fabrication Cost, Fine Pitch
And High Reliability Solder Bump”
Priority: Mar 2001
35Patent technics
Arbor Company LLP (US)
“Reconfigurable Processor Module
Comprising Hybrid Stacked
Integrated Circuits”
Priority: Dec 2001
36Patent technics
Norman, Richard (CA)
“Microelectronic Complex Having
Clusters Conductive Members”
Priority: Dec 2001
37Patent technics
Hong Kong Applied Science and
Technology Research Institute
(CN)
“Bonding Method for Through-
Silicon-Via Based 3D Wafer
Stacking”
Priority: Jun 2008
38Patent technics
• The 3D IC interconnect was identified as an interesting neighborhood. A
patent data set was created from a structural taxonomy using a
combination of keyword and semantic searches.
• The quality of the properties in the neighborhood was ranked. The data
set was refined using a filtering algorithm based on the context of patent
quality and acquisition.
• A shortlist was created to tour. Patents assigned to several small entities
were identified that met the quality criteria and that might available for
acquisition… patents or companies.
• Further refinement - include citation analysis and class code mining to
expand the initial pool before filtering on quality; incorporate claim
element/word count based scoring in the quality algorithm.
39Patent technics
Innography
www.innography.com
Patent Information Users Group
www.piug.org
CTEA