Download - Sample and Hold Circuit Basics
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Ste han Henzler Mixed-Si nal-Electronics 2011/12
Mixed-Signal-Electronics
PD Dr.-Ing. Stephan Henzler
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Supply Voltages of Mixed Signal Circuits
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General case: use of bipolar signals
VDD
AGND
VSS
most positive potential
analog ground / reference voltage
(reference point for analog signals)
most negative potential
positive signals
negative signals
Even more complex supply concepts in use check for available voltages and definitions before starting with design
+2V
-2V
0V
4V
0V
2V
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Transistor Description (for hand calculations)
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MOS Transistor as Switch
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VDDVSS
C o n d u t a n c e G
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Sample and Hold Circuits
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Chapter 2
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Sample & Hold Circuit
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Sample & Hold Circuit (cont)
1. Finite rise-time / finite bandwidth due to RC constant
2. Amplifier dynamics
(finite settling time, overshoot, ringing)
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Sample & Hold: Clock Feed-Through
3. Clock feed-through due to capacitive coupling.
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Sample & Hold: Charge Injection
4. Charge Injection: mobile carriers are removed
1:1 distribution is a approximation for fast switching9
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Sample & Hold Circuit (cont)
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6. Clock jitter
7. Droop in hold mode: leakage currents discharge hold cap
8. Linearity
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S&H Output Signal
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Impact of Jitter on S&H Performance
Consider a sinusoidal signal
Signal power
Rate of change
Jitter = random variation of sampling instance
Sampling error:
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Impact of Jitter on S&H Performance
Noise power resulting from sampling error
Signal-to-Noise Ratio
maximum achievable SNR for given jitter
frequency dependent, i.e. the larger the bandwidth the higher
the clock requirements13
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Impact of Offset-Voltage
Offset voltage of opamp is modeled as voltage source inseries to input terminal
Offset voltage is directly visible at output terminal
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Vo
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S&H with Correlated Double Sampling
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Noise in Discrete Time Systems
Noise is a random process statistical description is required
time domain: noise signal a(t)
frequency domain: power spectral density
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Noise of Sampled Signals
– kT/C-Noise –
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Remarks:
• Sampling makes this a little bit more complicated as noise is a wide band signal so there is aliasing of replica
spectra. However, the noise power in the baseband is still kT/C
• This is only a lower bound of noise power, buffers contribute also to overall noise power
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Closed Loop Track & Hold Circuit 1
Basic sampling circuit is embedded in feedback loop
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Very high input impedance – Reduction of non-idealities (e.g. buffer offset) by loop gain
– Loop must be designed stable speed degradation
– Feedback is broken during hold mode
• Input opamp saturates
• Long slewing time when circuit returns to track mode18
not critical wrt. offset errorsoffset not canceled
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Closed Loop Track & Hold Circuit 2
Hold mode:
Input opamp is configured as voltage follower
fast settling when circuit returns to track mode
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Closed Loop Track & Hold Circuit 3
Storage capacitor is shifted to feedback loop of output
amplifier (integrator) Swing across switch is always near to AGND
Error injection becomes nearly signal independent (pedestal error)
No appertur jitter
Input opamp is grounded during hold phase fast settling when switched to track mode
signal feedthrough is minimized
Reduced speed due to stability requirements20
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Closed Loop Track & Hold Circuit 4
Additional error replica to avoid the pedestal error
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Summary Sample & Hold Circuits