RF Transmitter based on Frequency Synthesizer
F. Badets F. Badets 2010, May 26th
Outline
Introduction Transmitter integration challenges
Frequency Synthesizer Modulation Translationnal TX loop Modulation of sigma delta frequency synthesizer
2
Modulation of sigma delta frequency synthesizer Two point modulation
DDS and ILO based RF transmitter Injection Locked Oscillator 400 MHz DDS Bluetooth DDS/ILO based transmitter
I Q based RF transmitter
General expression of signal to be transmitted
Principle :
RF(t) =
RF(t)
Principle : Generation of I and Q in baseband Generation of RF signal using in phase and
quadrature Local Oscillator
3
Heterodyne Transmitter Architecture
D/AI(n)
PA
IF Filter
ImageFilter
LPF
Linear
IF LO In0°
90°
4
D/AQ(n) RF LO
LPF
Drawbacks : - needs one external high Q RF filter- Precision needed on IF image rejection mixer- 2 LOs : 2 PLLs- Linear PA : Power hungry
Homodyne Transmitter(1)
D/AI(n)
Q(n)
PARF LO
LPF
LPF
BPF Linear
In0°
90°
5
D/AQ(n)
LPF
Architecture :- Zero IF -> eliminates a filter- IQ modulator shifts the spectrum of baseband
signal directly to the Rf carrier frequency
Homodyne Transmiter(2)
D/AI(n)
Q(n)
PARF LO
LPF
LPF
BPF Linear
In0°
90°
6
D/AQ(n)
LPF
Mixers :- act as switches (lower noise)- work better when quickly switched- -> responsible for genration of odd harmonics- non linearity -> intermodulation products
Homodyne Transmitter(3)
D/AI(n)
Q(n)
PARF LO
LPF
LPF
BPF Linear
In0°
90°
7
D/AQ(n)
LPF
Mismatches:- DC at mixer input -> LO leakage- Phase and amplitude mismatch ->degrades
orthogonality: IQ leakage- need feedback or calibration to counteract mismatches
Homodyne Transmitter(4)
D/AI(n)
Q(n)
PARF LO
LPF
LPF
BPF Linear
In0°
90°
8
D/AQ(n)
LPF
DAC: - generates white noise over fs/2 bandwidth- Σ∆ : quantization noise pushed towards fs/2- output : NRZ like signal -> alias signal at each fs
harmonics. (upsampling or precompensation)- INL, DNL -> distortion
Homodyne Transmitter(5)
D/AI(n)
Q(n)
PARF LO
LPF
LPF
BPF Linear
In0°
90°
9
D/AQ(n)
LPF
LO and quadrature: - LO : twice RF frequency -> minimizing pulling- quadrature obtained using both rising and falling
edge of a divider by 2.
Homodyne Transmitter(6)
LO
LO_RF_I
LO_RF_Q
10
LO and quadrature: - any imbalance in LO rising and falling edge timing
degrades LO I&Q generations -> loss of orthogonality
Homodyne Transmitter(7)
D/AI(n)
Q(n)
PARF LO
LPF
BPF Linear
In0°
90°
11
D/AQ(n)
LPF
LO pulling: - PA leakage could lock by injection the LO (substate noise, power
supply, modulation of LO load impedance).- LO tracks the PA modulation especially outside PLL badnwidth. ->
corrupted signal at output
Homodyne Transmitter(8)
D/AI(n)
Q(n)
PARF LO
LPF
BPF Linear
In0°
90°
12
D/AQ(n)
LPF
PA and all others drivers: - must preserve enveloppe -> spectral regrowth- should be linear -> PA inefficient (40% at peak output power)- high DC power - power control
Polar RF transmitter (1)
RF transmission using a phase and an amplitude phase
))t(tcos()t(A)t(RF
)tsin().t(Q)tcos()t(I)t(RF
RF
RFRF
ϕ+ω=ω+ω=
13
))t(I)t(Q
arctan()t(
)t(Q)t(I)t(A 22
=ϕ
+=
Polar Transmitter (2)
PA
Modulated Power Supply
DC power
Linear amplifier
Driver
A
DSP
Amplitude Modulation
Phase Modulation
14
Phase modulator
PA
Non linear PA
Modulation
Principle :ls –l
- Generation of A and φ in baseband- A modulate the power supply of a saturated PA (good efficiency- Φ is provided at RF using PLL modulation
Polar Transmitter (3)
PA
Modulated Power Supply
DC power
Linear amplifier
Driver
A
DSP
Amplitude Modulation
Phase Modulation
15
Phase modulator
PA
Non linear PA
Modulation
PA:- Better efficiency obtained with saturated PA (> 60 %)- Modulation through a DC/DC converter -> efficiency depends on switching frequency (noise, AM bandwidth)-Distortion for low supply voltages- needsof predistortion or feedback correction
Polar Transmitter (4)
PA
Modulated Power Supply
DC power
Linear amplifier
Driver
A
DSP
Amplitude Modulation
Phase Modulation
16
Phase modulator
PA
Non linear PA
Modulation
Phase and amplitude combination:- To be effective, amplitude and phase modulations should
arrive in the same time.- The phase modulator using modulated PLL brings group
delay -> to be compensated
Polar Transmitter (5)
PA
Modulated Power Supply
DC power
Linear amplifier
Driver
A
DSP
Amplitude Modulation
Phase
17
Phase modulator
PA
Non linear PA
Phase Modulation
This presentation
Outline
Introduction Transmitter integration challenges
Frequency Synthesizer Modulation Translationnal TX loop Modulation of sigma delta frequency synthesizer
18
Modulation of sigma delta frequency synthesizer Two point modulation
DDS and ILO based RF transmitter Injection Locked Oscillator 400 MHz DDS Bluetooth DDS/ILO based transmitter
Offset PLL based Transmitter
D/AI(n)
TX VCO
LPF
LPF
LPF
LPF
IF LO In0°
90°
fVCO
fIF
19
D/AQ(n) PFD CP
RF LO
LPF
LPF
PAfVCO
fRF
Outline
Introduction Transmitter integration challenges
Frequency Synthesizer Modulation Translationnal TX loop Modulation of sigma delta frequency synthesizer
20
Modulation of sigma delta frequency synthesizer Two point modulation
DDS and ILO based RF transmitter Injection Locked Oscillator 400 MHz DDS Bluetooth DDS/ILO based transmitter
FSK modulation (1)
FSK : Frequency Shift Keying
Bit duration = Tb
f 0f 0f1f12
f∆∆∆∆−−−−==== f 0f2
2
f∆∆∆∆++++====
∆∆∆∆ f
f 0f 0
RF expression:
Modulation index : h = ∆ f/fb Phase deviation over one bit : π.∆f.Tbit
21
∫∆π+ω=t
00 )du)u(sftcos(A)t(RF
MSK modulation
When FSK modulation index = 0.5 -> MSK Phase deviation over one Tbit : 90o
0
90
0 1 1 1 1 10 0 0 0 0 0 0 0train
binairemodulant
BinaryTrain
22
-360
-270
-180
-90
0
temps (s)
phas
e (°
)
MSK
GMSK
time
GMSK modulation(2)
FSK spectral occupation :
GMSK : filtering data using a gaussain filter in order to lower the spectral occupation without information loss
fT2
b
∆+
0
20MSK
23
-120
-100
-80
-60
-40
-20
0
-500 -400 -300 -200 -100 0 100 200 300 400 500
fréquence (kHz)
puis
san
ce (d
Bm
)
GMSK
Frequency (Hz)
Pow
er (
dbm
)
GMSK modulation(3)
24
BIT
bit
2BIT
2
2
T.B.2)2ln(
)t(fT2
T2
texp
Tbitt
rect
π=σ
=⋅σ⋅π
⋅σ⋅−
∗
Fractional N PLL based Transmitter
PFD CP
PrescalerN / N+1
LPF
PAfVCOfREF
25
Σ∆
Frac(Channel)ModulatingSignal
Filter
nnn
C
Int(channel)
reffREF
c2f ⋅∆=∆ ref
0vco f)
REFC
K(f ⋅+=
Gaussian Filter optimisation(2) Implementation of a digital gaussian filter
L=3*TBIT
R=8coeffic ients
par TBIT
réponse
L=4*TBIT
R=16coeffic ients
par TBIT
Theoritical
Determination of optimal impulse response length L and oversampling coefficient R.
Coefficient number: R*L
26
-4 -3 -2 -1 0 1 2 3 4t/TBIT
-4 -3 -2 -1 0 1 2 3 4t/TBIT
réponseimpulsionnelle
théorique
Theoriticalimpulse response
Gaussian Filter Optimisation(3)
Constraints on L&R Rmax = fref / fbit
Area occupied by digital filter Phase error due to the pulse response sampling
Reference filterϕref(t)ϕref(t)
27
modulating signal
Pseudo randoma(t)
156 bitsFBIT=270.8 kb/s
νref(t)
νL,R(t)
foversampling=R*f BIT
LL
+- Phase error
εεεεϕϕϕϕ
t
156*TBIT
t
156*TBIT2
∆fπ2 ××
2
∆fπ2 ××
digital filter∑
N
2Nx
N1 ∑
N
2Nx
N1
ϕL,R(t)
t
156*TBIT
N échantillons2∆f
π2 ××2∆f
π2 ××
Gaussian Filter Compensation
Before comparison, filters need to be compensated in
0
180360
540
720
9001080
1260
1440
0 2 4 6 8 10 12 14 16t/TBIT
(t) (°
)
filtre de référenceL=1 R=2L=1 R=8L=2 R=2L=2 R=8
0.00.10.20.30.40.50.60.70.80.91.0
0 2 4 6 8 10 12 14 16t/TBIT
(t)
filtre de référenceL=1 R=2L=1 R=8L=2 R=2L=2 R=8
Before comparison, filters need to be compensated in gain and group delay
28
0
180
360
540720
900
1080
1260
1440
0 2 4 6 8 10 12 14 16t/TBIT
(t)
filt re de référenceL=1 R=2L=1 R=8L=2 R=2L=2 R=8
0.00.10.20.30.40.50.60.70.80.91.0
0 2 4 6 8 10 12 14 16t/TBIT
(t)
filt re de référenceL=1 R=2L=1 R=8L=2 R=2L=2 R=8
Gaussian Filter Optimization
R
L
12.9 10.2 9.6 9.5 9.4
3.9 2.74 2.46 2.39 2.37
1.7 0.56 0.29 0.23 0.22
2 4 8 16 32
1
2
3
Table gives the quadratic phase error in degrees L=3 R=8 has been chosen
29
1.6 0.39 0.10 0.04 0.03
1.6 0.38 9.9E-2 3.8E-2 3.1E-2
1.6 0.38 9.9E-2 3.8E-2 3.1E-26
4
5
GMSK Modulator Implementation (1)
Gaussian filter of 3-bit impulse response could be seen as a sliding window of 3 bits and that concerns 4 bit
Fsliding windowlength L*Tbit
moving direction
TBIT
Idea: store in a ROM the filter response over 4 bits sequences (16 possibilities)
30
TBIT/R
GMSK Modulator implementation (2)
D entrée fixe du
convertisseur Σ∆Σ∆Σ∆Σ∆
D
D
registre àdécalage
adresseprincipale
ROM
FILTRE GAUSSIEN NUMERIQUE
n bits
Fref
Digital Gaussian Filter
Principal address
31
horloge de synchronisation provenant du
convertisseur Σ∆Σ∆Σ∆Σ∆
D
D
COMPTEUR
signalmodulant
adressesecondaire
entréeconvertisseur Σ∆
m bits
p bits
Modulating signal
Fref
Secondary addressCounter
GMSK modulator implementation (3)
50
150
250
350
1111 01111110
0110
1100
1101
1011
0011
32
-350
-250
-150
-50
0 1 2 3 4 5 6 7
1010
0010
1010
0000 10000001
PLL bandwidth influence on modulation (1)
33
PLL bandwidth influence on phase noise
GSM
Pha
se n
oise
34
Pha
se n
oise
PLL bandwidth tradeoff
0
5
10
15
20
25
30
50 70 90 110 130 150 170 190 210 230 250 270 290 310 330 350 370 390410 430 450 470 490 510 530 550B (kHz)
ϕϕ ϕϕm
ini (
° rm
s) Integrated error decreases with PLL bandwidth
35
0
1
2
3
4
5
6
7
8
50 70 90 110 130 150 170 190 210 230 250 270 290 310 330
B (kHz)
brui
t de
phas
e in
tég
ré ϕϕ ϕϕ
brui
t (°
rm
s)
Phase noise increases with PLL bandwidth
PLL bandwidth effect on GSMK modulation
36
Modulation Bandwidth Extension
GaussianFilter
Pre Distortion
Modulating Signal
Proportional to frac(Navg)
Predistortion filter to counteract the PLL bandwidth effect Needs to know and control the PLL transfer bandwidth
over PVT -> rather complicated
37
Filter filter
Flat Transfer Function
Outline
Introduction Transmitter integration challenges
Frequency Synthesizer Modulation Translationnal TX loop Modulation of sigma delta frequency synthesizer
38
Modulation of sigma delta frequency synthesizer Two point modulation
DDS and ILO based RF transmitter Injection Locked Oscillator 400 MHz DDS Bluetooth DDS/ILO based transmitter
Two Point Modulation Architecture
N
F(p) VCO
Principle : PLL is a high pass filter for VCO noise and a low pass filter for divider noise.
Idea : apply modulation on both divider and VCO to enlarge the modulation bandwidth
39
Modulated Divider Small Signal Model
Frequency step at divider output:
Frequency modulation due to divider modulus deviation:avg
fRe2
avg
VCOVCOVCO
Nf
N
fN
f1N
fdf −≈−≈−
+=
reff*)t(n)t(df −= fref*)t(n)t(m =
Integration in z domain then in laplace domain leads to:
40
avg
refref N
f*)t(n)t(df −=
avgN1
*p
)p(m2)p(d π−=φ
fref*)t(n)t(m =
Two Point Modulation : small signal analysis (1)
F(p)p
1Kv2π
p2Kv
2πGvm(p)
π2I
41
N
Modulation applied on another VCO varactor Modulation applied on feed back loop divider: modulates the
frequency need thus to be integrated in phase noise model
Gdiv p2π−m(p)
Output response for VCO modulation:
Output response for divider modulation
Two Point Modulation : small signal analysis (1)
)p(BO11
p)p(m
GK2 V2v1out +π=φ
)p(BO)p(mG=φ
Output response for modulation applied on both inputs
42
)p(BO1pGDiv2out +
=φ
))p(BO1
)p(BOGKG(
p)p(m
2 div2Vv1out2outout +
+π=φ+φ=φ
If Gdiv = 1 and Gv = 1/Kv2:
It is thus possible to use a frequency synthesizer as a modulator even for bandwidth signal greater than the PLL
Two Point Modulation : small signal analysis (2)
p)p(m
2out π=φ
modulator even for bandwidth signal greater than the PLL bandwidth
Accuracy of the method depends strongly on the accuracy of the gain Gv that should equal to the 1 over the VCO gain.
43
Example: GMSK modulation
GFSK 1Mb/s – modulation index 0.33 Gaussian filtering index BT = 0.5
44
Bluettooth Eye Diagram
Bluetooth specifies minimum openings of transmitted data eye diagram
45
PLL test bench
46
Modulation gain vs gain on VCO
47
Effect on eye Diagram
Modulation on divider only Modulation on VCO
48
Output PLL Modulation
Precision on VCO gain
49
• Precision on VCO gain degrades eye opening -> precision needed of 5 % • Need to calibrate the VCO gain before each transmission in a new channel
Outline
Introduction Transmitter integration challenges
Frequency Synthesizer Modulation Translationnal TX loop Modulation of sigma delta frequency synthesizer
50
Modulation of sigma delta frequency synthesizer Two point modulation
DDS and ILO based RF transmitter Injection Locked Oscillator 400 MHz DDS Bluetooth DDS/ILO based transmitter
Research context
Frequency synthesis and transmitter trend All digital Re-congirugability : going towards SDR: Software Defined
Radio
Try to be competitive with all digital PLL Try to be competitive with all digital PLL
Applications: phase modulator to be able to be embedded in polar TX – Able to transmit constant phase envelop modulations (GSM, Bluetooth…)
Proposed Architecture Fully Integrated Bluetooth
transmitter: Fully integrated Reference
Oscillator (based on BAW oscillator for example)
RF – DDS generating 500 MHz signal
Injection Locked Oscillator as
BAW
Reference
Oscillator
500 MHz Direct
Digital
Frequency
Synthesizer
ILO RF filter
PA
500 MHz 2.5GHz
52
Injection Locked Oscillator as a frequency multiplier
Advantages: No feed Back Loop Fully integrated Could be quickly Powered on Low phase group delay ->
easy to handle within polar TX
Digital GSM/Bluetooth Modulator
Proposed Architecture Fully Integrated Bluetooth
transmitter: Fully integrated Reference
Oscillator (based on BAW oscillator for example)
RF – DDS generating 500 MHz signal
Injection Locked Oscillator as
BAW
Reference
Oscillator
500 MHz Direct
Digital
Frequency
Synthesizer
ILO RF filter
PA
500 MHz 2.5GHz
53
Injection Locked Oscillator as a frequency multiplier
Advantages: No feed Back Loop Fully integrated Could be quickly Powered on Low phase group delay ->
easy to handle within polar TX
Digital GSM/Bluetooth Modulator
Outline
Introduction Transmitter integration challenges
Frequency Synthesizer Modulation Translationnal TX loop Modulation of sigma delta frequency synthesizer
54
Modulation of sigma delta frequency synthesizer Two point modulation
DDS and ILO based RF transmitter Injection Locked Oscillator 400 MHz DDS Bluetooth DDS/ILO based transmitter
Injection Locking Phenomenon
SSB phase noise
Free running oscillator
Locked oscillator
Phase noise
Free runningoscillator
Injectedsignal
f
Injectedsignal
fLOCK
Locked oscillator
fn
Locked oscillatortracking bandwidth
Locked oscillator acts as a 1 st order PLL
f0f
fLOCK
Locking range ∆ffL fH
Middle band High limitLow limit
Injection Locking Theory (1) - Huntoon & Weiss (1947 ) (*)
Solid fact Oscillator frequency is function of admittance load Y0 fILO = fct(Y0)
V0
I
OscillatorfILO
Y0ILOCK
fLOCK
OscillatorfILO
Y0 dy
Oscillator load
Injected signal
Modeled injected signal
0 ILO 0
Hypothesis Injected signal at fLOCK in the vicinity of f0 ILOCK magnitude small enough to not modify V0 magnitudeAssumption Locking source modeled by a small load admittance variation dy
β
=
⋅=∂∂= .j
FYY
F eEYf
E0
5
Injection Locking Theory (2) - Huntoon & Weiss (1947)
)cos(V
I.E)ff(
dtd
.21
0
LOCKF0LOCK β+φ⋅−−=φ⋅
π
ILO output phase
ILOLOCK φ−φ=φ
Huntoon & Weiss theory leads to:
0
LOCKF
V
IE2f
⋅⋅=∆
ILO locking range
Constant depending on oscillator structureand locking process
ILOLOCK
66
ILO Modulation
0ILOSYNC )t(n)t(m)t()t()t( φ+−=φ−φ=φ
( ))cos(
V
I.Ef
dttdm
21
fdtd
.21
0
LOCKF0LOCK β+φ⋅−
−
⋅π⋅
+=φ⋅π
)t(mt.f..2)t( LOCKLOCK +π=φ
0LOCKILO )t(nt.f..2)t( φ−+π=φ
Modulated locking signal phase
ILO output phase once locked
0ILOSYNC )t(n)t(m)t()t()t( φ+−=φ−φ=φ
nffj1
1)f(m)f(n
⋅+=
Assuming a small tracking phase error
( ) ( ) ( )[ ]tntmfdt
tdn21
n −⋅=⋅π⋅
Fourier Transform
( ) ( )20LOCK
2
n ff4f
f −−∆=
Tracking Phase Modulation
nffj1
1)f(m)f(n
⋅+=
Ability to track phase modulation
(dB)
ILO filtersmodulation
ILO tracks modulation
n(f)m(f)
20.logn(f)m(f)
20.log
Log 10(f) (Hz)0 dB
Modulation
ILO tracking bandwidth
-20 dB/dec
fnfLOCK
ILO Tracking Bandwidth( ) ( )2
0LOCK
2
n ff4f
f −−∆=
60
Tracking bandwidth depends on the difference between the Injected signal frequency and the ILO free running frequency
2-GHz Injection Locked Oscillator Design
AB0
LOCK
C41
VI
2f⋅π⋅
⋅⋅=∆ EF
VDD
L
M4
ILOCK
V0A B
M3
CAB=C+CM1+ CM2+CPARASITIC
∆f parameters known Optimized design possibleI0
C
L
M1 M2
V0
Injection Locking by a Sub-harmonic
Free running oscillator
dB
f0
f
∆f
fLOCK
FundamentalInjectionLocking
dB
f0
ffLOCK
∆f
5.fLOCK
Sub HarmonicInjectionLocking
Injected signal
Locked oscillator voltage
π==
.nI.2
II 0LOCKN
Locking source rich in nth harmonic
t
Locking current
I0
TLOCK TPULSE=α.TLOCK
Locked oscillator voltage
V0
T0
2-GHz Fifth SbILO Schematic
Pulse
Buffer
VDD
Oscillator Core
2-GHzoutput
500 ps
t 250 ps
t
2.5 ns
MP
VDD
L
M4M3
PulseGenerator
Buffer
BandgapCurrentSource
400-MHzinput
t
2.5 ns
250 ps
t
2.5 ns
t
500 ps
MP
MN
I0
C
M1 M2
2-GHz Fifth SbILO layout
350 µm
450
µm
Buffer
0.35-µµµµm BiCMOS STMicroelectronics technology
PulseGenerator
OscillatorCore
Band GapReference
Design Summary
PARAMETER VALUE Technology 0.35-µm BiCMOS STMicroelectronics
Voltage Supply 2.5 V
Current Consumption 16 mA
Output Buffers 15 mA Current Current
Consumption ILO Core + Pulse Generator + Bandgap Current Source
1 mA
Locking Range 400 MHz
Center Frequency 2 GHz
Chip Area (w/o pads and buffers) 0.160 mm2
Spectrum Measurements
-46.2 dB-46.0 dB
-32.3 dB-32.0 dB
1 MHz 1 MHz
+14 dB
1 MHz 1 MHz
SbILO input (400MHz) SbILO output (2GHz)10-mrad phase deviation 50-mrad phase deviation
-46.2 dB Measurement result-46.0 dB Bessel function of the first kind
S(t)=A.cos[n.ωC.t+n.Φ(t)] ≈ A.cos(n.ωC.t) - A.n.Φ(t).sin(n.ωC.t)
Phase multiplied by 5 20.log 10(5) = 14 dB
Spectrum Measurements
-23.6 dB-22.5 dB-49 dB
-50.9 dB
121 23 4
-9.2 dB-7.9 dB
-23.7 dB-22.2 dB
-41.3 dB-40.2 dB
-60.5 dB-60.6 dB
-46.2 dB Measurement result-46.0 dB Bessel function of he first kind
Large phase deviation requires Bessel functionsPhase deviation has to be multiplied by 5 at ILO output
SbILO input (400MHz) SbILO output (2GHz)150-mrad phase deviation 750-mrad phase deviation
Spectrum Measurements
1 MHz 5 MHzFreq. offset
x5
Frequency deviation widers spectrum by a ratio 5Carrier and offset between carrier and spurious are
multiplied by 5 at ILO output
SbILO input (400MHz) SbILO output (2GHz)500-kHz frequency deviation 2.5-MHz frequency deviation
Freq. carrier
x5
ILO : Proof of Concept (1)
69
ILO designed in BiCMOS6 as a multiplier by 5
ILO : Proof of Concept (2)
70
TEST MAXIMUM VALUES
REQUIRED
SBILO INPUT
SBILO OUTPUT
Phase Error (o rms)
5 0.22 0.26
Phase Error (o Peak)
20 0.83 0.85
ILO input ILO output
Conclusion ILO A theory on ILO modulation has been proposed
A fifth sub-harmonic injection locked oscillator designed Wide locking range: 400 MHz Center frequency: 2 GHz
Spectrum at SbILO output can be predicted for Low phase deviation with Bessel function or Taylor development Large phase deviation with Bessel function of the first kind Frequency deviation thanks to the ILO multiplication ratio
Phase error introduced by ILO once modulated negligeable
Outline
Introduction Transmitter integration challenges
Frequency Synthesizer Modulation Translationnal TX loop Modulation of sigma delta frequency synthesizer
72
Modulation of sigma delta frequency synthesizer Two point modulation
DDS and ILO based RF transmitter Injection Locked Oscillator 400 MHz DDS Bluetooth DDS/ILO based transmitter
Frequency synthesis could be seen as a phase modulation, where the modulated phase is a ramp.
400 MHz DDS Principle (1)
tf2)t(
))t(tcos(A)ttcos(A)tcos(A)t(V
1
0101RF
π=ϕϕ+ω=ω+ω=ω=
modulation, where the modulated phase is a ramp. The slope of the ramp is related to the frequency step Frequency synthesizer composed of
An RF clock A phase shifter that increments a value at each rising
edge of the clock
73
0
400 MHz DDS Principle (2)
φ(t)=β
0
TCLK
Phasor Time waveform
0
TDDS
0
400 MHz DDS Principle (2)
φ(t)=β
β0
TCLK
β
Phasor Time waveform
β0
TDDS
0
400 MHz DDS Principle (2)
φ(t)=β
β 2β0β
TCLK
2β
Phasor Time waveform
β 2β0
TDDS
400 MHz DDS Principle (2)
φ(t)=β
β 2β 3β0
TCLK
Phasor Time waveform
β 2β 3β0
TDDS
3β
400 MHz DDS Principle (2)
φ(t)=β
β 2β 3β0
TCLKTDDS=TCLK(1+ )
β
2π
Phase Accumulator:Digital context
Phase Interpolator:Analog Context
β 2β 3β0
TDDS
3β
400 MHz DDS architecture (1)
D
2n-phase Digitally Controlled Phase Shifter
Digital Phase Accumulator
n
79
CK
D
Adder
P
n
400 MHz DDS architecture (2)
Advantages ROM less High frequency (classical implementation output
frequency restricted to Fclock/2 at least)
Drawbacks Step frequency limited by the resolution of the digitally
controlled phase shifter Spurious response depends on the phase accuracy
80
Decreasing Step Frequency
Σ∆ modulator is used to decrease the step of
f0
f0+df
DDS
Y=<X>
fDDS
the DDS by switching ramdomly between two coarse frequencies
81
Σ∆
X
NSD
Outline
Introduction Transmitter integration challenges
Frequency Synthesizer Modulation Translationnal TX loop Modulation of sigma delta frequency synthesizer
82
Modulation of sigma delta frequency synthesizer Two point modulation
DDS and ILO based RF transmitter Injection Locked Oscillator 400 MHz DDS Bluetooth DDS/ILO based transmitter
DDS based RF transmitter principle
Σ∆
fDDS : DDS output frequency df : frequency step Σ∆ modulator synthesizes carrier frequency and shapes
quantification noise. An ILO will act as a frequency multiplier to get the RF signal
Frequency plan
GSM (x2) – DCS Frequency range: 1710 – 1830 MHz Frequency step: 0.1 ppm (170 Hz) ILO multiplication factor: 4 DDS frequency range 427.5 – 457.5 MHz DDS Frequency step: 42.5 Hz DDS Frequency step: 42.5 Hz
Bluetooth Frequency range: 2402 – 2480 MHz Frequency step: 1 ppm (2400 Hz) ILO multiplication factor: 5 DDS frequency range: 480.4 – 496 MHz DDS frequency step: 480 Hz
Σ∆
Bluetooth schematic
2450 MHz
K=5
490 MHz
Σ∆
Σ∆ generates 2NSD frequencies between f0 and f0+df
Transmitter modelization- Bluetooth
fILO=2.45 GHzfDDS=490 MHzRBW=100 kHz
Lowering df lowers the phase noise
Σ∆
GSM/DCS schematics
1800 MHz
K=4
450 MHz
Σ∆
Σ∆ modulator generates 2NSD frequencies between f0 and f0+df
Transmitter modelisation– GSM/DCS
fILO=1.8 GHzfDDS=450 MHzRBW=100 kHz
Modulations
fILO=1.8 GHzfDDS=450 MHzRBW=30 kHz
fILO=2.45 GHzfDDS=490 MHzRBW=100 kHz
GSMfBIT: 270.833 kb/sModulator oversampling: 64Symbols number: 148df: 400 kHz
BluetoothfBIT: 1 MHzModulator ovesampling: 32Symbols number: 50df: 400 kHz
Σ∆ and phase interpolation based DDS
Σ∆ and phase interpolation based DDS
DIGITAL ANALOG
RAZ
/4
State
Machine
Phase
Accumulator
0
max DAC
VREF
+
-
2 GHzLO
COMP
Σ∆
Fine Coarse
CAP
VREF
500 MHz
Reset
Capacitor charge with variable current
/4
State
Machine
Phase
Accumulator
0
max DAC
VREF
+
-
2 GHzLO
COMP
Σ∆
Fine Coarse
CAP
VREF
500 MHz
Reset
Capacitor charge with Imax
/4
State
Machine
Phase
Accumulator
0
max DAC
VREF
+
-
2 GHzLO
COMP
Σ∆
Fine Coarse
CAP
VREF
500 MHz
Reset
Phase interpolation
Variable
chargeReset
VREF MIN
Constant
charge
MA
X
t
TCLK
M
Synthesizer working process
Synthesizer working process
/4
State
Machine
Phase
Accumulator
Σ∆
0
max DAC
VREF
+
-
Reset
LO
C
VCAP VCOMP
Synthesizer working process
/4
State
Machine
Phase
Accumulator
Σ∆
0
max DAC
VREF
+
-
Reset
LO
C
VCAP VCOMP
Synthesizer working process
Synthesizer working process
Synthesizer working process
/4
State
Machine
Phase
Accumulator
Σ∆
0
max DAC
VREF
+
-
Reset
LO
C
VCAP VCOMP
Synthesizer working process
/4
State
Machine
Phase
Accumulator
Σ∆
0
max DAC
VREF
+
-
Reset
LO
C
VCAP VCOMP
Synthesizer working process
Synthesizer working process
Synthesizer working process
/4
State
Machine
Phase
Accumulator
Σ∆
0
max DAC
VREF
+
-
Reset
LO
C
VCAP VCOMP
Synthesizer working process
/4
State
Machine
Phase
Accumulator
Σ∆
0
max DAC
VREF
+
-
Reset
LO
C
VCAP VCOMP
Synthesizer working process
Synthesizer working process
tTCLK
VREF
Delay
VCAP
VCOMP
Time waveform
VREF
Combinaisons de l’interpolation de phase
28 - 1 phasesdans TCLK
CNA 8 bits
28 - 1combinaisons
t
TCLK TCLK
Detailed DDS bloc Diagramm
DDS frequencies calculation
1 phase interpolation each 4TCLK
(28 – 1) phases in TCLK
fDDS=P
fCLK
4 fCLK = 2 GHz
f /4 = 500 MHzP4(28-1)
(1 + )fCLK/4 = 500 MHz
P = 0 fDDS_MAX = 500 MHzP = 28-1 fDDS_MIN = 400 MHz
∆f ≈ 500 kHz
Σ∆ Combinations
Σ∆ 14 bits (MASH11)2 levels quantisizer
13 data bits+ 1 signe bit
213
Combinationover time
Detailed DDS bloc Diagramm
/4
State
Machine
Phase
Accumulator
0
max DAC
VREF
+
-
LO
C
VCAP VCOMP
P 8 bits
Σ∆
MASH11
ResetC
PSD
14 bits
PPA
8 bits
<PSD>
3 bits
Σ∆ advantages
P is composed of an integer part PPA and a fractional one PSD
∆fCOARSE ≈ 500 kHzfDDS=
P +PSD
fCLK
4
Diminution of frequency resolution Quantisizer noise shaping
∆fACCURATE≈ ∆fCOARSE/2^13≈ 60 Hz
PPA+213
PSD
4(28-1)(1 + )
DDS micrographCMOS 65-nm STMicroelectronics
Active ara: 0.1 mm2
Power supply: 1.2 VPower consumption:
29 mW (without buffers)
State machine, Σ∆,And phase accumulator
DecoupVref
50-ΩBufCAP
Vref
Reset
COMPCOMP500 And phase accumulatorP&R with standard cells
ClockTypcal: 2 GHzworst case: 2.8 GHz
package: TQFP 32
JTAG
Accu+Σ∆Accu+Σ∆Accu+Σ∆CNA
Reset
500 µm
300 µm
Frequency resolution0
-10
-20
-30
-40
-50
RBW: 10Hz
VBW: 10Hz60 Hz60 Hz60 Hz60 Hz
-50
-60
-70
-80
-90
-100 Span: 200 HzCenter: 496.511022 MHz
Phase Noise – LO / DDS
-110
-100
-90
-80
-70B
ruit
de p
hase
(dB
c/H
z)
2-GHz LO500-MHz DDS
Pha
se n
oise
-150
-140
-130
-120
-110
1,E+03 1,E+04 1,E+05 1,E+06 1,E+07 1,E+08
f (Hz)
Bru
it de
pha
se (
dBc/
Hz)
Pha
se n
oise
-110
-100
-90
-80
Bru
it de
pha
se (
dBc/
Hz)
Phase noise – with/ Σ∆
fIM = 500 MHz – fC ≈ 2.5 MHz
4.fIM
Pha
se n
oise
-150
-140
-130
-120
1,E+03 1,E+04 1,E+05 1,E+06 1,E+07 1,E+08
f (Hz)
Bru
it de
pha
se (
dBc/
Hz)
Avec Σ∆
Sans Σ∆
fC: 497.5 MHz
With
Without
Pha
se n
oise
Phase Noise – model/measure
-120
-110
-100
-90
-80
Bru
it de
pha
se (
dBc/
Hz)
Pha
se n
oise
fC: 497.5 MHz
-150
-140
-130
-120
1,E+03 1,E+04 1,E+05 1,E+06 1,E+07 1,E+08
f (Hz)
Bru
it de
pha
se (
dBc/
Hz)
ModèleMesureP
hase
noi
se
DDS output spectrum0
-10
-20
-30
-40
-50
RBW: 10kHz
VBW: 10kHz
AC: 8
68 dB
fC≈ 496 MHz
-50
-60
-70
-80
-90
-100 Span: 250 MHzCenter: 500 MHz
AC: 8SD: -31
~16 MHz
DDS state of the art Lindeberg
JSSC 2005
Daï JSSC 2006
Strollo JSSC 2007
Ce travail ASSCC 2007
Min 0 0 0 400 Fréquence de sortie (MHz) Max 100 150 315 500
Fréquence d’horloge (MHz) 200 300 630 2000
Sortie 1 bit CAN 1 bit
1 bit CNA 12 bits
13 bits quadrature
1 bit CNA 8 bits CAN 1 bit CNA 12 bits quadrature CNA 8 bits
Tension d’alimentation (V) 1.5 3.3 2.5 1.2
Puissance consommée (mW)
138 200 76 29
Technologie (µm) 0.13 0.35 0.25 0.065
Surface (mm2) 2,02 1.11 0.063 0.1
Figure de mérite (mW/MHz)
690 666 121 29
Transmitter Block Diagramm
+
-VREF
VCAPAccumulateur
de phaseLO CNA
ILO OUT
CAP
2 GHz400-500 MHz
2-2.5 GHz
1001
01
1101
• Output Frequency Range: 2 to 2.5 GHz• Frequency step : 300 Hz• RF filtering provided by ILO
Σ∆
ModulationCanalEmetteur001011000
01
Numérique Analogique
ILO frequency multiplication
ff1 f2f0
f5.f1 5.f25.f0
Signal injecté Sortie de l’ILO
ILO
x 5
Injected Signal ILO output
∆f ∆f 5. ∆f 5. ∆f
Schrinked Modulation Ouput ILO Modulation
ILO Design
12
LOCKIf∆ = ⋅ ⋅
0
12
4
LOCK
Total
If
V π C∆ = ⋅ ⋅
⋅ ⋅
Transmitter MicrographCMOS 65-nm STMicroelectronics
Active area: 0.25 mm2
Power Supply: 1.2 VDissipated Power:
37 mW (without output buffers)
DDS + ILODDS + ILO
ILO locking range programmableFrom 1 to 31 MHz
TQFP 48 package
Free Running and Locked – ILO Phase Noise
-110,00
-100,00
-90,00
-80,00
-70,00
-60,00
-50,00B
ruit
de p
hase
(dB
c/H
z)
ILO libre
ILO verrouillé (31)
Pha
se n
oise
-160,00
-150,00
-140,00
-130,00
-120,00
-110,00
1,E+03 1,E+04 1,E+05 1,E+06 1,E+07 1,E+08
f (Hz)
Bru
it de
pha
se (
dBc/
Hz)
ILO verrouillé (31)
DDS
ILO verrouillé (1)
Pha
se n
oise
Phase Noise for different ILO locking range
-130,00
-120,00
-110,00
-100,00B
ruit
de p
hase
(dB
c/H
z) Masque
ILO libre
Pha
se n
oise
-160,00
-150,00
-140,00
1,E+05 1,E+06 1,E+07 1,E+08
f (Hz)
Bru
it de
pha
se (
dBc/
Hz)
DDSLCK 31
LCK 8
LCK 4
LCK 1
Pha
se n
oise
Phase Noise Filtering – ILO/DDS
-15,00
-10,00
-5,00
0,00
5,00B
ruit
de p
hase
[DD
S +
14d
B -
ILO
]
LCK 31
-30,00
-25,00
-20,00
-15,00
1,E+04 1,E+05 1,E+06 1,E+07 1,E+08
f (Hz)
Bru
it de
pha
se [D
DS
+ 1
4dB
- IL
O]
LCK 1
LCK 4
LCK 8
Pha
se n
oise
Transmitter output spectrum
Locking Range= 1 MHz
Locking Range= 31 MHz
GSM 1 Bluetooth Modulation Plots
BluetoothModulation
GSMModulation
Conclusion
Innovative tansmitter based on Phase Shifter based pulse output DDS
Demonstrated feasabilitty from system to silicon Matlab modelization including mismatches DDS measurement
DDS output frequency from 400 MHz to 500 MHz DDS output frequency from 400 MHz to 500 MHz 60 Hz frequency resolution 29 mW
Transmitter Measurement Frequency band from 2 GHz à 2.5 GHz 300 Hz frequency resolution 37 mw
Acknowledgements
This presentation is based on Ph D work of L.Camino (modulation of Σ∆ fractional PLL) and T. Finateu (DDS –ILO based transmitter)
133