Re-programmable Prototyping Re-programmable Prototyping for Actel™ RTAX and RTSX space-for Actel™ RTAX and RTSX space-flight systems designs flight systems designs MAPLD 2009 PresentationMAPLD 2009 Presentation
Poster SessionPoster Session
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MAPLD 2009 – Poster Session
Today’s Prototyping SolutionToday’s Prototyping Solution
Socket + AX/SX-A ApproachGood solution, but several design iterations could require several of the OTP (One Time Programmable) or Actel AX/SX-A commercial chips to complete the design.
Weak PointThe potential risk for using several of these OTP or AX/SX-A devices could add to the overall project cost and impact the budget.
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MAPLD 2009 – Poster Session
Today’s Prototyping Design FlowToday’s Prototyping Design Flow
Create and Verify Design Code
Create and Verify Design Code
Synthesize and Implement for OTP chip
Synthesize and Implement for OTP chip
Test in Hardware:Results OK?
Throw AwayOTP Chip!
Throw AwayOTP Chip!
Synthesize and Implement for target technology
Synthesize and Implement for target technology
Final Hardware Tests
Y
N
Modify and Verify Design Code
Modify and Verify Design Code
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MAPLD 2009 – Poster Session
Aldec Re-programmable SolutionAldec Re-programmable Solution
Ability to prototype RTAX-S/SL and RTSX-SU designs using re-programmable Actel Flash ProASIC®3E FPGA family chips
Adaptor board is footprint-compatible with the final RTAX-S/SL and RTSX-SU device
Programming connector (JTAG) allows on-the-fly reprogramming of the device without detaching the adaptor from the target PCB
EDIF netlist converter allows to migrate from RTAX-S/SL and RTSX-SU to ProASIC®3E FPGA easily
Design efficiency is achieved, saving Development Time and Costs
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MAPLD 2009 – Poster Session
Aldec Suggested Design Flow 1Aldec Suggested Design Flow 1
Create and Verify Design Code
Create and Verify Design Code
Synthesize and Implement for ProASIC® FPGA
Synthesize and Implement for ProASIC® FPGA
Test in Hardware:Results OK?
Modify and Verify Design Code
Modify and Verify Design Code
Synthesize and Implement for target technology
Synthesize and Implement for target technology
Final Hardware Tests
Y
N
Preferred flow for PURE HDL Designs
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MAPLD 2009 – Poster Session
Aldec Suggested Design Flow 2Aldec Suggested Design Flow 2
Generate netlist for target technology
Generate netlist for target technology
Netlist ConversionNetlist Conversion
Test in Hardware:Results OK?
Modify and Verify Design Code
Modify and Verify Design Code
Implement for target technology
Implement for target technology
Final Hardware Tests
Y
N
Flow for schematic and legacy designs
Implement for ProASIC® FPGAImplement for ProASIC® FPGA
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MAPLD 2009 – Poster Session
The Advantages of FlashThe Advantages of Flash
Word Select / Bias
Output
InputBit Select 1 Bit Select 2
SWITCH
Floating Gate
Flash
MEMORY•Erase•Program•Sense
VCC
A B
Word line
BitLine SRAM
BitLine
VCC
Smaller size: more switches for greater routing flexibility Low power: less capacitance and resistance Reprogrammable and non-volatile
is better for prototyping than SRAM-based FPGAs:
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MAPLD 2009 – Poster Session
ProASIC®3 FPGA Key Data Device Features
Devices range from 15,000 to 3 million system gates Up to 504 Kbits of true Dual-Port SRAM Up to 620 user I/Os Up to 6 PLLs 1 Kb User Flash memory (FlashRom) Secure ISP using on chip 128 bit AES
encryption/decryption Support for wide range of packages including
PQ, VQ, TQ, QN, FG RoHS compliant packages available
Offers pin compatibility across families for easy migration Support for various IO standards
Standard IO: LVTTL, LVCMOS, PCI Differential IO: LVPECL, LVDS…. Advanced IO: (ProASIC3E) : GTL, GTL+, HSTL, SSTL2, SSTL3….
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MAPLD 2009 – Poster Session
Prototyping Adaptors and ConverterPrototyping Adaptors and Converter
• ALDEC Prototyping Solution consists of two parts: Selection of Prototyping Adaptors
(designers picks adaptor according to the desired package of RTAX/RTSX chip and design size)
EDIF Netlist Converter(allows conversion of RTAS/RTSX netlist to ProASIC3 format,skipping synthesis stage and proceeding directly to implementation)
• Converter use is optional, but allows faster workflow in many design cases
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MAPLD 2009 – Poster Session
A3PE1500/3000-CQ256 AdaptorA3PE1500/3000-CQ256 Adaptor
Description Adaptor size: 43.07mm x 43.07mm
The following elements reside on the top part of the adaptor
Actel ProASIC3E device A3PE1500-FGG484 or A3PE3000-FGG484
JTAG connector
Capacitors, resistors
The following elements reside on the bottom part of the adaptor
Leads that mimic CQ256 package
Capacitors A3PE1500-FGG484or
A3PE3000-FGG484
JTAG Connector
Leads that mimic CQ256 package
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MAPLD 2009 – Poster Session
A3PE1500/3000-CQ352 AdaptorA3PE1500/3000-CQ352 Adaptor
Description Adaptor size: 55mm x 55mm
The following elements reside on the top part of the adaptor
Actel ProASIC3E FPGA device A3PE1500-FGG484 or A3PE3000-FGG484
JTAG connector
Power connector
Capacitors, resistors
The following elements reside on the bottom part of the adaptor
Leads that mimic CQ352 package
CapacitorsA3PE1500-FGG484or
A3PE3000-FGG484
JTAG Connector
Power Connector
Leads that mimic CQ352 package
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MAPLD 2009 – Poster Session
A3PE3000-CG624 AdaptorA3PE3000-CG624 Adaptor
Description Adaptor size: 32.5mm x 34mm
The following elements reside on the top part of the adaptor
Actel ProASIC3E FPGA device, A3PE3000-FGG896
JTAG connector
Capacitors, resistors
The following elements reside on the bottom part of the adaptor
Leads that mimic CG624 package
Capacitors
A3PE3000-FGG896
JTAG Connector
Ball grid array that mimics CG624 package
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MAPLD 2009 – Poster Session
RTAX4000S/SL-CQ352 AdaptorRTAX4000S/SL-CQ352 Adaptor
Description Adaptor size: 55mm x 55mm
The following elements reside on the top part of the Daughter Board AND Mother Board
Actel ProASIC3E FPGA device A3PE3000-FGG896
JTAG connector
Capacitors, resistors
The following elements reside on the Bottom part of the adaptor
Leads that mimic CQ352 package
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MAPLD 2009 – Poster Session
RTAX4000S/SL-CQ352 RTAX4000S/SL-CQ352
IO/Clocks
IO/Clocks
IO/Clocks
IO/ClocksIO/Clocks
IOIO
FP GA 1 M other B oard
FP GA 2D a u g h te r Bo a rd
C Q352RTA X-4000S
leads
I OI O
1 0 ( s i n g l e e n d e d )
1 4 7 ( s i n g l e e n d e d )
1 6 ( L V D S s u p p o r t e d )
1 5 0 ( L V D S s u p p o r t e d )
1 0 ( s i n g l e e n d e d )I O / C l o c k s H
igh
Sp
ee
d C
on
ne
cto
rsIO/Clocks
8x MMCX 8x MMCX
8 (s ingle ended) 8 (s ingle ended)
DescriptionCQ352 leads connected to FPGA1 on Mother Board (166 I/Os, 1:1 mapping), single ended and LVDS transmissions supported
FPGA2 on Daughter Board is connected to FPGA1 (on Mother Board) only
167 interconnections between FPGA1 and FPGA2 (single ended)
Additional 8 micro-coax connectors for each FPGA
External clocks can be delivered
Can be used as additional interconnections between FPGA1 and FPGA2
Adaptor Block Diagram
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MAPLD 2009 – Poster Session
Aldec RTAX-S/SL AdaptorsAldec RTAX-S/SL Adaptors
* The adaptor can be used to prototype the specified RTAX-S/SL device only if the customer design does not exceed the capacity of the flash device on top of the adaptor.
•**RTAX2000S–CG624
•*RTAX4000S–CQ352
•**•*RTAX2000S–CQ352
•*RTAX2000S–CQ256
•RTAX1000S–CG624
••RTAX1000S–CQ352
••RTAX250S–CQ352
A3PE3000-CG624A3PE3000-CQ352A3PE1500-CQ352A3PE1500-CQ256
ADAPTOR BOARD TO BE USED FOR PROTOTYPINGRTAX-S DEVICETO PROTOTYPE
** Industrial configurations available for CQ352 and CG624 adaptors
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MAPLD 2009 – Poster Session
RTSX-RTSX-SU PrototypingSU Prototyping
NEW Adaptors Description Stacked Architecture
Mother Board with Actel ProASIC3 FPGA and RTSX-SU compatible leads
Daughter Board with Power components and JTAG connector
Packages supported
CQ208
CQ256
CG624
1:1 I/O and bank mapping
Powered from the target board (through RTSX-SU pins)
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MAPLD 2009 – Poster Session
RTSX-SU DEVICETO PROTOTYPE
ADAPTOR BOARD TO BE USED FOR PROTOTYPING
Aldec RTSX-SU AdaptorsAldec RTSX-SU Adaptors
*The adaptor is available in ACT-RTSX-CG624-3V3 and ACT-RTSX-CG624-5V option
RT54SX72SU-CG624
RT54SX72SU-CQ256
•RT54SX72SU-CQ208
•RT54SX32SU–CQ256
ACT-RTSX-CG624ACT-RTSX-CQ256ACT-RTSX-CQ208
••
•*
RT54SX32SU–CQ208 •
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MAPLD 2009 – Poster Session
RTAX2A3P EDIF Netlist ConverterRTAX2A3P EDIF Netlist Converter
RTAX2A3P EDIF Netlist Converterperforms automatic conversion ofthe RTAX-S/SL and RTSX-SUEDIF netlist to ProASIC3E FPGAEDIF netlist
Features Conversion of combinatorial primitives
Conversion of sequential primitives
Conversion of I/O macros
Memory conversion
Replacement of sequential primitives to TMR primitives
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MAPLD 2009 – Poster Session
RTAX2A3P EDIF Netlist ConverterRTAX2A3P EDIF Netlist Converter
Input RTAX-S/SL or RTSX-SU EDIF netlist RTAX-S/SL or RTSX-SU PDC file
Output ProASIC3E FPGA EDIF netlist ProASIC3E FPGA PDC file for selected
adaptor board
RTAX and RTSX to ProASIC3E FPGA
Converter
PrimitivesLibrary
Implementation for ProASIC3E FPGA in Actel Designer
RTAX-S/SLRTSX-SU
EDIF netlist
Pin LocationLibrary
RTAX-S/SL RTSX-SU PDC file
ProASIC3E FPGA EDIF
netlist
ProASIC3E FPGA PDC
file
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MAPLD 2009 – Poster Session
RTAX2A3P EDIF Netlist ConverterRTAX2A3P EDIF Netlist Converter
Primitives Mapping
Number of RTAX-S
primitives
Number of ProASIC3E
FPGA primitives
Best Case mapping 1 1
Worst Case mapping 1 2.5
Average mapping 1 1.5
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MAPLD 2009 – Poster Session
SummarySummary Reduce chip costs Save Development Time – “Re-Programmability” ProASIC®3 FPGA “flash-based” technology Wide Device & Package Support: CQ208, CQ256, CQ352 &
CG624 packages Footprint compatible adaptors Automatic translation of netlist, memories and constraints Customer proven with over 100 units shipped worldwide