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Qsys and IP Core Integration
Prof. David Lariviere
Columbia University
Spring 2014
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Overview
What are IP Cores?Altera Design Tools for using and integrating IP CoresOverview of various IP Core Interconnect Fabrics
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Cyclone V SoC - Mix of Hard and Soft IP Cores
Source: Altera
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IP Core
"In electronic design a semiconductor intellectual propertycore, IP core, or IP block is a reusable unit of logic, cell, orchip layout design that is the intellectual property of oneparty... The term is derived from the licensing of the patentand/or source code copyright that exist in the design. IPcores can be used as building blocks within ASIC chipdesigns or FPGA logic designs."Source: Wikipedia: Semiconductor Intellectual Property Core
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IP Core Types - Hard vs. Soft
"Hard" IP: Dedicated ASIC blocks within the FPGA targetingspecific functionality
"Soft" IP: Implemented using the general purposeconfigurable fabric of the FPGA
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Example IP Cores
CPUs: either hard (ARM SoC) or soft-core (Nios II)
Highspeed I/O: Hard IP Blocks for High Speed Transceivers(PCI Express, 10Gb Ethernet, etc)
Memory Controllers: (onboard SRAMs, external DDR3, etc)
Clock and Reset signal generation: (PLLs)
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Cyclone V SoC - FPGA layout
Source: Altera
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Cyclone V SoC - HPS Layout
Source: NARD, LLC.
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Stratix V - FPGA Layout
Source: Altera
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Stratix V - Solarflare AoE PCB Layout
Source: Solarflare FDK
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Stratix V - Solarflare AoE Qsys Layout
Source: Solarflare FDK
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Stratix V - Solarflare AoE Qsys Example
Source: Solarflare FDK
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Bridges
Purpose: modify how data is transported betweencomponents.
Allows for: different clock domains, protocol conversion(AXI <–> Avalon), pipelining, bus width adaptation, etc
Bridge Types:
SOC HPS <–> FPGA Bridge
Avalon MM Clock Crossing Bridge
Avalon MM Pipeline Bridge
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Cyclone V SoC: FPGA <–> HPS Bridge
Source: Altera
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Clock Crossing Bridge Example
Source: Altera
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Pipeline Bridge Example
Source: Altera
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Altera Tools for IP Cores
Megawizard
SOPC Builder: System-on-Chip (SoC); old, replaced by Qsys
Qsys: Network-on-Chip (NoC).
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Megawizard
Source: Altera
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Megawizard - Example 10Gb Ethernet PHY
Source: Altera
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Megawizard IP CoresArithmetic: Addition, Subtraction, Multiplication, Division,Multiply-(add|accumulate), ECC
Floating Point:
Gate Functions: Shift Registers, Decoders, Multiplexers
I/O Functions: PLL, temp sensor, remote update, varioushigh speed transceiver related
Memory: (Single|Dual)-port RAM or ROMs,(Single|Dual)-clock FIFOs, (RAM) Shift registers
DSP: FFT, ECC, FIR, etc (large suite specifically for graphics aswell)
Note: availability of specific megafunctions is FPGA specific(may only be available on Stratix V but no Cyclone V SoC,etc)
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Qsys
Qsys is Altera’s system integration tool for buildingNetwork-on-Chip (NoC) designs connecting multiple IPcores.
It replaces SOPC Builder (previous version of the tool).
You utilize Qsys to construct a system of IP components (andeven system of systems), and Qsys will automaticallygenerate the interconnect, add required adaptation, warnon misconfigurations, etc.
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Qsys - Raising Level of Abstraction
Source: Altera
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Qsys UI
Source: Altera
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System Level Design - Why use Qsys
Avoids manually developing custom interconnect fabricsand signaling.
Instead of cycle-to-cycle coordination between everyindividual IP core, focus on ’transaction’ level designs.
Design IP without knowing exactly when data will transferand instead only focus on how (once it does).
(Only valid if you design your individual components to oneof the standardized interfaces)
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Old (Manual) Method of Design
Source: Altera
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Qsys-based Method of Design
Source: Altera
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Interface Types
Memory-mapped Interfaces:Avalon MM (Altera)AXI (ARM, supported by Qsys now for SoC)
Streaming Interfaces: Avalon ST:
Avalon ST source port: outputs streaming data
Avalon ST sink port: receives incoming streaming data
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"Control" vs. "Data" Planes
Control Plane: Memory mapped registers typically used forconfiguring devices, querying status, initiating transactions,etc (low bandwidth)
Data Plane: Streaming directed graphs for actually movingand processing large amounts of data (audio/video,network packets, etc); high bandwidth
A single IP core can have both MM and ST interfaces(including multiple of each).
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Control and Data Planes Example
Source: Altera
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Control and Data Planes Example - Solarflare AoE
Source: Altera
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Qsys signal types
Clock
Reset
Interrupt
Avalon MM signals
Avalon ST signals
Tristate
Conduit (avoid unless truly not one of the above)
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Why explicitly label signal types?
...vs. simply making everything a wire/conduit
Allows Qsys to protect you from yourself!
Ensure matching between signal types ("clock out" –>"clock in", etc)
Detect and automatically insert dual clock crossing domains(only if it knows which clock domains IPs are in)
Automatically convert data widths, formats, error flags(convert 32 bit master into four 8-bit slave reads, etc)
Automatically synchronize and OR-gate multiple resets
Automatically insert pipeline stages to improve fmax
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Avalon MM Master Signals
Source: Altera
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Avalon MM Slave Signals
Source: Altera
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Avalon ST Signals
Source: Altera
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Example Qsys Layout - 10Gb Reference Design
Source: Altera
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Advanced - Qsys Hierarchical Designs
Source: Altera
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Advanced - Qsys Automatic Pipelining
Source: Altera
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Advanced - Qsys Testbench Generation
Source: Altera
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Additional References
Altera online training lectures: (HIGHLY recommended;many of these slides are taken directly from them)
http://www.altera.com/education/training/curriculum/trn-curriculum.html
Introduction to Qsys
Advanced System Design Using Qsys
Custom IP Development Using Avalon and AXI Interfaces