Interconnect Planning, Synthesis, Interconnect Planning, Synthesis, and Layout for Performance, Signal and Layout for Performance, Signal
Reliability and Cost OptimizationReliability and Cost Optimization
SRC Task ID: 605.001SRC Task ID: 605.001
PI: Prof. Jason Cong (UCLA)Graduate Students: Chin-Chih Chang, David Pan, Xin Yuan
Industrial Liaisons: Dr. Prakash Arunachalam (Intel) Dr. Norman Chang (HP)
Dr. Wilm Donath (IBM) Dr. Stefan Rusu (Intel)SRC Monitor: Lawrence Arledge (SRC)
Project Overview
Objective: investigate an interconnect-centric
design flow and methodology, consisting of:
Interconnect Planning
Interconnect Synthesis
Interconnect Layout
Overview of Interconnect-Centric IC Design Flow
Architecture/Conceptual-level Design
Design Specification
Final Layout
abstractionStructure viewFunctional viewPhysical viewTiming view
HDM
Synthesis and Placement under Physical Hierarchy
Interconnect Planning•Physical Hierarchy Generation•Foorplan/Coarse Placement with Interconnect Planning•Interconnect Architecture Planning
Interconnect Optimization (TRIO)
• Topology Optimization with Buffer Insertion• Wire sizing and spacing• Simultaneous Buffer Insertion and Wire Sizing• Simultaneous Topology Construction with Buffer Insertion and Wire Sizing
Interconnect LayoutRoute Planning
Point-to-Point Gridless Routing
Interconnect Performance Estimation Models (IPEM)
•OWS, SDWS, BISWS
Interconnect SynthesisPerformance-driven Global Routing
Pseudo Pin Assignment under Noise Control
Overview of Interconnect-Centric IC Design Flow
Architecture/Conceptual-level Design
Design Specification
Final Layout
abstractionStructure viewFunctional viewPhysical viewTiming view
HDM
Synthesis and Placement under Physical Hierarchy
Interconnect Planning•Physical Hierarchy Generation•Foorplan/Coarse Placement with Interconnect Planning•Interconnect Architecture Planning
Interconnect Optimization (TRIO)
• Topology Optimization with Buffer Insertion• Wire sizing and spacing• Simultaneous Buffer Insertion and Wire Sizing• Simultaneous Topology Construction with Buffer Insertion and Wire Sizing
Interconnect LayoutRoute Planning
Point-to-Point Gridless Routing
Interconnect Performance Estimation Models (IPEM)
•OWS, SDWS, BISWS
Interconnect SynthesisPerformance-driven Global Routing
Pseudo Pin Assignment under Noise Control
Interconnect Synthesis
Performance-driven Global Routing
Pseudo Pin Assignment under Noise Control
Interconnect LayoutRoute Planning
Point-to-Point Gridless Routing
Interconnect Performance Estimation Models (IPEM)
• OWS• SDWS• BISWS
Interconnect Optimization (TRIO)
• Topology Optimization with Buffer Insertion• Wire sizing and spacing• Simultaneous Buffer Insertion and Wire Sizing• Simultaneous Topology Construction with Buffer Insertion and Wire Sizing
Interconnect Planning
• Physical Hierarchy Generation• Foorplan/Coarse Placement with Interconnect Planning• Interconnect Architecture Planning
Overview of Interconnect-Centric IC Design Flow
Architecture/Conceptual-level Design
Design Specification
Final Layout
abstractionStructure viewFunctional viewPhysical viewTiming view
HDM
Synthesis and Placement under Physical Hierarchy
Interconnect Planning•Physical Hierarchy Generation•Foorplan/Coarse Placement with Interconnect Planning•Interconnect Architecture Planning
Interconnect Optimization (TRIO)
• Topology Optimization with Buffer Insertion• Wire sizing and spacing• Simultaneous Buffer Insertion and Wire Sizing• Simultaneous Topology Construction with Buffer Insertion and Wire Sizing
Interconnect LayoutRoute Planning
Point-to-Point Gridless Routing
Interconnect Performance Estimation Models (IPEM)
•OWS, SDWS, BISWS
Interconnect SynthesisPerformance-driven Global Routing
Pseudo Pin Assignment under Noise Control
Review: Accomplishments in Year 1& 2
Efficient (constant time) and accurate (90%) interconnect delay estimation models for 2-pin nets under different interconnect optimization algorithms [Cong-Pan, IWLS’98, SRC/TECHCON’98,
ASPDAC’99]
Interconnect architecture planning [Cong-Pan,DAC’99]
Efficient and accurate interconnect estimation models for multiple-pin nets [Cong-Pan, TAU’99]
Buffer block planning for interconnect-driven floorplanning [Cong-Kong-Pan, ICCAD’99]
Accomplishments and Ongoing Works in Year 3
An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00]
Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00]
Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00]
Ongoing studies on physical planning
Accomplishments and Ongoing Works in Year 3
An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00]
Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00]
Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00]
Ongoing studies on physical planning
Crosstalk Noise
0
0.2
0.4
0.6
0 0.5 1 1.5 2 2.5
Time (ns)
Vo
ltag
e S
pik
e (V
)
Cx
Victim net
Aggressor net
Previous Works Transmission line equations [Sakurai+, TED’93, ASPDAC’98]
Only handle fully coupled bus lines Devgan’s model [ICCAD’97]
Elegant, Elmore-like formula for peak noise Over estimation, esp. when aggressor slew is small => could lead
to noise even larger than Vdd ! Charge-sharing based (e.g., [Vittal & Marek-Sodawska,
TCAD’97]) One lumped R, C for victim/aggressor net Simple noise formulae for peak noise, and noise amplitude-width
product Cannot differ near-source versus near-sink coupling
Need simple yet accurate model that considers more KEY (but not more than necessary) parameters to guide layout optimization !
2- Crosstalk Noise Model [Cong-Pan-Srinivas, SRC Techcon’00,
TAU’00]
Cx
Victim net
Aggressor net
Ls Le Cl
Cs1
Tr
Rd Rs
Ce1Cs2
Ce2Cl
Re
Lc
2- Model
C1=Cs1
Rd Rs
C2=Cs2+Ce1 CL=Ce2+Cl
Re
Cs1
TrRd Rs
Ce1Cs2
Ce2Cl
Re
Closed-Form Solutions
Peak noise
vr
r
x ttet
tv /1max
vr
vr
vrwidthtte
ttettt
/1
/21ln
Let1e12 R))((
)(
CCRCCCxRRt
CRRt
dLsdv
xsdx
tx: RC delay from upstream resistance times coupling cap.tv: Elmore delay of the victim net
Noise widthNoise width
Unified View for Existing Models
Peak noise
vr
r
x ttet
tv /1max
As v
xr
t
tvt max , then0
(Vittal+ TCAD’97 model)
As r
xvr
t
tvtt max , then (Devgan ICCAD’97 model)
(2- model)
221
1
1
2
11/1max
rv
x
v
rv
x
v
r
v
xvr
r
x
tt
t
ttt
t
t
t
t
tttet
tv
As
(Vittal+ TCAD’99 model,Up to 100% larger than Devgan metric for large tr)
Experimental Results
1,000 random nets based on realistic parameters
Average Error (%)
0
100
200
300
400
500
600
700
devgan vittal 2-Pi
Model
Perc
enta
ge
Average Error (%)
0
2
4
6
8
10
12
14
16
18
vittal 2-Pi
Model
Perc
enta
ge
Applications of 2- Model
We have obtained a set of rules for noise reduction using different interconnect optimizations Driver sizing Near source versus sink coupling Shield insertion Wire sizing and spacing AW product (noise amplitude • width)
Used in Magma’s BlastFusion software -- U.S. Patent Pending
Accomplishments and Ongoing Works in Year 3
An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00]
Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00]
Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00]
Ongoing studies on physical planning
Overview of Interconnect-Centric IC Design Flow
Architecture/Conceptual-level Design
Design Specification
Final Layout
abstractionStructure viewFunctional viewPhysical viewTiming view
HDM
Synthesis and Placement under Physical Hierarchy
Interconnect Planning•Physical Hierarchy Generation•Foorplan/Coarse Placement with Interconnect Planning•Interconnect Architecture Planning
Interconnect Optimization (TRIO)
• Topology Optimization with Buffer Insertion• Wire sizing and spacing• Simultaneous Buffer Insertion and Wire Sizing• Simultaneous Topology Construction with Buffer Insertion and Wire Sizing
Interconnect LayoutRoute Planning
Point-to-Point Gridless Routing
Interconnect Performance Estimation Models (IPEM)
•OWS, SDWS, BISWS
Interconnect SynthesisPerformance-driven Global Routing
Pseudo Pin Assignment under Noise Control
Coupling: 4 Coupling: 2
Pseudo Pin Assignment with Crosstalk Noise Control
Pseudo pin: a point where a net crosses a tile boundary Pseudo pin assignment: bridge between global routing
and detailed routing Our contributions: Pseudo pin assignment algorithm
for gridless general area routing with noise control Control crosstalk noise Handle obstacle constraints Align pseudo pins for detailed routing routability Reduce the total wire length
Vias: 6 Vias: 8
Why Crosstalk Noise Control in Pseudo Pin Assignment
What can we do in routing to affect crosstalk? Buffer insertion (if the global router does it) Wire ordering Wire spacing
Determine wire ordering and spacing Global routing? High complexity, hard to consider obstacles Detailed routing? Flexibility is low Pseudo pin assignment? Reasonable complexity and high
accuracy
PPA Algorithm Overview
One layer at a time Optimize one row at a time
Maximum strip boundary decomposition:
Partition boundary to intervals
Coarse pseudo pin assignment:
Assign pseudo pins to intervals
Detailed assignment within each “strip”:
Determine pseudo pin locations
A Noise Distribution Example – After Detailed Routing
0500
10001500200025003000350040004500
nets
0-0.1 0.1-0.2
0.2-0.3
0.3-0.4
0.4-0.5
noise (Vdd)
no noise control
with noisecontrol
Test case: scaled mcc2, NTRS’97 0.18 um Tech, 0.3 Vdd noise constraints
Pseudo pin assignment with noise control effectively reduce crosstalk noise and meet noise constraints
Accomplishments and Ongoing Works in Year 3
An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00]
Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00]
Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00]
Ongoing studies on physical planning
Motivations for Routing Tree Construction under Fixed Buffer Locations
Given buffer blocks planned in early stage, how to do routing and buffer insertion under fixed buffer locations?
Investigate different buffer block planning schemes.
An Example of Floorplan with Buffer Block Planning
sink
hard block or IP
buffer blockobstacle
source
RMP (Recursively Merging and Pruning) Algorithm
Basic Idea: A bottom-up tree construction combined with
buffer insertion. Generate a set of subtrees from sinks and then
gradually expand and merge them until a complete tree with best performance is produced.
Key differences from previous approaches The sets of subtrees may not be disjoint Multiple subtrees may be generated at a node Works on a routing graph Handle multiple-pin nets with fixed buffer
locations constraints.
Comparison BetweenRMP and Modified BA-tree Algorithm
Modify BA-tree algorithm [TRIO] to handle fixed buffer insertion (MBA-tree) Similar to the semi-automatic approach used in real design: “round” ideal buffers in
BA-tree to the given buffers in MBA-tree.
#pinsRMP MBA-tree
(adjacent NR)MBA-tree
(t-adjacent NR)rat wl rat wl rat wl
4 1.0 1.0 1.62 0.90 1.29 1.08
5 1.0 1.0 1.99 0.90 1.46 1.13
6 1.0 1.0 1.84 0.85 1.29 0.97
Experimental results of RMP vs. BMA-tree (all data are normalized with respect to RMP).
RMP can outperform MBA-tree by up to 50% in terms of delay with comparable wirelength.
Accomplishments and Ongoing Works in Year 3
An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00]
Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00]
Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00]
Further study on physical planning
Ongoing Studies on Physical Planning
Motivation Logical hierarchy is different to physical hierarchy Planning based on logical hierarchy is limited by
floorplanning on logical hierarchy Planning based on physical hierarchy with
performance driven geometric embedded partitioning shows good promises [Cong-Lim ICCAD’00]
Further study on interconnect planning in physical hierarchy
Example of Logic Hierarchy in Final Layout
By courtesy of IBM (Tony Drumm)
Example of Logic Hierarchy in Final Layout
By courtesy of IBM (Tony Drumm)
Several Ongoing Efforts
Studies on the impacts of layer assignment
Studies on the congestion of global interconnect
A reasonable formulation for physical planning
Impacts of Layer Assignments on Delays
0
200
400
600
800
1000
1200
1400
1600
wire length (mm)
dela
y (p
s)
layer 1-2layer 3-4layer 5-6layer 7-8
Delays estimated by IPEM for optimal buffer insertion and wire sizing
0.13 um NTRS’97 technology Delay reduction of changing wires
from layers 1-2 to layers 7-8: 0.5mm: 2% 6.5mm: 40% 27.5mm: 49%
The longer the wire, the more possible reduction by assigning to upper metals
Several Ongoing Efforts
Studies on the impacts of layer assignment
Studies on the congestion of global interconnect
A reasonable formulation for physical planning
Congestion Analysis – Efforts and Preliminary Results
Upper metal layers are used for long wires for reducing delays
Are there enough routing resource on upper metal layers? What is the trend? How many long wires that need to be routed on upper metal
layers? How much space available on upper metal layers (Power and
Clock nets are also competing)? List of industrial contacts that we consulted:
IBM – Tony Drumm, John Darringer Intel – Desmond Kirkpatrick, Mosur Mohan, Kris Konigsfeld HP – Norman Chang
Layer Competition under Different Target Delays (Test case from IBM)
Wire area requirements under different target delays using IPEM with 0.13um NTRS'97 Tech
050
100150200250300350
target delay(ps)
area
delay not meetlayer 7-8 or abovelayer 5-6 or abovelayer 3-4 or abovelayer 1-2 or above
Several Ongoing Efforts
Studies on the impacts of layer assignment
Studies on the congestion of global interconnect
A reasonable formulation for physical planning
Problem Formulation for Physical Planning
Plan the following to achieve optimization goals: Physical hierarchy with rough geometric information for
identifying global interconnects Retiming and pipelining Layer assignment for global interconnects Global net topology generation and congestion control Buffer planning …
Estimate and Optimize the following objectives: Delay Area Power Signal integrity
Deliverables Development of efficient and accurate interconnect performance
estimation models for interconnect-driven synthesis and planning (Completed - 30-Jun-1999)
Development of interconnect architecture planning framework (Completed - 30-Jun-1999)
Development of efficient algorithms for integrated interconnect planning & floorplanning capabilities at the physical level (Completed - 30-Sep-1999)
Development & validation of accurate noise models to guide the interconnect synthesis algorithm for signal reliability (Completed - 31-Dec-1999)
Development of optimal or near-optimal interconnect synthesis algorithm for multiple spatially or temporally related signal nets for performance & signal reliability optimization (Completed - 31-Dec-1999)
Development of efficient algorithms for integrated interconnect planning & floorplanning capabilities at the RTL-level; Software (Planned - 31-Dec-2000)
Technology Transfer TRIO (Tree-Repeater-Interconnect-Optimization) package
Integrated into Intel design technology http://cadlab.cs.ucla.edu/~trio
IPEM (Interconnect Performance Estimation Model) package Integrated into IBM design technology http://cadlab.cs.ucla.edu/software_release/ipem/htdocs
Wire width planning U.S. Patent pending under SRC sponsorship
BBP (Buffer Block Planning) for physical level floorplanning Source code transferred to IBM Interests from Intel and HP
Crosstalk noise modeling U.S. Patent pending (joint with Magma)
Summary
An improved crosstalk model with application to noise constrained interconnect optimization.
Pseudo pin assignment with crosstalk noise control
Routing tree construction under fixed buffer locations
Ongoing studies on physical planning
Milestones Development of a computational model for interconnect architecture planning based
on a given design characterization (specified in terms of target clock rate, interconnect distribution, depths of logic,network, etc.) (31-Dec-1998)
Development of estimation models for interconnect layout optimizations suitable for pre-layout synthesis and planning (31-Dec-1998)
Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the RTL-level (31-Dec-1999)
Completion of the ongoing effort on the development on a multi-layer general-area gridless routing system (31-Dec-1999)
Development of optimal or near-optimal interconnect synthesis algorithm for multiple spatially or temporally related signal nets for performance and signal reliability optimization (31-Dec-1999)
Development and validation of very efficient but accurate noise models to relate the noise with the physical parameters to guide the interconnect synthesis algorithm for signal reliability optimization (31-Dec-1999)
Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the physical level (31-Dec-1999)
Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the RT-level (31-Dec-2000)