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ITRS MOSFET Scaling Trends, Challenges, and
Key Technology Innovations
Workshop on Frontiers of Extreme Computing
Santa Cruz, CA
October 24, 2005
Peter M. Zeitzoff
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Outline
Introduction MOSFET scaling and its impact
Material and process approaches andsolutions
Non-classical CMOS
Conclusions
SEMATECH, the SEMATECH logo, AMRC, Advanced Materials Research Center, ATDF, the ATDF logo, Advanced
Technology Development Facility, ISMI and International SEMATECH Manufacturing Initiative are servicemarks of
SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.
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Introduction IC Logic technology: following Moores Law by
rapidly scaling into deep submicron regime Increased speed and function density
Lower power dissipation and cost per function The scaling results in major MOSFET challenges,
including: Simultaneously maintaining satisfactory Ion(drive
current) and Ileak
High gate leakage current for very thin gate dielectrics Control of short channel effects (SCEs) for very small
transistors Power dissipation
Etc. Potential solutions & approaches:
Material and process (front end): high-k gate dielectric,metal gate electrodes, strained Si,
Structural: non-classical CMOS device structures
Many inno vat ions needed in rapid su ccession
I i l T h l R d f
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International Technology Roadmap forSemiconductors (ITRS) Industry-wide effort to map IC technology
generations for the next 15 years
Over 800 experts from around the world
From companies, consortia, and universities
For each calendar year
Projects scaling of technology characteristics andrequirements, based on meeting key Moores Law targets
Assesses key challenges and gaps
Lists best-known potential solutions
Projections are based on modeling, surveys, literature,experts technical judgment
This talk is based on both the 2003 ITRS and onpreliminary data from 2005 ITRS (not yet released)
O C f f
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Year of Production 2003 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018
Technology Node hp90 hp65 hp45 hp32 hp22
DRAM Pitch (nm) 100 90 80 70 65 57 50 45 35 32 25 22 18
MPU Physical
Gate Length
(nm)
45 37 32 28 25 22 20 18 14 13 10 9 7
Vdd (V) 1.2 1.2 1.1 1.1 1.1 1 1 1 0.9 0.9 0.8 0.8 0.7
Chip Frequency
(MHz)
On-chip local
clock 2,976 4,171 5,204 6,783 9,285 10,972 12,369 15,079 20,065 22,980 33,403 39,683 53,207
Allowable
Maximum PowerHigh-
performance
with heatsink
(W)
149 158 167 180 189 200 210 218 240 251 270 288 300
Cost-performance
(W)80 84 91 98 104 109 114 120 131 138 148 158 168
Functions per chip
at production(million transistors
[Mtransistors])
153 193 243 307 386 487 614 773 1,227 1,546 2,454 3,092 4,908
Key Overall Chip Parameters for High-Performance Logic, Datafrom 2003 ITRS
Technology generations defined by DRAM half pitch
Gate length (Lg) 0.5 X DRAM half pitch
Rapid scalingof Lgis driven by need to improve transistor speed
Clock frequency, functions per chip (density) scale rapidly, but allowablepower dissipation rises slowly with scaling: limited by ability to removeheat
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MOSFET Scaling Approach: 2005 ITRS
MASTAR computer modeling software is
used: detailed, analytical MOSFET modelswith key MOSFET physics included
Initial choice of scaled MOSFET parameters is
made
Using MASTAR, MOSFET parameters are
iteratively varied to meet ITRS targets for either
Scaling of transistor speed OR
Specific (low) levels of leakage current
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ITRS Drivers for Different Applications High-performancechips (MPU, for example)
Driver: maximize chip speedmaximize transistorperformance (metric: t, transistor intrinsic delay [or,equivalently, 1/t )
Goal of ITRS scaling: 1/tincreases at ~ 17% peryear, historical rate
Must maximize Ion Consequently, Ileakis relatively high
Low-powerchips (mobile applications)
Driver: minimize chip power (to conserve batterypower) minimize Ileak Goal of ITRS scaling: low levels of Ileak
Consequently, 1/tis considerably less than forhigh-performance logic
This talk focuses on high-performance logic,
which largely drives the technology
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1/tand Isd,leakscaling for High-Performance and Low-Power Logic. Data from 2003 ITRS.
100
1000
10000
2003 2005 2007 2009 2011 2013 2015 2017
Calendar Year
1/(G
Hz)
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
Isd,leak(
A/m)
Isd,leakHigh Perf
1/tHigh Perf
Isd,leakLow Power
1/tLow Power
17%/yr ave. increase
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1
10
100
1000
10000
2003 2005 2007 2009 2011 2013 2015 2017
Calendar Year
1/tau(GH
z)
Intrinsic, 1/t
Chip Clock: assumption is that
only improvement here is from
transistor speed increase
Frequency scaling: Transistor Intrinsic Speed andChip Clock Frequency for High-Performance Logic.Data from 2003 ITRS.
Chip clock: ITRS projection
Conclusion: transistor speed
improvement is a critical enabler ofchip clock frequency improvement
C S
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Potential Problem with Chip Power Dissipation Scaling:High-Performance Logic, Data from 2003 ITRS
1
10
100
2003 2005 2007 2009 2011 2013 2015 2017
Calendar Year
RelativeChipP
owerDissipation
Static
Dynamic
Unrealistic assumption, to make a point about Pstat ic:
all transistors are high performance, low Vt type
Projected cooling capability
P i l S l i f P Di i i
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Potential Solutions for Power DissipationProblems, High-Performance Logic
Increasingly common approach: multiple
transistor types on a chipmulti-Vt, multi-Tox, etc.
Only utilize high-performance, high-leakagetransistors in critical pathslower leakage
transistors everywhere else Improves flexibility for SOC
Circuit and architectural techniques: passgates, power down circuit blocks, etc.
Improved heat removal, electro-thermalmodeling and design
Electrical or dynamically adjustable Vt
devices (future possibility)
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Outline
Introduction
MOSFET scaling and its impact
Material and process approachesand solutions
Non-classical CMOS
Conclusions
Diffi lt T i t S li I
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Difficult Transistor Scaling Issues Assumption: highly scaled MOSFETs with
the targeted characteristics can besuccessfully designed and fabricated
However, with scaling, meeting transistorrequirements will require significanttechnology innovations
Iss ue: High gate leakage static powerdissipation
Direct tunneling increases rapidly as Toxisreduced
Potential solution: high-k gate dielectric
Issue: Polys i l icon deplet ion in gate electrodeincreased effective Tox, reduced Ion
Issue: Need for enhanced channel mob i l ity
Etc.
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For Low-Power Logic, Gate Leakage Current Density Limit VersusSimulated Gate Leakage due to Direct Tunneling. Data from 2003 ITRS.
1.00E-03
1.00E-02
1.00E-01
1.00E+00
1.00E+01
1.00E+02
1.00E+03
2003 2005 2007 2009 2011 2013 2015 2017
Calendar Year
Jg(A
/cm2)
0
1
23
4
5
6
7
8
9
1011
12
13
14
15
16
17
18
1920
21
22
23
24
EOT
(A)
Jg,simulated
Jg,limit
EOT
2006, EOT = 1.9 nm, Jg,max ~ 0.007 A/cm-2
Beyond this point of cross over,
oxy-nitride is incapable ofmeeting the limit (Jg,limit) on gate
leakage current density
Hi h K G t Di l t i t R d Di t T li
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High K Gate Dielectric to Reduce Direct Tunneling
Equivalent Oxide Thickness = EOT = Tox= TK* (3.9/K), where 3.9 isrelative dielectric constant of SiO2 and K is relative dielectricconstant of high K material
C = Cox= eox/Tox To first order, MOSFET characteristics with high-k are same as for SiO2
Because TK> Tox, direct tunneling leakage much reduced with high K
If energy barrier is high enough
Current leading candidate materials: HfO2(Keff~15 - 30); HfSiOx(K
eff
~12 - 16)
Materials, process, integration issues to solve
Electrode
Si substrate
Tox SiO2
TK
High-k Material
Electrode
Si substrate
Diffi lt T i t S li I
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Difficult Transistor Scaling Issues With scaling, meeting transistor
requirements requires significant
technology innovations Iss ue: High gate leakage static power
dissipation
Potential solution: high-k gate dielectric
Issue: po lys i l icon deplet ion in gate electrodeincreased effective Tox, reduced Ion
Potential solution: metal gate electrodes
Issue: Need fo r enhanced channel mob i l ity
Etc.
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Polysilicon Depletion and SubstrateQuantum Effects
Tox,electric = Tox+ (Kox/Ksi)*
(Wd,Poly
)
Kox= 3.9
Ksi= 11.9
Tox,electric= Tox+ (0.33)* (Wd,Poly)
Wd,Poly~1/(poly doping)0.5
increase poly doping toreduce Wd,Polywith scaling
But max. poly doping is
limited
cant reduce
Wd,Polytoo much
Poly depletion become more
critical with Toxscaling
Eventually, poly will reach
its limit of effectiveness
TOx
Polysilicon
Gate
Gate Oxide
Substrate
Depletion Layer
Inversion Layer
Wd,Poly
M t l G t El t d
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Metal Gate Electrodes
Metal gate electrodes are a potentialsolution when poly runs out of steam:
probably implemented in 2008 or beyond
No depletion, very low resistance gate, no boronpenetration, compatibility with high-k
Issues
Different work functions needed for PMOS andNMOS==>2 different metals may be needed
Process complexity, process integrationproblems, cost
Etching of metal electrodes
New materials: major challenge
Difficult Transistor Scaling Issues
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Difficult Transistor Scaling Issues With scaling, meeting transistor
requirements requires significant
technology innovations Iss ue: High gate leakage static power
dissipation
Potential solution: high-k gate dielectric
Issue: Poly deplet ion in gate electrodeincreased effective Tox, reduced Ion
Potential solution: metal gate electrodes
Issue: Need fo r enhanced channel mob i l ity
Potent ia l so lut ion : enhanced mob i l ity viastrain engineer ing
Etc.
U i i l P I d d St f
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Uniaxial Process Induced Stress forEnhanced Mobility
From K. Mistry et al., Delaying Forever: Uniaxial Strained
Silicon Transistors in a 90nm CMOS Technology, 2004 VLSITechno logy Sympos ium, pp. 50-51.
NMOS: uniaxial tensile stress
from stressed SiN film
PMOS: uniaxial compressive
stress from sel. SiGe in S/D
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Outline
Introduction
Scaling and its impact
Material and process approachesand solutions
Non-classical CMOS Conclusions
Li it f S li Pl B lk MOSFET
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Limits of Scaling Planar, Bulk MOSFETs 65 nm tech. generation (2007, Lg= 25nm) and
beyond: increased difficulty in meeting all device
requirements with classical planar, bulk CMOS(even with high-k, metal electrodes, strained Si)
Control of SCE
Impact of quantum effects and statistical variation
Impact of high substrate doping Control of series S/D resistance (Rseries,s/d)
Others
Alternative device structures (non-classicalCMOS) may be utilized
Ultra thin body, fully depleted: single-gate SOI
and multiple-gate transistors
Transistor Structures: Planar Bulk & Fully Depleted SOI
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Transistor Structures: Planar Bulk & Fully Depleted SOI
REFERNCES
1. P.M. Zeitzoff, J.A. Hutchby and H.R. Huff, MOSFET and Front-End Process Integration: Scaling
Trends, Challenges, and Potential Solutions Through The End of The Roadmap, International
Journal of High-Speed Electronics and Systems, 12, 267-293 (2002).2. Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001.
Planar Bulk Fully Depleted
SOI
SD
G
Substrate
Depletion Region
+Wafer cost / availability
- SCE scaling difficult
-High doping effects and
Statistical variation
-Parasitic junctioncapacitance
+Lower junction cap+Light doping possible+ Vt can be set by WF of
Metal Gate Electrode- SCE scaling difficult
- Sensitivity to Sithickness (very thin)
-Wafer cost/availability
Substrate
BOX
SDG
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Double Gate Transistor Structure
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Double Gate Transistor Structure
+ Enhanced scalabi l i ty
+Lower junction capacitance
+Light doping possible
+ Vt can be set by WF ofmetal gate electrode
+~2x drive current
-~2x gate capacitance
-High Rseries,s/draised S/D-Complex process
Ultra-
thin FD
S D
Top
Bottom
Double-Gate SOI:
BOX
SUBSTRATE
REFERENCES
1. P.M. Zeitzoff, J.A. Hutchby and H.R. Huff, MOSFET and
Front-End Process Integration: Scaling Trends, Challenges, and
Potential Solutions Through The End of The Roadmap,
International Journal of High-Speed Electronics and Systems,
12, 267-293 (2002).2. Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001.
Summ ary: mo re advanced, opt im aldevice structu re, bu t dif f icul t tofabr icate, part icular ly in this SOI
conf igurat ion
Field Lines for Single and Double-Gate MOSFETs
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Field Lines for Single and Double-Gate MOSFETs
S D
G
S D
G
G
E-Field lines
Regular SOI MOSFET Double-gate MOSFET
Double gates
electrically shield
the channel
To reduce SCEs,
aggressively reduce
Si layer thickness
Single-Gate SOI Double-Gate
Cour tesy: Prof. J-P Coling e, UC-Davis
BOX BOX
Double Gate Transistor Structure
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Double Gate Transistor Structure
+ Enhanced scalabi l i ty
+Lower junction capacitance
+Light doping possible
+ Vt can be set by WF ofmetal gate electrode
+~2x drive current
-~2x gate capacitance
-High Rseries,s/draised S/D-Complex process
Ultra-
thin FD
S D
Top
Bottom
Double-Gate SOI:
BOX
SUBSTRATE
REFERENCES
1. P.M. Zeitzoff, J.A. Hutchby and H.R. Huff, MOSFET and
Front-End Process Integration: Scaling Trends, Challenges, and
Potential Solutions Through The End of The Roadmap,
International Journal of High-Speed Electronics and Systems,
12, 267-293 (2002).2. Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001.
Summ ary: mo re advanced, opt im aldevice structu re, bu t dif f icul t tofabr icate, part icular ly in this SOI
conf igurat ion
Oth D bl G t T i t St t (Fi FET)
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Other Double-Gate Transistor Structures (FinFET)
Poly GatePoly GatePoly GatePoly Gate
Source DrainSource DrainSource Drain
Fin
Source Drain
Top View of
FinFET
Arrow indicatesCurrent flow
Key advantage: relatively
conventional processing,
largely compatible with
current techniques
current
leading approach
Perspective
view of FinFET.Fin is colored
yellow.
Gate overlaps fin here
SiO2
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
SiO2
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
SiO2
BOX
GateGate
DrainDrainSourceSourceSiOSiO22 SiOSiO22
Courtesy: T-J. King and
C. Hu, UC-Berkeley
Fin
Substrate Silicon
Types of Multiple Gate Devices
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Types of Multiple-Gate Devices
S
D
G
S
D
G
S
DG
1 2 3
Buried Oxide
S
DG
S
DG
4 5
Buried Oxide
1: Single gate2: Double gate3: Triple gate4: Quadruple gate (GAA)
5:Pgate
Courtesy:
Pro f. J-P
Colinge,UC-Davis
Increasingprocess
complexity,
increasing
scalability
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Outline
Introduction
Scaling and its impact
Material and process approachesand solutions
Non-classical CMOS
Conclusions
Timeline of Projected Key Technology Innovations from 03 ITRS, PIDS
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j y gy ,Section
This timeline is from PIDS evaluation for the 2003 ITRS
Conclusions
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Conclusions Rapid transistor scaling is projected to continue through
the end of the Roadmap in 2020
Transistor performance will improve rapidly, but leakage & SCEswill be difficult to control
Transistor performance improvement is a key enabler of chipspeed improvement
Many technology innovations will be needed in a relatively shorttime to enable this rapid scaling
Material and process innovations include high-k gate dielectric,
metal gate electrodes, and enhanced mobility through strainedsilicon
High-k and metal gate electrode needed in 2008
Structural potential solutions: non-classical CMOS
Non-classical CMOS and process and material innovations
will likely be combined in the ultimate, end-of-Roadmapdevice
Well under 10nm MOSFETs expected by the end of the Roadmap
Power dissipation, especially static, is a growing problemwith scaling: integrated, innovative approaches
needed