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Penn ESE680-002 Spring2007 -- DeHon 1
ESE680-002:Computer Organization
Day 3: January 17, 2007
Arithmetic and Pipelining
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Penn ESE680-002 Spring2007 -- DeHon 2
Last Time
• Boolean logic computing any finite function
• Sequential logic computing any finite automata – included some functions of unbounded size
• Saw gates and registers– …and a few properties of logic
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Penn ESE680-002 Spring2007 -- DeHon 3
Today
• Addition– organization– design space– area, time
• Pipelining
• Temporal Reuse– area-time tradeoffs
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Penn ESE680-002 Spring2007 -- DeHon 4
Why?
• Start getting a handle on – Complexity
• Area and time• Area-time tradeoffs
– Parallelism– Regularity
• Arithmetic underlies much computation– grounds out complexity
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Penn ESE680-002 Spring2007 -- DeHon 5
C: 00A: 01101101010B: 01100101100S: 0
C: 000A: 01101101010B: 01100101100S: 10
C: 0000A: 01101101010B: 01100101100S: 110
C: 10000A: 01101101010B: 01100101100S: 0110
C: 010000A: 01101101010B: 01100101100S: 10110
C: 1010000A: 01101101010B: 01100101100S: 010110
C: 11010000A: 01101101010B: 01100101100S: 0010110
C: 011010000A: 01101101010B: 01100101100S: 10010110
C: 1011010000A: 01101101010B: 01100101100S: 110010110
C: 11011010000A: 01101101010B: 01100101100S: 1110010110
C: 11011010000A: 01101101010B: 01100101100S: 11110010110
Example: Bit Level Addition
• Addition – (everyone knows how to do addition base
2, right?)
A: 01101101010B: 01100101100S:
C: 0A: 01101101010B: 01100101100S:
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Penn ESE680-002 Spring2007 -- DeHon 6
Addition Base 2• A = an-1*2(n-1)+an-2*2(n-2)+... a1*21+ a0*20
= (ai*2i)
• S=A+B
• What is the function for si … carryi?
• si=(xor carryi (xor ai bi))
• carryi = ( ai-1 + bi-1 + carryi-1) 2
= (or (and ai-1 bi-1) (and ai-1 carryi-1)
(and bi-1 carryi-1))
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Penn ESE680-002 Spring2007 -- DeHon 7
Adder Bit
• S=(xor a b carry)• t=(xor2 a b); s=(xor2 t carry)• xor2 = (and (not (and2 a b)
(not (and2 (not a) (not b)))
• carry = (not (and2 (not (and2 a b)) (and2 (not (and2 b carry)) (not (and2 a carry)))))
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Penn ESE680-002 Spring2007 -- DeHon 8
Ripple Carry Addition• Shown operation of each bit
• Often convenient to define logic for each bit, then assemble:– bit slice
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Penn ESE680-002 Spring2007 -- DeHon 9
Ripple Carry Analysis
• Area: O(N) [6n]
• Delay: O(N) [n+3]
What is area and delay?
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Penn ESE680-002 Spring2007 -- DeHon 10
Can we do better?
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Penn ESE680-002 Spring2007 -- DeHon 11
Important Observation
• Do we have to wait for the carry to show up to begin doing useful work?– We do have to know the carry to get the
right answer.– But, it can only take on two values
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Penn ESE680-002 Spring2007 -- DeHon 12
Idea
• Compute both possible values and select correct result when we know the answer
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Penn ESE680-002 Spring2007 -- DeHon 13
Preliminary Analysis
• Delay(RA) --Delay Ripple Adder
• Delay(RA(n)) = k*n
• Delay(RA(n)) = 2*(k*n/2)=2*DRA(n/2)
• Delay(P2A) -- Delay Predictive Adder
• Delay(P2A)=DRA(n/2)+D(mux2)
• …almost half the delay!
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Penn ESE680-002 Spring2007 -- DeHon 14
Recurse
• If something works once, do it again.
• Use the predictive adder to implement the first half of the addition
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Penn ESE680-002 Spring2007 -- DeHon 15
Recurse
Redundant (can share)
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Penn ESE680-002 Spring2007 -- DeHon 16
Recurse
• If something works once, do it again.
• Use the predictive adder to implement the first half of the addition
• Delay(P4A(n))=Delay(RA(n/4)) + D(mux2) + D(mux2)
• Delay(P4A(n))=Delay(RA(n/4))+2*D(mux2)
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Penn ESE680-002 Spring2007 -- DeHon 17
Recurse
• By know we realize we’ve been using the wrong recursion– should be using the Predictive Adder in the
recursion
• Delay(PA(n)) = Delay(PA(n/2)) + D(mux2)
• Every time cut in half…?
• How many times cut in half?
• Delay(PA(n))=log2(n)*D(mux2)+C
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Penn ESE680-002 Spring2007 -- DeHon 18
Another Way
(Parallel Prefix)
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Penn ESE680-002 Spring2007 -- DeHon 19
CLA
• Think about each adder bit as a computing a function on the carry in– C[i]=g(c[i-1])– Particular function f will
depend on a[i], b[i]– G=f(a,b)
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Penn ESE680-002 Spring2007 -- DeHon 20
Functions
• What functions can g(c[i-1]) be?– g(x)=1
• a[i]=b[i]=1
– g(x)=x• a[i] xor b[i]=1
– g(x)=0• a[i]=b[i]=0
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Penn ESE680-002 Spring2007 -- DeHon 21
Functions
• What functions can g(c[i-1]) be?– g(x)=1 Generate
• a[i]=b[i]=1
– g(x)=x Propagate• a[i] xor b[i]=1
– g(x)=0 Squash• a[i]=b[i]=0
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Penn ESE680-002 Spring2007 -- DeHon 22
Combining
• Want to combine functions– Compute c[i]=gi(gi-1(c[i-2]))
– Compute compose of two functions
• What functions will the compose of two of these functions be?– Same as before
• Propagate, generate, squash
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Penn ESE680-002 Spring2007 -- DeHon 23
Compose Rules(LSB MSB)
• GG• GP • GS• PG• PP• PS
• SG• SP• SS
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Penn ESE680-002 Spring2007 -- DeHon 24
Compose Rules (LSB MSB)
• GG = G• GP = G• GS = S• PG = G• PP = P• PS = S
• SG = G• SP = S• SS = S
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Penn ESE680-002 Spring2007 -- DeHon 25
Combining
• Do it again…
• Combine g[i-3,i-2] and g[i-1,i]
• What do we get?
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Penn ESE680-002 Spring2007 -- DeHon 26
Reduce Tree
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Penn ESE680-002 Spring2007 -- DeHon 27
Prefix TreeP
refix
T
ree
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Penn ESE680-002 Spring2007 -- DeHon 28
Parallel Prefix
• Important Pattern
• Applicable any time operation is associative
• Examples of associative functions?– Non-associative?
• Function Composition is always associative
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Penn ESE680-002 Spring2007 -- DeHon 29
Note: Constants Matter
• Watch the constants
• Asymptotically this Carry-Lookahead Adder (CLA) is great
• For small adders can be smaller with– fast ripple carry– larger combining than 2-ary tree– mix of techniques
• …will depend on the technology primitives and cost functions
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Penn ESE680-002 Spring2007 -- DeHon 30
Two’s Complement
• Everyone seemed to know Two’s complement
• 2’s complement:– positive numbers in binary– negative numbers
• subtract 1 and invert• (or invert and add 1)
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Penn ESE680-002 Spring2007 -- DeHon 31
Two’s Complement
• 2 = 010
• 1 = 001
• 0 = 000
• -1 = 111
• -2 = 110
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Penn ESE680-002 Spring2007 -- DeHon 32
Addition of Negative Numbers?
• …just works
A: 111B: 001S: 000
A: 110B: 001S: 111
A: 111B: 010S: 001
A: 111B: 110S: 101
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Penn ESE680-002 Spring2007 -- DeHon 33
Subtraction• Negate the subtracted input and use adder
– which is:
• invert input and add 1• works for both positive and negative input
–001 110 +1 = 111–111 000 +1 = 001–000 111 +1 = 000–010 101 +1 = 110–110 001 +1 = 010
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Penn ESE680-002 Spring2007 -- DeHon 34
Subtraction (add/sub)
• Note: you can use the “unused” carry input at the LSB to perform the “add 1”
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Penn ESE680-002 Spring2007 -- DeHon 35
Overflow?
• Overflow=(A.s==B.s)*(A.s!=S.s)
A: 111B: 001S: 000
A: 110B: 001S: 111
A: 111B: 010S: 001
A: 111B: 110S: 101
A: 001B: 001S: 010
A: 011B: 001S: 100
A: 111B: 100S: 011
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Penn ESE680-002 Spring2007 -- DeHon 36
Reuse
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Penn ESE680-002 Spring2007 -- DeHon 37
Reuse
• In general, we want to reuse our components in time
– not disposable logic
• How do we do that?– Wait until done, someone’s used output
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Penn ESE680-002 Spring2007 -- DeHon 38
Reuse: “Waiting” Discipline
• Use registers and timing (or acknowledgements) for orderly progression of data
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Penn ESE680-002 Spring2007 -- DeHon 39
Example: 4b Ripple Adder
• Recall 1 gates/FA• Latency and throughput?• Latency: 4 gates to S3• Throughput: 1 result / 4 gate delays max
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Penn ESE680-002 Spring2007 -- DeHon 40
Can we do better?
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Penn ESE680-002 Spring2007 -- DeHon 41
Stagger Inputs
• Correct if expecting A,B[3:2] to be staggered one cycle behind A,B[1:0]
• …and succeeding stage expects S[3:2] staggered from S[1:0]
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Penn ESE680-002 Spring2007 -- DeHon 42
Align Data / Balance Paths
Good discipline toline up pipe stagesin diagrams.
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Penn ESE680-002 Spring2007 -- DeHon 43
Example: 4b RA pipe 2
• Recall 1 gates/FA• Latency and Throughput?• Latency: 4 gates to S3• Throughput: 1 result / 2 gate delays max
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Penn ESE680-002 Spring2007 -- DeHon 44
Deeper?
• Can we do it again?
• What’s our limit?
• Why would we stop?
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Penn ESE680-002 Spring2007 -- DeHon 45
More Reuse• Saw could pipeline and reuse FA more
frequently
• Suggests we’re wasting the FA part of the time in non-pipelined
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Penn ESE680-002 Spring2007 -- DeHon 46
More Reuse (cont.)
• If we’re willing to take 4 gate-delay units, do we need 4 FAs?
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Penn ESE680-002 Spring2007 -- DeHon 47
Ripple Add (pipe view)
Can pipeline to FA.
If don’t need throughput, reuse FA on SAME addition.
What if don’t need the throughput?
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Penn ESE680-002 Spring2007 -- DeHon 48
Bit Serial Addition
Assumes LSB first ordering ofinput data.
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Penn ESE680-002 Spring2007 -- DeHon 49
Bit Serial Addition: Pipelining• Latency and throughput?
• Latency: 4 gate delays
• Throughput: 1 result / 5 gate delays
• Can squash Cout[3] and do in 1 result/4 gate delays
• registers do have time overhead– setup, hold time, clock jitter
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Penn ESE680-002 Spring2007 -- DeHon 50
Multiplication
• Can be defined in terms of addition
• Ask you to play with implementations and tradeoffs in homework 2– Out today – Pickup from syllabus page on web
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Penn ESE680-002 Spring2007 -- DeHon 51
Compute Function
• Compute:
y=Ax2 +Bx +C
• Assume–D(Mpy) > D(Add)
–A(Mpy) > A(Add)
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Penn ESE680-002 Spring2007 -- DeHon 52
Spatial Quadratic
• D(Quad) = 2*D(Mpy)+D(Add)
• Throughput 1/(2*D(Mpy)+D(Add))
• A(Quad) = 3*A(Mpy) + 2*A(Add)
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Penn ESE680-002 Spring2007 -- DeHon 53
Pipelined Spatial Quadratic
• D(Quad) = 3*D(Mpy)
• Throughput 1/D(Mpy)
• A(Quad) = 3*A(Mpy) + 2*A(Add)+6A(Reg)
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Penn ESE680-002 Spring2007 -- DeHon 54
Bit Serial Quadratic
• data width w; one bit per cycle
• roughly 1/w-th the area of pipelined spatial
• roughly 1/w-th the throughput
• latency just a little larger than pipelined
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Penn ESE680-002 Spring2007 -- DeHon 55
Quadratic with Single Multiplier and Adder?
• We’ve seen reuse to perform the same operation – pipelining– bit-serial, homogeneous datapath
• We can also reuse a resource in time to perform a different role.– Here: x*x, A*(x*x), B*x– also: (Bx)+c, (A*x*x)+(Bx+c)
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Penn ESE680-002 Spring2007 -- DeHon 56
Quadratic Datapath
• Start with one of each operation
• (alternatives where build multiply from adds…e.g. homework)
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Penn ESE680-002 Spring2007 -- DeHon 57
Quadratic Datapath
• Multiplier servers multiple roles– x*x– A*(x*x)– B*x
• Will need to be able to steer data (switch interconnections)
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Penn ESE680-002 Spring2007 -- DeHon 58
Quadratic Datapath
• Multiplier servers multiple roles– x*x– A*(x*x)– B*x
• x, x*x
• x,A,B
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Penn ESE680-002 Spring2007 -- DeHon 59
Quadratic Datapath
• Multiplier servers multiple roles– x*x– A*(x*x)– B*x
• x, x*x
• x,A,B
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Penn ESE680-002 Spring2007 -- DeHon 60
Quadratic Datapath
• Adder servers multiple roles– (Bx)+c– (A*x*x)+(Bx+c)
• one always mpy output
• C, Bx+C
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Penn ESE680-002 Spring2007 -- DeHon 61
Quadratic Datapath
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Penn ESE680-002 Spring2007 -- DeHon 62
Quadratic Datapath• Add input
register for x
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Penn ESE680-002 Spring2007 -- DeHon 63
Quadratic Control• Now, we just need to control the datapath• What control?• Control:
– LD x– LD x*x– MA Select– MB Select– AB Select– LD Bx+C– LD Y
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Penn ESE680-002 Spring2007 -- DeHon 64
FSMD
• FSMD = FSM + Datapath• Stylization for building controlled
datapaths such as this (a pattern)• Of course, an FSMD is just an FSM
– it’s often easier to think about as a datapath– synthesis, AP&R tools have been
notoriously bad about discovering/exploiting datapath structure
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Penn ESE680-002 Spring2007 -- DeHon 65
Quadratic FSMD
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Penn ESE680-002 Spring2007 -- DeHon 66
Quadratic FSMD Control• S0: if (go) LD_X; goto S1
– else goto S0• S1: MA_SEL=x,MB_SEL[1:0]=x, LD_x*x
– goto S2• S2: MA_SEL=x,MB_SEL[1:0]=B
– goto S3• S3: AB_SEL=C,MA_SEL=x*x, MB_SEL=A
– goto S4• S4: AB_SEL=Bx+C, LD_Y
– goto S0
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Penn ESE680-002 Spring2007 -- DeHon 67
Quadratic FSMD Control• S0: if (go) LD_X; goto S1
– else goto S0• S1: MA_SEL=x,MB_SEL[1:0]=x, LD_x*x
– goto S2• S2: MA_SEL=x,MB_SEL[1:0]=B
– goto S3• S3: AB_SEL=C,MA_SEL=x*x, MB_SEL=A
– goto S4• S4: AB_SEL=Bx+C, LD_Y
– goto S0
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Penn ESE680-002 Spring2007 -- DeHon 68
Quadratic FSM
• Latency/Throughput/Area?
• Latency: 5*(D(MPY)+D(mux3))
• Throughput: 1/Latency
• Area: A(Mpy)+A(Add)+5*A(Reg) +2*A(Mux2)+A(Mux3)+A(QFSM)
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Penn ESE680-002 Spring2007 -- DeHon 69
Big Ideas[MSB Ideas]
• Can build arithmetic out of logic• Pipelining:
– increases parallelism– allows reuse in time (same function)
• Control and Sequencing– reuse in time for different functions
• Can tradeoff Area and Time
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Penn ESE680-002 Spring2007 -- DeHon 70
Big Ideas[MSB-1 Ideas]
• Area-Time Tradeoff in Adders
• Parallel Prefix
• FSMD control style