PCI Express® Revision 2Receiver (RX) Jitter Tolerance Test
with J-BERT N4903B
High-Performance Serial BERT
Application Note
J-BERT N4903B High-Performance Serial BERT with Complete Jitter Tolerance Testing for PCI Express® Revision 2
All jitter sources built in (dual tone DJ,
spectral RJ, SSC and residual SSC)
compliant to PCI Express® revision 2
Flexible clock and trigger channels to
support PCI Reference clock differential
mode noise
flexible pattern sequencer to train the
DUT (set loop-back mode) and run the
test
J-BERT N4903B high performance
serial BERT´s automated compliance
tests with N5990A test automation
software
•
•
•
•
2
PCIe 2nd RX test
Chip test
Base spec
Data driven topo
Chip test
Base spec
Common ref clk
Add-in test
CEM spec
Common ref clk
System board
CEM spec
Common ref clkCalibration channel (ISI) 5 : 1 pulse voltage 5 : 1 pulse voltage No No
RJ 1.5 MHz .. 100 MHz 4.2 ps rms 3.4 ps rms 3.4 ps rms 1.4 ps rms
RJ 10 kHz .. 1.5 MHz 8.0 ps rms 4.2 ps rms 4.2 ps rms 3.0 ps rms
DJ > 100 MHz No No Yes, SJ of 27 ps Yes, SJ of 27 ps
DJ > 1.5 MHz .. 100 MHz Yes, pure SJ or (SJ + ISI) of 88 ps Yes, SJ of 30 ps Yes, SJ of 30 ps
Desidual SSC No 75 ps, triangle 75 ps, triangle No
SSC 20 ns (-500 ppm) No No No
CM crosstalk (SI) 300 mV 300 mV No No
VRX-eye, min 100 mV pp, diff 120 mV pp, diff 300 mV pp, diff 260 mV pp, diff
Table 1: Parameters for RX Jitter Tolerance Testing required for the different test cases
Scope of this document
This document describes the RX jitter
tolerance test requirements for PCI
Express revision 2. It explains how
these requirements can be efficiently
fulfilled for compliance and character-
ization test with help of the J-BERT
N4903B high-performance serial
BERT with complete jitter tolerance
testing.
Finally there is a short introduction on
TX testing with help of the measure-
ments of the J-BERT N4903B.
Introduction
PCI Express made it to one of the
major interfaces inside a computer. In
December 2006 the PCI-SIG® associa-
tion released the base specification
revision 2 [1]. The revision 2 doubles
the operating speed from 2.5 Gb/s in
revision 1 to 5 Gb/s. Beside the base
specification there was a release of
the card electromechanical (CEM)
specification, revision 2.0 in April
2007 [2] as a companion to the base
specification.
From testing perspective the two
specifications can be treated as: the
base specification deals with perfor-
mance at chip level, while the CEM
specification deals with the cards at
the connectors especially in the case
of interoperability.
Requirements by the standards
The base specification deals with two
different clocking topologies called:
Data driven topology
Common reference clock
Simply said the first does not share
a clock signal, while the second
provides a common reference clock
at 1/50 of the data rate. The first two
columns in Table 1 represent the two
test cases and the according jitter
parameter values.
The CEM standard deals with add-in
card and system board test for the
common reference clock topology.
The last two columns in Table 1
represent the jitter parameter values
for these two test cases.
Consecutively Table 1 lists the jitter
parameters for the four RX test cases.
In the following these parameters are
described in more detail:
•
•
1. The calibration channel applies
in the base specification. It intends
to create inter-symbol interference
(ISI) described as an amplitude
ratio of 5:1. The intention is to
create a signal aberration which
is apparent in printed circuit
boards used for the motherboard
and the add-in card. A signal with
this amplitude ratio can be
obtained from ISI trace 3 in J-BERT.
N4903B as shown in Figure 1. The
marker read-outs provide the
desired ratio. This incorporates a
timing jitter of 73 ps (ISI reading)
as can be seen on Figure 2. With
the specification of DJ (1.5 MHz ..
100 MHz) with value of 88 ps,
there is a remaining need for SJ by
15 ps.
2. All the following jitter parameters
are calibrated dials on the J-BERT
N4903B. There is no need for any
calibration. Just enter the desired
values in the dials as shown in
Figure. If it is intended to verify
the jitter values, the use of the
infiniium 86100C DCA-J is
recommended with help of the
jitter analysis as shown in Figure 2
(RJ, PJ & ISI readings) in
accordance with the application
note [7].
3
3. RJ (1.5 MHz .. 100 MHz) applies in
all test cases with various amount.
4. RJ (10kHz .. 1.5 MHz) applies in all test
cases with various amount.
5. DJ > 100 MHz applies in the CEM
standard as a replacement of the ISI
generation in the base specification.
6. DJ (1.5 MHz .. 100 MHz) applies in all
test cases with various amount. With
help of the jitter tolerance measurement
it is possible to sweep the frequency
for debug/characterization testing.
7. Residual SSC applies to both standards
but not for system board test. This
is similar to a periodic jitter but with a
triangular shape.
8. SSC applies in the base specification
for the data driven topology only. SSC
is again a calibrated dial located in the
N4903B generator clock setup window.
SSC is the only jitter component which
can‘t be measured directly with the
jitter analysis on the infiniium 86100C
DCA-J; instead a spectrum analyzer is
recommended, more details are given
in [6].
9. The bottom row values in Table 1 refer
to the required minimum amplitudes.
The amplitudes are intended at the chip
pin. Due to the loss of the PC board,
these amplitude are different from the
amplitudes at the end of the coaxial
cables. Furthermore the Gen2 standard
requires the loss compensation the way
that the transitional bit and the
de-emphasized bit have the same
amplitude. This makes it necessary
to use the N4916A de-emphasis signal
converter as shown in Figure 3. For
add-in card test according the CEM
spec the calibration of the minimum
amplitude can be performed with help
of the compliance base board (CBB)
and the compliance load board (CLB),
both provided by the PCI SIG, where
the coaxial cables hook up
conveniently. The N4916A signal
converter is used to dial in its variable
de-emphasis until the amplitudes of the
transitional bit and the amplitude of the
de-emphasized bit are the same. [8]
Figure 1: Calibration channel with amplitude ratio of 5:1, realized with
J-BERT N4903B ISI trace #3
Figure 2: Jitter analysis on the signal in fi gure 1, the measured ISI is 73 ps
Figure 3: Setup of J-BERT with N4916A de-emphasis signal converter and
CBB and CLB for the calibration of the minimum amplitude
Compliance
base board (CBB)
Compliance
load board (CLB)
Data to DSA91304A
Data from J-BERT N4903B generator
N4916A De-Ephasis signal converter
4
More PCI Express revision 2 RX test jitter fundamentals
PCI Express Revision 2 RX Jitter toler-
ance testing deals with new kind of
jitter creation for stressing the RX:
1. Spectrally distributed RJ
2. Dual tone DJ
3. Residual SSC
This chapter is intended to look a
little deeper into these subjects:
Figure 4 shows spectrally distributed
RJ. The diagram shows the amount
of jitter vs. frequency. White noise
(unlimited bandwidth) contains
constant amount of energy at all
frequencies. The specification here
intends a higher amount of random
jitter at the lower frequencies and a
lower amount at the higher frequen-
cies. The actual amount depends on
the test case, see Table 1. The corner
frequency is at 1.5 MHz, the filter cut-
off shall be infinitely steep (Brick-wall
filter).
J-BERT N4903B creates this scenario
by RJhf over the whole bandwidth
(10 kHz .. 100 MHz) and adds RJlf (10
kHz .. 1.5 MHz) on top.
Figure 5 shows the concept of dual
tone DJ. Normally DJ jitter would
be used as sinusoidal jitter at one
frequency while the frequency may
be varied over time (jitter tolerance
measurement). The dual tone method
uses two sinusoidal signals at the
same time, one at the lower and one
at higher frequency.
Optionally the signal at lower
frequency may sweep continuously
between the min. and max. value
of the frequency band. The actual
amount of both signals depend on
test case, see Table 1. J-BERT
N4903B creates PJ1 and PJ2
accordingly.
Figure 6 shows the spread-spectrum
modulation (SSC). Such a modulation
is defined by the SSC deviation (typ.
500 ppm) and the SSC frequency (typ.
30 .. 33 kHz). The deviation occurs
downwards typically . So for a data
rate of 5 Gb/s the deviation of 500
ppm means the data rate changes
between 5 GB/s and 4.975 Gb/s with
a frequency of 30 .. 33 kHz. The shape
of the ideal modulation is triangular,
while practically anything between
sinusoidal and triangular is applied.
Figure 4: Bandwidth weighted RJ
Spectrally distributed RJ
10 kHz 1.5 MHz 100 MHz
RJLF
RJHF
White
noise
Variable
gain
LF bandpass filter (brick-wall)
HF bandpass
filter
f
UI/ps rms
‚Brick-wall‘ filter
Figure 5: Dual Tone DJ
Dual tone DJ
1.5 MHz 100 MHz 200 MHz
Variable
gain
Sweep
HF source
variable
LF source
sweep
UI/ps
DJLF
DJHF
f
5
Figure 7 depicts the SSC modulation
in time view. The top trace is a signal
without SSC for reference. With the
bottom trace the data signal is shown
while the SSC modulation starts with
the negative slope. On this slope the
data rate (in frequency) decreases
linear; the data cycle (in time)
increases by the by the 1/x function.
With a SSC frequency of 33 kHz the
duration of the negative slope lasts
15 us. So there are:
15 us/200ps = 75000 data cycles (1)
along the negative transition. The
change in time for the data cycle
is from 200 ps (D1) to 201,005 ps
(D75000
). The total delay shift of the
data stream in reference to the un-
modulated signal is as much as TSSC
= 20 ns from the beginning to the
end of the negative transition of the
modulation:
TSSC
= ∑ (Dn-200 ps), n = 1 .. 75000 (2)
PCIe adds the SSC modulation to
the 100 MHz refclk, consequently
the system needs a multiplying PLL
in the TX and a multiplying PLL with
clock-data recovery (CDR) in the RX.
A CDR has a finite bandwidth, caus-
ing a finite time for reacting on the
refclk changes. A system architecture
as shown in Figure 8, incorporates
a significant difference in transport
delay for the TX data appearing at the
RX latch input and the clock running
through the CDR. The transport delay
through the CDR (~ 200 ns) is much
higher than through the channel
(spec is < 12 ns). Such delay differ-
ence results in phase shift of the SSC
causing eye closure at the sampler.
This is called‚ residual SSC‘ (rSSC).
When testing this matter is inverted
by using a clean refclk and residual
SSC on the data which creates an
equivalent stress situation.
Figure 6: SSC modulation
SSC modulation
fssc
30 .. 33 kHz
5 Gb/s
-.5%
4.975 Gb/s
Data rate
t
Figure 7: SSC modulation in time view
SSC in time view
fssc
= 33 kHz
P = 30 us
D1
200 ps
200 ps 200.1 ps 200.2 ps 201 ps 200.9 ps
200 ps 200 ps 200 ps
D2
D3
D1
D2
D3
D75000
D75001
D75001
20 ns
t
T = 15 us
T = 0 us
No SSC
Figure 8: Transport delay differences cause residual SSC (rSSC)
Residual SSC
rSSC spec is 75 psResults from SSC on Refclk and transport delay T1Per calculation the 75 ps represent a delay of 220 ns, spec for T1 = 12 ns≥ most of the rSSC budget is due to CDR (min BW > 5MHz)When testing SSC on Refclk is disabled and replace by rSSC on data
•••••
Tx PLL
Tx Latch Channel
Refclk
CDR
Tx Latch
Rx PLLX
1(s)
T1 = Transport delay delta
X1(s)
H2(s)H
1(s)
6
Test setup, block architecture
Figure 9 to 11 illustrate the RX test
setups as block diagrams.
The base specification applies to the
device under test (DUT) on a chip
level. Custom designed boards to
accommodate the chips are neces-
sary. These designs may or may not
include the calibration channel. If not,
the ISI capability of J-BERT N4903B
may be used.
Depending on the clock topology
the J-BERT N4903B connects to the
board with generator data and error
detector and with or without refer-
ence clock. For the reference clock
it is recommended to use the trigger
channel, see next page and Figure 12.
The CEM specification applies to
the add-in card test (Figure 10) and
system board test (Figure 11). For
these tests the compliance base
board (CBB) and the compliance load
board are necessary [3], [4]. It may
be necessary to apply modification to
the CBB for proper reference clock
injection, see [5].
For the test of an add-in card with
more than one data lane a PCIe-Riser-
Card x1 to 1x PCIe x16 is recom-
mended.
Testing according CEM specification
is in general according the refer-
ence clock topology. So the J-BERT
N4903B connects with generator
data, error detector and the trigger
channel as reference clock, see
above.
RX test, block diagram, CEM spec, add-in card
add-in, card
Compliance base board
Data refclk Data
All jitter components by generator and jitter setup,
Generator with sequence containing training and compliance pattern
Analyzer in CDR mode with compliance pattern
•
•
•
Calibration channel (ISI) No
RJ 1.5 MHz .. 100 MHz 3.4 ps rms
RJ 10 kHz .. 1.5 MHz 4.2 ps rms
DJ > 100 MHz Yes, SJ of 27 ps
DJ > 1,5 MHz .. 100 MHz Yes, SJ of 30 ps
Residual SSC 75 ps, triangle
SSC No
CM Crosstalk (SI) No
VRX-eye, min 300 mV, pp, diff
Add-in testCEM specCommon refclk
Figure 10: Test setup for RX test according CEM specifi cation for add-in card
RX test, block diagram, base spec
Figure 9: Test setup for RX test according base specifi cation, with or without reference clock depending on the topology
DUT, chip
Custom board
Data refclk Data
All jitter components by generator and jitter setup,
Generator with sequence containing training and compliance pattern
Analyzer in CDR mode with compliance pattern
•
•
•
Calibration channel 5:1 pulse voltage 5:1 pulse voltage
RJ 1.5 MHz .. 100 MHz 4.2 ps rms 3.4 ps rms
RJ 10 kHz .. 1.5 MHz 8.0 ps rms 4.2 ps rms
DJ > 100 MHz No No
DJ > 1,5 MHz .. 100 MHz Yes, pure SJ or (SJ +
ISI) of 88 ps
Residual SSC No 75 ps, triangls
SSC 20 ns (-500 ppm) No
CM Crosstalk (SI) 300 mV 300 mV
VRX-eye, min 100 mV, pp, diff 100 mV, pp, diff
Min RX PW 120 ps 120 ps
Chip test Chip testBase spec Base specData driven topo Common refclk
Figure 11: Test setup for RX test according CEM specifi cation for system board
RX test, block diagram, CEM spec, system board
System board
Compliance load board
Data Data
Analyzer in CDR mode to recover clk from system board data, this recovered clk is fed to generator clk inAll jitter components by generator and jitter setup,Generator with sequence containing training and compliance patternAnalyzer checks against compliance pattern
•
•••
Calibration channel (ISI) No
RJ 1.5 MHz .. 100 MHz 1.4 ps rms
RJ 10 kHz .. 1.5 MHz 3.0 ps rms
DJ > 100 MHz Yes, SJ of 27 ps
DJ > 1,5 MHz .. 100 MHz Yes, SJ of 30 ps
Residual SSC No
SSC No
CM Crosstalk (SI) No
VRX-eye, min 380 (260 @ 6 dB) mV, pp, diff
System boardCEM specCommon refclk
7
Test Setup, J-BERT N4903B Settings
J-BERT N4903B connects with generator
data out, error detector data in and the
trigger channel as a reference clock if
needed. The trigger channel can be pro-
grammed in amplitude and offset to apply
the required level specifications as shown
in Figure 12. The trigger channel is able to
supply a clock signal with a divider factor
of 1/50 to supply the reference clock at
100 MHz (this programming window is not
shown, it is accessible with the button PG
Setup -› Trigger/Ref CIK Setup).
Figure 13 shows the J-BERT N4903B
sequence editor with the sequence neces-
sary to train the add-in card. The training
consists of the top three blocks, which
bring the add-in card into the loop-back
mode. Block 4 contains the compliance
pattern, which will be used on the error
detector for synchronization and BER
measurement. The sequence is loaded
into the J-BERT N4903B hardware by
pressing the button‚ To PG‘. Before press-
ing the‚ Start‘ button, the add-in card
should be powered. When pressing the
‚Start‘ button the sequence is generated
by sending block 1 & 2 once, block 3 times
500 and finally block 4 for infinite. This is
indicated in the left bottom status window
reading ‚..Sequence, B:4‘. At this point the
J-BERT error detector can be auto-aligned
resulting in the ‚BER:0.000‘ reading. Not
shown is that the J-BERT N4903B error
detector gets the clock from the generator
clock output in ext. clock mode. (ED Setup
-› Clock Setup).
Figure 14 shows the jitter setup for the
add-in card test scenario. The values
dialed in:
With this mix of jitter components the
add-in card has to work for a BER < 1e-12
to be standard compliant.
Figure 12: Test setup for Reference Clock when necessary, this clock is generated
by the Trigger Channel with divider of 50 (seperate screen)
Figure 13: Sequencer setup with 4 blocks containing training and compliance test
segments, the analyzer detects on the compliance segment (block 4)
Figure 14: Jitter setup for the Add-Inn card Jitter mix
rSSC (spec is 75 ps) 375 mUI
PJ1(<100 MHz, 30 ps) 150 mUI
PJ2 (> 100 MHz, 27 ps) 135 mUI
sRJ (HF, 3.4ps rms) 17mUI rms
sRJ (LF, 4.2 ps rms) 4 mUI rms
Note: The implementation of RJLF is incremental; the programming value calculates: RJLF-RJHF = 4.2ps rms-3.4ps rms = 0.8ps rms (equals 4 mUI rms)
8
RX Test Results
The verification of the compliance of an
add-in card can be effectively performed
with help of the `accumulated results‘, as
shown in Figure 15. To prove the BER
< 1e-12 with a confidence level of 95% it
is necessary to test ~3 * 1e12 bits without
an error [9]. This equals 600 sec test time
at the data rate of 5 Gb/s. The accumu-
lated result measurement is configured
for single run and 600 sec duration.
The resulting graph will tell if any error
occurred.
For characterization or debug testing the
jitter tolerance characterization measure-
ment is a meaningful tool, as shown
in Figure 16. The measurement can be
configured for start and end of tolerance
sweep and resolution and can be zoomed
as desired. Optional a compliance mask
can be loaded to see the margin. The
faster version is the jitter tolerance
compliance measurement, where the
measured point are along the compli-
ance curve. Figure 16 runs the tolerance
measurement from 1 kHz to 300 MHz with
50 points.
While the specifications state the RX
compliance testing is performed with
non-de-emphasized signals, for charac-
terization purpose it may be desirable to
use such signals. In this case it is recom-
mended to use the N4916A de-emphasis
signal converter, for details see [8].
TX Test Results
TX compliance test is efficiently per-
formed with help of the J-BERT N4903B
eye diagram measurement and the ability
to load a predefined compliance mask
with margin definition, as shown in
Figure 17. This measurement is fast and
quantifies any violations (yellow insert).
Beside the fit to the compliance mask the
measurement provides the readings for
levels, amplitude, transition time, jitter
and signal-to-noise ratio.
Figure 15: Compliance test result RX test, the BER is measured for 600 sec, while
no error occured, this equals a BER < 1e-12 with 95 % confi dence level
Figure 16: Characterization of jitter tolerance, the measurement is performed with
SJ from 1 kHz to 300 MHz
Figure 17: Eye diagram measurement with compliance mask on the J-BERT N4903B
9
The J-BERT N4903B provides various
measurements for characterization of
the TX. Figure 18 & 19 show as examples
the eye opening and the output timing
measurement. The J-BERT N4903B data
sheet (5990-3217EN) provides the full list
of measurement capabilities.
The eye diagram in Figure 18 provides the
eye contour measurement of the output
signal of an add-inn card down to BER 1
e-9 (red curve) with a resolution of 1 mV
in amplitude and 1 ps in time.
The output timing measurement in
Figure 19 is able to measure the total
jitter at mostly any BER threshold, the
graph shown here is configured for BER
1e-6. With the fast total jitter optimization
enabled, the measurement on the total
jitter for BER
< 1e-12 will be completed in roughly
20 min.
Figure 20 shows a measurement of the TX
Jitter Transfer. This measurement is done
by manual sweep of the jitter frequency
(SJ = .1 UI, 500 kHz .. 50 MHz) and record
of the phase margin parameter of output
timing measurement. The values are
entered into a spreadsheet and normal-
ized to the reading at lowest jitter
frequency. Figure 20 represents the
resulting graph for the TX jitter transfer.
Summary
This document describes the require-
ments for PCI Express revision 2 RX jitter
tolerance intended by the base and CEM
standards. These standards set some new
kind of jitter creation requirements, which
are discussed in depth. The document
highlights the capabilities of the J-BERT
N4903B to efficiently address these
new requirements. Finally there is some
outlook provided to address TX test need
with the J-BERT N4903B.
The J-BERT N4903B provides all jitters
as calibrated dials, so without any need
for a custom calibration. In case of de-
emphasized signals are desired, the use of
N4916A de-emphasis signal converter is
recommended.
Figure 18: Characterization of the eye opening, the inner curve represents the eye
opening at BER 1e-12
Figure 19: Output timing measurement for characterization of total jitter at
BER 1e-6
Figure 20: Manually measured TX jitter transfer curve with help of the jitter
sources and measurements provided by J-BERT N4903B
5.000
0.000
-5.000
-10.000
Gai
n (
dB)
-15.000
-20.000Frequency (Hz)
1.00E + 05 1.00E + 06 1.00E + 07 1.00E + 08
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Related Products
J-BERT N4903B
N4916A de-emphasis signal
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oscilloscope
Infiniium DSA91304A High
Performance Oscilloscope
Literature
[1]: PCI Express base specifi cation, revision 2.0 December 20, 2006
[2]: PCI Express card electromechani-cal specifi cation, revision 2.0 April 11, 2007
[3]: Compliance load board (CLB2.0), test fi xture user’s document, April 2, 2008, revision 1.0, PCI-SIG
[4]: Compliance base board (CBB2.0) `test fi xture user’s document, April 2, 2008, revision 1.0, PCI-SIG
[5]: PCI Express revision 2.0 receiver testing, with J-BERT N4903A and 81150A pulse function arbitrary generator, Agilent Technologies, December 2008, 5990-3233EN
[6]: Calibrated jitter, jitter tolerance test and jitter laboratory with the Agilent J-BERT N4903A, 5989-4967EN
[7]: Precision jitter analysis using the Agilent 86100C DCA-J, 5989-1146EN
[8]: De-emphasized signal generation with the Agilent N4916A de-emphasis signal converter, 5989-7193EN
[9]: Total jitter measurement at low probability levels, using optimized BERT scan method5989-2933EN
J-BERT N4903B data sheet,
5990-3217EN
•
•
•
•