Download - PCI-E X4: status report
CERN, 15 April, 2008 TDAQ Working Group 1
PCI-E X4: status report
Two boards currently being mounted
Next week tests
• 12 layer (6 routing)
• FPGA 780 pin with embedded transceivers
• 2100 nets, 2400 vias, 12 power supplies, controlled impedance
• 2.5 gbit/s lines
• DDR2
CERN, 15 April, 2008 TDAQ Working Group 2
Board mounted (side A)
CERN, 15 April, 2008 TDAQ Working Group 3
Fit results with quartus
18k Logic Elements available for the user
CERN, 15 April, 2008 TDAQ Working Group 4
Parameters
• LKr readout (depending on readout implementation)
• CTP interface (the board can act as a CTP coprocessor: 18k Logic Elements free)
• TELL1 readout
• PCI-E - 4 lines – 16 bit @ 125 MHz (2.0 gbit/s) per lane
• Optical link – 4 TLK2501 – 16 bit @ 75-125 MHz (1.2-2.0 gbit/s)
• Copper link – 2-4 DS90CR485 – 48 bit @ 66-133 MHz (3.1-6.3 gbit/s) – maximum working frequency depends on cable length
Can be used for
CERN, 15 April, 2008 TDAQ Working Group 5
LKr trigger proposal
Assumptions:
• 216 LKr readout boards (64 channels per board)
• Digital sum on 4x4 cells on the readout boards
Trigger concentrator boards• Receives 16 readout boards• Peak finding in space and time• Pulse reconstruction with 1-2 ns time resolution• Trigger primitives sorting and propagation to CTP
CERN, 15 April, 2008 TDAQ Working Group 6
1 116 116 1
RO board (CERN): digitization + RO4x4 ch digital sum
1st layer Trig board: cluster reconstrtrig prim gener
2nd layer Trig board:
sortinginterface to CTP
RO boa
rd
(CER
N)
Trig
ger b
oard
Trig
ger b
oard
64 ch4 ch 1024 ch
216 x 16 x 1 x
CTP
• 16 optical input
• 1 optical output
• 9U x 400 mm
LKr Trigger: architecture
CERN, 15 April, 2008 TDAQ Working Group 7
Pulse reconstruction in FPGA (1-2 ns)
CERN, 15 April, 2008 TDAQ Working Group 8
LKr trigger: implementation•The best solution would be to design a completely new system
•A good compromise is to use the existing TELL1 board as a motherboard and design only the interconnections (implemented with TLK2501 + optical transceiver)
•TELL1 was designed some years ago with (now) old components
•TELL1 exists and is working
•We know it (working on LHCb TELL1 muon firmware)
•We already used TLK2501 + optical txrx in an R&D project
OUR STRATEGY
Design a prototype LKr trigger with TELL1 and all the interconnect implemented with TLK2501 + optical transceiver (to minimize design effort).Once it works, if we have time and if needed start the design of the new motherboard
CERN, 15 April, 2008 TDAQ Working Group 9
Throughput estimation
• 30 MHz istant/13k cell ~ 150 kHz/board -> average!
• Our conservative assumption is 10 x average in the central region = ~ 1.5 MHz/board
• 16 bits x 4 pads x 8 samples @ 1.5 MHz = ~ 800 Mbit
-> we can work with 4x4 pads and a TLK2501!
CERN, 15 April, 2008 TDAQ Working Group 10
TELL1 board
24 optical input
CERN, 15 April, 2008 TDAQ Working Group 11
How can we perform halo expansion with TELL1?
• If we work without halo expansion -> 1 optical link for RO card, up to 24 optical input on the trigger concentrator (TELL1)
• If we want halo expansion on the TELL1 we can try the following approach:
each RO card equipped with 1 optical link + 8 lemo out + 8 lemo in cables -> if a seed is found in a RO card one or more neighboring RO cards are flagged for transmission
24 TELL1 input arranged as 16 input + 4 bidirectional links (halo expansion between two different TELL1s) to be checked!
CERN, 15 April, 2008 TDAQ Working Group 12
Why to design a new board?
Pulse time reconstruction is a typical DSP application
Altera Stratix III (E version) with embedded DSP