OR4E FPGA Ver 2.0 1 Lattice Semiconductor Corp 4/1/2002
OR4E FPGA Ver 2.0 2 Lattice Semiconductor Corp 4/1/2002
Series 4 FPGA Evaluation Board Diagram Revision 2.0
OR4E FPGA Ver 2.0 3 Lattice Semiconductor Corp 4/1/2002
JTAG Programming Connection J55 Schematic page 4 An 8-pin connection to the JTAG interface used for programming.
JTAG Connector Pin 1 Vdd Pin 2 TDI Pin 3 TMS Pin 4 TCK Pin 5 TDO Pin 6 Rd_Cfg_n Pin 7 Init_n Pin 8 GND
Serial Programming Connection J57 Schematic page 4 A 7-pin serial connector used for configuration through the serial mode interface
Serial Connector Pin 1 Vdd Pin 2 cclk Pin 3 D0 Pin 4 Done Pin 5 Prog Pin 6 nc Pin 7 GND
General-purpose I/O Header Connections J1, J2, J3, J4, J6, J7, J10 ,J12, J13 Schematic page 5
Standard 0.100 headers are provided for interconnecting points on the board. This can be accomplished with 0.100 IDC connectors and ribbon cable for bus connections or 0.025 pin socket patch cords(such as Pomona Electronics #5948 www.pomonaelectronics.com)
Differential I/O Headers J5, J9, J15, J19, J18 Schematic page 5
Additional 0.100 headers are provided in a 3-pin configuration to provide access to differential LVPECL or LVDS I/O. The 3-pin assemblies provide a center position ground. The headers accept connections to a 3-pin cable assembly such as P/N HDN1610-01 manufactured by W.L. Gore (www.wlgore.com).
OR4E FPGA Ver 2.0 4 Lattice Semiconductor Corp 4/1/2002
Power Supply Modes Schematic page 1
a) Bench Supply ONLY. +5V, 3.3V, 2.5V, 1.5V applied through corresponding banana jacks. J101 in 2-3 position. b) Wall Adapter ONLY. +5V applied through barrel jack. +3.3V, 2.5V, and 1.5V regulated from +5V. J101 in 1-2 position. c) +5V Bench Supply ONLY. +5V applied through +5V banana jack. +3.3V, 2.5V, and 1.85V regulated from +5V. J101 in 1-2 position. d) Wall Adapter and Bench Supply COMBO. +5V applied through barrel connector. +3.3V, 2.5, 1.5V applied through corresponding banana jacks. J101 in 2-3 position.
Selecting VDDIO Levels J64, J59, J63, J69, J72, J77, J73, J68 Schematic page 2
8 independent voltages can be applied to the proper device banks through a 2x3 header and a 2-position shunt. By placing the shunt across the appropriate pins of the header the VDDIO can be sourced from the board to be 1.5V, 2.5V, 3.3V or driven externally through a banana jack. Settings are as follows: Pin 1 – 3 = 3.3V Pin 3 - 5 = 2.5V Pin 4 – 6 = 1.5V Pin 2 – 4 = External
Voltage References and Terminating Voltages J42, J49, J53 Schematic page 2
Connections between banana jacks(J45,J52, J139) VR1, VR2, and VTT are available to an adjacent 2x4 0.100 header. These are used for provided VREF and terminating connections for specific IO settings.
Dip Switch Pull-Up Voltage J119 Schematic page 7
a) 1-2 Position: Resistors are pulled-up to +3.3V. b) 2-3 Position: Resistors are pulled-up to local applied banana jack voltage.
OR4E FPGA Ver 2.0 5 Lattice Semiconductor Corp 4/1/2002
Oscillator Connections to SMA J28 and SMA J38 Output Source Schematic page 4
J24 settings a) 1-2 Position: Output of Y1 connected to SMA J28. b) 2-3 Position: Output of Y2 (15MHz XO) connected to SMA J28. J34 settings a) 1-2 Position: Output of Y3 connected to SMA J38. b) 2-3 Position: Output of Y4 (66MHz XO) connected to SMA J38.
SMA Connections Schematic page 4/7
Each input SMA has an on-board termination scheme that is foot printed but not stuffed. These SMA connectors provide differential input to the PLL clocks as well as differential or single-ended connections to the primary clock pins.
LEDs J46 Schematic page 4
A standard 2x8 0.100 header connects to LEDs. When a jumper cable is used, output from the OR4E device can drive these LEDs to display a pattern. The connections are:
J5 Pin 1 red LED Pin 2 red LED Pin 3 red LED Pin 4 red LED Pin 5 yellow LED Pin 6 yellow LED Pin 7 yellow LED Pin 8 yellow LED Pin 9 green LED Pin 10 green LED Pin 11 green LED Pin 12 green LED Pin 13 red LED Pin 14 red LED Pin 15 red LED Pin 16 red LED
OR4E FPGA Ver 2.0 6 Lattice Semiconductor Corp 4/1/2002
Chip Select Control J23 Schematic page 4
J23 and J27 provide chip select control over the OR4E. If un-shunted the onboard OR4E will be, by default, selected. However, CS can be taken away by shunting either J23, or J27.
DATA0 Control JJ36 Schematic page 8
J36 Provides control over OR4E DATA0 input source. On the OR4E evaluation board (r2), there are three devices inherently capable of driving DATA0: The Serial Port, Parallel Port, and the Windriver MPC860 development daughter-board. J36 segments DATA0 into DATA0_A and DATA0_B: a) 1-2 Position: DATA0 is connected to the MPC860 daughter-board. b) 2-3 Position: DATA0 is connected to the Serial and Parallel port.
Microprocessor Interface JJ1113, J1114, J1115 Schematic page 8
96-pin headers are provided to mate directly with the 860 bus to communicate to a Windriver(www.windriver.com) MPC860 development board.
J16, J17, J21 Schematic page 8 Headers are provided to observe signals of the PowerPC interface. Parallel Port Voltage Stepdown and Buffer Control J54 Schematic page 4
The Parallel Port is designed to be externally driven to 5V levels. The OR4E's inputs are not 5V tolerant. U2 is responsible for shifting 5V levels to approx. 3.3V levels and isolating the parallel interface when not in use. When using the Parallel Port, J54 must be shunted to activate the Buffer IC U2. 5V power to the Parallel Port is assumed to come from the driving device (cable). However, if onboard +5V is to be used L7 must be removed and placed in the L5 position. This option not supported by the device programming software.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3.3V VDDio +2.5V
+1.5VBANANA
SELECTING VDDIO VOLTAGES
2.0
LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD
C
1 1Thursday, March 28, 2002
Title
Size Document Number Rev
Date: Sheet of
VDDIO0
VDDIO1
VDDIO2
VDDIO7
VDDIO4
VDDIO3
VDDIO5 VDDIO5
VDDIO6 VDDIO6
VDDIO2
VDDIO3
VDDIO0
VDDIO4
VDDIO1
VDDIO7
L7C_D3L5C_A0
L14T_A0
L3T_D1
L10C_A0
L6C
_S1
L4C
_A0
L20C
_S1
L8C
_S0
L9C
_D1
L18C
_D0
L12C
_S0
L2T_
D0
L20T_D1L22T_D2
L16C_A1
L17C
_D3
L6T_
S0
L14C
_A3
L13T
_S2
L2T_
A1
L16T
_D0
+1.5V
+3.3V
+2.5V
+1.5V
+1.5V
+3.3V
+2.5V
+1.5V
+1.5V
+3.3V
+2.5V
+1.5V
+1.5V
+3.3V
+2.5V
+1.5V
+3.3V
+1.5V
+3.3V
+1.5V +2.5V
+3.3V
+2.5V+1.5V
+1.5V
+3.3V
+2.5V +1.5V
+3.3V
+2.5V +1.5V
+3.3V
+3.3V
+3.3V
+1.5V
+1.5V
C82
100N
FC
8310
0NF
C85
100N
FC
8410
0NF
C2147UF
J77
111-0102-001Red Banana Jack
1
J61
111-0102-001Red Banana Jack
1
J63
TSW-103-07-T -D2x3 0.100" HDR
21
354
6
VDDio+3.3V
+2.5VVDDio+1.5V
BANANA
J76
TSW-108-07-T-D2x8 0.100" Header
123456789 10 11 12 13 14 15 16
123456789 10 11 12 13 14 15 16
C49 100NF
C27100NF
J64
TSW-103-07-T -D2x3 0.100" HDR
21
354
6
VDDio+3.3V
+2.5VVDDio+1.5V
BANANA
C38
100N
F
C23100NFC25100NF
C47 100NF
C13
747
UF
C46 100NF
C67100NF
C7347UF
C68100NF
J60
TSW-108-07-T -S1x8 0.100" Header
12345678
12345678
C13
447
UF
C51100NF
C37
100N
F
J70
TSW-103-07-T -D2x3 0.100" HDR
21
354
6
VDDio+3.3V
+2.5VVDDio+1.5V
BANANA
OR4E VSS BLOCK
OR4E
CE
NTE
R R
IGH
T [C
R/3
]
MFR: LATTICEPKG: 680PBGA
BOT LEFT [BL/6]
TOP CENTER [TC/1]
CE
NTE
R L
EFT
[CL/
7]
TOP
LE
FT [T
L/0]
TOP RT [TR/2]
BO
T R
T [B
R/4
]
BOTTOM CENTER [BC/5]
P O W E R B L O C K
U1A A1
A2
A18
A33
A34
B1
B34
B33
B2
C3
C13
C22
C32
D4
D31
N3
N13
N14
V16
V17
V18
V19
V34
W16
W17
W18
W19
Y13
N15
N20
N21
N22
N32
P13
P14
P15
P20
P21
P22
R13
R14
R15
R20
Y14
Y15
Y20
Y21
Y22
AA
13A
A14
AA
15A
A20
AA
21A
A22
AB
3
AB
13A
B14
AB
15A
B20
AB
21A
B22
AB
32A
L4A
L31
AM
3A
M13
AM22
AM32AN1AN2
AN33AN34
AP1AP2
AP18AP33AP34
N16N17N18N19
P19
P16
P18
P17
T14
R19
R16
T13
R18
T20
R17
T15
T21
T22
U13U14U15U20U21U22
V13V14V15V20V21V22
W13
W14
W15
W20
W21
W22
Y16Y17Y18Y19
AA16AA17
AA18AA19AB16AB17AB18AB19
A3B3C1C2C4
E5D3
A17
A11
A19
A24
C12
C15
C20
C23
A32
C31B32
D32
C33C34
E30
L34M32R32U34
AC32
W34
AD34
Y32
AK30AL32
AM33AM31
AM34
AP32AN32
AM
12A
M15
AM
20A
M23
AP
24
AP
11
AP
19A
P17
AK5AL3AM1AM2
AP3
AM4AN3
L1M3R3U1
AD1
W1Y3
AC3
F5
AL2AK6
AN31AK31
F30E29
D5
L3M1P3T 4
W2Y5
AB4AC5
AF2
AG1
AH
4A
H5
AL7
AN
6A
K11
AP
9A
K13
AP
14A
P15
AM
16A
L19
AN
20A
L23
AK
23A
P26
AK
25A
N28
AM
29A
M30
AL3
4A
K34
AH
33A
E31
AD32AB33W30V31T32P32M34N30
J31F33J30E32D29A30C27D26
D23
D22
C21
D18
E18
A13
D13D12
C9C8B7E9G4F2K5J1
U18U19V1T16R22R21U17T17T18T19U16
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
S
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
S
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
S
VS
S
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
S
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
S
VSS
VSSVSSVSSVSSVSSVSSVSSVSSVSSVSS
VDD15VDD15VDD15VDD15
VDD
15
VDD15
VDD
15
VDD15
VDD
15
VDD
15
VDD
15
VDD
15
VDD
15
VDD
15
VDD
15
VDD
15
VDD
15VD
D15
VDD15VDD15VDD15VDD15VDD15VDD15
VDD15VDD15VDD15VDD15VDD15VDD15
VDD
15VD
D15
VDD
15VD
D15
VDD
15VD
D15
VDD15VDD15VDD15VDD15VDD15VDD15
VDD15VDD15VDD15VDD15VDD15VDD15
VDDIO0VDDIO0VDDIO0VDDIO0VDDIO0
VDDIO0VDDIO0
VDD
IO1
VDD
IO1
VDD
IO1
VDD
IO1
VDD
IO1
VDD
IO1
VDD
IO1
VDD
IO1
VDDIO2
VDDIO2VDDIO2
VDDIO2
VDDIO2VDDIO2
VDDIO2
VDDIO3VDDIO3VDDIO3VDDIO3
VDDIO3
VDDIO3
VDDIO3
VDDIO3
VDDIO4VDDIO4
VDDIO4VDDIO4
VDDIO4
VDDIO4VDDIO4
VDD
IO5
VDD
IO5
VDD
IO5
VDD
IO5
VDD
IO5
VDD
IO5
VDD
IO5
VDD
IO5
VDDIO6VDDIO6VDDIO6VDDIO6
VDDIO6
VDDIO6VDDIO6
VDDIO7VDDIO7VDDIO7VDDIO7
VDDIO7
VDDIO7VDDIO7VDDIO7
VDD
33
VDD33VDD33
VDD33VDD33
VDD33VDD33
VDD
33
VREF_7_01VREF_7_02VREF_7_03VREF_7_04VREF_7_05VREF_7_06VREF_7_07VREF_7_08
VREF
_6_0
1VR
EF_6
_02
VREF
_6_0
3VR
EF_6
_04
VREF
_6_0
5VR
EF_6
_06
VREF
_6_0
7VR
EF_6
_08
VREF
_6_0
9VR
EF_6
_10
VREF
_6_1
1
VREF
_5_0
1VR
EF_5
_02
VREF
_5_0
3VR
EF_5
_04
VREF
_5_0
5VR
EF_5
_06
VREF
_4_0
1VR
EF_4
_02
VREF
_4_0
3VR
EF_4
_04
VREF
_4_0
5VR
EF_4
_06
VREF
_4_0
7VR
EF_4
_08
VREF_3_01VREF_3_02VREF_3_03VREF_3_04VREF_3_05VREF_3_06VREF_3_07VREF_3_08
VREF_2_01VREF_2_02VREF_2_03VREF_2_04VREF_2_05VREF_2_06VREF_2_07VREF_2_08
VREF
_1_0
1VR
EF_1
_02
VREF
_1_0
3VR
EF_1
_04
VREF
_1_0
5VR
EF_1
_06
VREF_0_01VREF_0_02VREF_0_03VREF_0_04VREF_0_05VREF_0_06VREF_0_07VREF_0_08VREF_0_09VREF_0_10
VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS
C36
100N
F
J68
111-0102-001Red Banana Jack
1
C60
100N
F
C43
100N
FC
4410
0NF
C62
100N
FC
6310
0NF
J66
TSW-108-07-T -D2x8 0.100" Header
123456789
10111213141516 1
23456789
10111213141516
C61
100N
F
C86
100N
F
C88
100N
F
C87
100N
F
C2047UF
C13
947
UF
C40
100N
F
C89
100N
F
C92
100N
F
C39
100N
F
C93
100N
F
C42
100N
FC
4110
0NF
C91
100N
F
C54
100N
F
C90
100N
F
C55
100N
F
J75
TSW-103-07-T -D2x3 0.100" HDR
21
354
6VDDio+3.3V
+2.5VVDDio+1.5V
BANANA
C132 47UF
J65
TSW
-108
-07-
T-S
1x8
0.10
0" H
eade
r12345678
12345678
J58
111-0102-001Red Banana Jack
1
C3147UF
J78
TSW-103-07-T -D2x3 0.100" HDR
21
354
6
VDDio+3.3V
+2.5VVDDio+1.5V
BANANA
C72 100NF
C24100NF
C70 100NF
C71 100NF
C26100NF
C30100NF
C66 100NFC65 100NF
C13
847
UF
C77100NF
C29100NF
C74 100NF
C28100NF
C76100NF
C19 100NF
C75100NF
C13
347
UF
J62
111-0102-001Red Banana Jack
1
C59
100N
F
J74
TSW-103-07-T -D2x3 0.100" HDR
21
354
6VDDio+3.3V
+2.5VVDDio+1.5V
BANANA
C81
100N
F
J67
111-0102-001Red Banana Jack
1
C57
100N
FC
5810
0NF
C79
100N
F
C69 47UF
C80
100N
FC
5610
0NF
J72
111-0102-001Red Banana Jack
1
J73
111-0102-001Red Banana Jack
1
C78
100N
F
C15 100NF
C22100NF
C32100NF
C17 100NFC16 100NF
C34100NF
C33100NF
C5047UF
J71
TSW-108-07-T-S1x8 0.100" Header
12345678
12345678
C13
647
UF
C18 100NF
C64
100N
F
J69
TSW-103-07-T -D2x3 0.100" HDR
21
354
6VDDio+3.3V
+2.5VVDDio+1.5V
BANANA
C13
547
UF
J59
TSW-103-07-T-D2x3 0.100" HDR
21
354
6VDDio+3.3V
+2.5VVDDio+1.5V
BANANA
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLACE ALL CAPS CLOSE TO INPUTSAND OUTPUTS OF REGS!
GREEN LEDINDICATES 5VPRESENT
THE SPECIFIED WALL ADAPTER CANPROVIDE UP TO 4A @ 5V.
ALL LDO REGULATORS CAN SOURCE 3AAT THEIR SPECIFIED VOLTAGE
1.5V
2.5V
POWER SEQUENCER GUARANTEES 1.5V IS ALWAYSPRESENT BEFORE 2.5V, OR 3.3V
3.3VGREEN LED INDICATES 3.3V PRESENCE
GREEN LED INDICATES 2.5V PRESENCE
PLACE ALL CAPS CLOSE TO INPUTSAND OUTPUTS OF REGS!
WHEN USING 5VBANANA JACKENSURE J101 ISIN THE 2-3POSITION
PLACE ALL CAPS CLOSE TO INPUTSAND OUTPUTS OF REGS!
2.0
LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD
C
1 8Thursday, March 28, 2002
Title
Size Document Number Rev
Date: Sheet of
PWR_EN
RELAY+
RELAY+
RELAY+
RELAY+
PWR_EN
PWR_EN
+3.3V
+2.5V
+1.5V
+3.3V
+2.5V
+1.5V
+5V
+5V
+1.5V
+5V
J79
111-0102-001Red Banana Jack
1
GD
23
HLM
P-1790
J100
111-0102-001Red Banana Jack
1
GD
22HLM
P-1790
U3
AMS1503CT5 to 3.3V (3A) Regulator
4
3
2
15
VCONTROL
OUTPUT
ADJ/GND
SENSEVPOWER
R92 4.7K
U5
AMS1503CT5 to 3.3V (3A) Regulator
4
3
2
15
VCONTROL
OUTPUT
ADJ/GND
SENSEVPOWER
J83
111-0102-001Red Banana Jack
1
J85
111-0102-001Red Banana Jack
1
U7
AMS1503CT5 to 3.3V (3A) Regulator
4
3
2
15
VCONTROL
OUTPUT
ADJ/GND
SENSEVPOWER
C203 ALCAP_F
C201 TANT B
R11
2
75R
C204 ALCAP_F
C202 TANT B
R11
312
4R
F1
F1226CT-ND3A Fast-Blo Socketed Fuse
C205 ALCAP_F
F4
F1310CT-ND5A Slo-Blo Socketed Fuse
J80
TSW-102-07-T -S1x2 0.100" Header
12 1
2
F2
F1224CT-ND2A Fast Blo Socketed Fuse
R11
412
4R
R11
512
4R
R10
31K
J81
TSW-102-07-T -S1x2 0.100" Header
12 1
2
C10
010
0NF
C10
410
0NF
Q32N2222
31
2
R11
724
.9R
J82
TSW-102-07-T -S1x2 0.100" Header
12 1
2
R11
6
124R
C200 TANT B
C10
810
0NF
J84
22HP037AMale Power Jack 2.5mm
13
2
Q42P3906
32
1
U6
G5LE-14-DC55Vdc Coil, 10A Capacity Relay
134
5
2COMM
NONC
+5V
GND
J87
111-0103-001Black Banana Jack
1
C98
10U
F
C10
722
UF
T 11
1520-3Turret
T 10
1520-3Turret
C11
110
0NF
U8
G5LE-14-DC55Vdc Coil, 10A Capacity Relay
134
5
2COMM
NONC
+5V
GND
C11
010
0NF
C10
910
0NF
C10
322
UF
R90
4.7K
F3
F1309CT-ND4A Slo-Blo Socketed Fuse
C99
22U
F
T 2
U4
G5LE-14-DC55Vdc Coil, 10A Capacity Relay
134
5
2COMM
NONC
+5V
GND
23
1
J101
123
123
T 1
T3
R162680R
T4
T 5
C97
100N
F
T6
T7
C10
110
0NF
C10
210
UF
T 8
C10
610
UF
C10
510
0NF
G
D24
HLM
P-17
90
R97
680RR
102270R
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLACE CLOSE TO PLL_VF [D30]WHICH PIN IS VSSA_7? -FOR THE FILTER GND
2.0
LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD
C
3 8Thursday, March 28, 2002
Title
Size Document Number Rev
Date: Sheet of
GP3_9GP3_10
GP3_12
GP3_18
DAT
A3
ADDR20
DEB
UG
_BU
S9
DAT
A24
DAT
A19
DAT
A17
GP7_32
DAT
A7
GP3_6
GP4
_8G
P4_7
GP5
_1
ADDR3
GP5
_0
GP7_5
DEB
UG
_BU
S1
DAT
A20
ADDR1
DEB
UG
_BU
S2
DAT
A26
DAT
A10
ADDR12
GP3_7GP3_8
GP4
_2
GP4
_5G
P4_6
GP5
_2
GP7_6
ADDR19
DEB
UG
_BU
S14
ADDR9
ADDR11
GP3_5
GP3_13
GP4
_4
GP5
_5
GP7_12
DEB
UG
_BU
S13
DEB
UG
_BU
S3
ADDR13
GP3_0
GP3_16
GP4
_9
DAT
A1
GP7_7
GP3_15
GP3_17
GP4
_0
GP5
_6
DEB
UG
_BU
S5D
EBU
G_B
US4
ADDR6
ADDR10
DAT
A2
GP5
_4
GP7_31
GP7_8
ADDR8
GP3_2GP3_1
GP5
_7
GP5
_3
GP7_9
GP7_4
GP7_1
DEB
UG
_BU
S0
DEB
UG
_BU
S15
ADDR16
DAT
A6
GP3_3
GP7_14
GP7_10
ADDR2
ADDR14
ADDR17
DAT
A5
DAT
A1
GP3_14
ADDR7
DATA4
DAT
A3
GP3_11
GP4
_1
GP7_3
ADDR18
DEB
UG
_BU
S7
ADDR0
ADDR4ADDR5
GP3_4
DAT
A2
DEB
UG
_BU
S6
ADDR15
DAT
A7
DAT
A4
GP7_13
GP7_0
DAT
A0
ADDR21
DEB
UG
_BU
S12
DEB
UG
_BU
S10
DAT
A0
DAT
A5
GP7_11
GP7_2
DEB
UG
_BUS
11
DEB
UG
_BU
S8
GP4
_3
GP7_15
DAT
A6
DAT
A15
DAT
A16
DAT
A25
DAT
A9
DAT
A27
DAT
A11
DAT
A21
DAT
A22
DAT
A31
DAT
A29
DAT
A23
DAT
A14
DAT
A28
DAT
A12
DAT
A13
DAT
A18
DAT
A30
DAT
A8
GP7_18
GP7_27GP7_26
GP7_21
GP7_25GP7_24
GP0_0
GP0_8
GP0_21
GP0_1
GP0_16
GP0_6
GP0_15
GP0_4
GP0_10
GP0_13
GP0_14
GP0_11
GP0_9
GP0_26
GP0_5
GP0_12
GP0_7
GP0_2GP0_3
GP0_17
GP0_25GP0_24
GP0_18
GP0_19
GP0_20
GP0_23GP0_22
GP1
_10
GP1
_1
GP1
_8
GP1
_13
GP1
_12
GP1
_0
GP1
_3G
P1_2
GP1
_6
GP1
_18
GP1
_4
GP1
_11
GP1
_7
GP1
_5
GP1
_9
GP1
_15
GP1
_14
GP1
_20
GP1
_16
GP1
_17
GP1
_19
GP2_9
GP2_5
GP2
_32
GP2
_33
GP2
_41
GP2_2
GP2_6
GP2
_40
GP2_8
GP2
_39
GP2_4
GP2_12
GP2_10
GP2_30
GP2_15
GP2_1
GP2_11
GP2_29
GP2
_35
GP2_14
GP2
_34
GP2_7
GP2_13
GP2_3
GP2_31
GP2_0
GP2_28
GP2_25
GP2_27
GP2
_26
GP2_24
GP2
_16
GP2_23
GP2_22
GP2
_17
GP2_21
GP2_20
GP2
_19
GP2
_18
GP2
_38
GP2
_37
GP2
_36
GP7_16
GP7_17
GP7_19GP7_20
GP7_22
GP7_23
GP7_28
GP7_30
GP7_29
GP6
_19
GP6_6GP6_5
GP6_14
GP6
_13
GP6_3
GP6
_21
GP6
_17
GP6
_15
GP6_9
GP6_0
GP6_8
GP6_11GP6_12
GP6_26
GP6
_31
GP6
_22
GP6
_20
GP6_10
GP6
_30
GP6
_28
GP6
_27
GP6_7
GP6
_16
GP6_1
GP6_4
GP6
_29
GP6
_25
GP6
_18
GP6_2
GP6
_34
GP6_24GP6_23
GP6
_32
GP6
_33
GP6
_35
GP6
_36
TCK
M0
GP6_[36:0]
DEBUG_BUS[15:0]
M2PR
GR
M_N
GP2_[41:0]
DATA[31:0]
ADDR[21:0]
CFG
_IR
Q_N
M3TD
I
M1
GP1_[20:0]
TMSCC
LKR
ESET
_N
GP3_[18:0]
RD
_DAT
A/TD
O
HD
C
GP7_[32:0]
LDC
_N
GP4_[9:0]GP5_[7:0]
L15C_D1
L17C_D2L17T_D2
L8T_
S0
L21C_A0
L19C_A1
L18T_A1
L14T_D0
L12C_D2
L2C_D0
L3C
_A1
L21T_A0
L10T_A0
L15T_D2L14C_D0
L11T
_S0
L7T_
A0
L3T_
A1
L8T_A0L7C_A2
L1C_A0
L19T_A1
L11C_A0
L5T_S0
L9T_D1
L5C_S0
L1C
_D2
L9C_A0
L10C_D2
DO
UT
L21C
_D3
L6T_S1
L4T_A0
L9C
_S0
L2C
_A1
L20C_D1
L17C_A1
L1T_A0
L5T_
A1
L11T_D1
L16T_A1
L12T_A0
L8C_D1
L14C_A0
L3C_D1
L13C_S2
L18C_A1
L12C_A0
L15C_D2
L12T_D2
L11C_D1
L6T_D1
L2T_D1
L18T
_D0
L6C
_S0
L6C_D1
L1C_D1L1T_D1
L20T
_S1
L16C_D0
L8C_A0
L3C_S1
L7C
_A0
L4C_D0
L17T_A1
L8T_D1L7T_D3
L5T_A0
L19C
_D2
L19T
_D2
L7T_A2
L3T_S1L9
T_S0
L5C
_A1
L9T_A0
L22C_D2
L4T_D0
L15T_D1
L11T_A0
L2C_D1
L21T
_D3
L1T_
D2
L10T_D2
L16C
_D2
L13C
_T2
L12T
_S0
L15C
_A0
L14T
_A3
L16T
_D2
L11C
_S0
L18T
_A0
L18C
_A0
L13T
_T2
L15T
_A0
L17T
_D3
L4C
_S0
L4T_
S0
L10C
_S0
L10T
_S0
INIT
_N
DO
NE
PTE
MP
TEST
CFG
CS0
_NC
S1
GP0_[26:0]
UR
PLL1
_TU
RPL
L1_C
LRPLL2_C
LRPLL2_T
LLH
PP
LL_C
LLH
PP
LL_T
ULHPPLL_TULHPPLL_C
ULPPLL_CULPPLL_T
LLP
PLL
_TLL
PP
LL_C
LRPPLL_T
LRPPLL_C
UR
PP
LL_T
UR
PP
LL_C
RD
_CFG
_N
L13C_D2L13T_D2
PLCK1CPLCK1T
PLCK0CPLCK0T
PTC
K0T
PTC
K0C
PTC
K1T
PTC
K1C
+3.3V
ADD
R[2
1:0]
TOP LEFT [TL/0]
JTAG MODECTRL
SLAVE SERIAL MODE
SLAVE PARALLEL MODE(including DATA4)
TOP CENTER [TC/1]
TOP RT [TR/2]
CE
NTE
R L
EFT
[CL/
7]
BOTTOM LEFT [BL/6] BOTTOM CENTER [BC/5]
BOT RT [BR/4]
CE
NTE
R R
IGH
T [C
R/3
]
OR4EMFR: LATTICEPKG: 680PBGA
I N P U T / O U T P U T B L O C K
U1B
ORCA
E4
E3
D2
G5
D1
F4 E2
H5
J5F1H3
G2
G1J4 L5 H
1
J2
K3
L4K2
N5
P5
N1N4P2
U5
T 2T 3
U2V2
W5
W4AA1
Y4AA5AB1
AA4
AC2AD2AD3AE1AE2
AD4AE3
AF1
AF3
AF4
AG3
AG4
AG5
AK
1A
K2
AK
4
AL5
AN
4A
K7
AN5
AK
9A
M7
AM
8A
K10
AP
7A
M9
AL1
0A
P8
AM
10A
N10
AP
10A
L12
AP
12A
P13
AK
15A
M14
AK
16A
L15
AM
17A
M18
AM
21A
L21
AL30AP31
AJ30AK32
W33
T34
Y34
U31
E31
G30
D30
C30
B31
A20
B20
A22
D20
A23
B22
B23
B24
E23
C24
B25
E24
C25
E19
A15
E17
B17
C17
B16
C16
E16D14
A12
B12
E15
B11
C11
E14
D11
B9
A9
D9A8B8
E12
E11
A7
C7
D7
D6
C6
E7
E6
B4
F3E1H4G3J3H2K4M5
K1L2M4M2N2P1R5T 5P4R1R2R4T 1V5U4U3V3V4
W3Y1Y2
AA2AA3AB2AB5AC1AC4AD5
AE4AE5AG2AF5AH1AH3AH2AJ2AJ3AJ4AJ1AJ5AK3AM5AP4
AL6
AM
6A
K8
AP
5A
P6
AL8
AN
7A
L9A
N8
AN
9A
K12
AL1
1A
N11
AM
11A
N12
AK
14A
L13
AN
13A
N14
AL1
4
AN
15
AN
16A
K17
AL1
6
AP
16A
N17
AL1
7
AN
18A
L18
AK
18A
M19
AN
19A
P20
AL2
0
AP
21A
N21
AK
19A
K20
AP
22A
N22
AK
21
AL2
2A
K22
AN
23A
P23
AN
24A
M24
AL2
4A
P25
AN
25
AK
24
AN
26
AL2
5A
M25
AM
26
AP27AN27AL26AM27AK26AP28AL27AL28
AK
27
AM
28A
N29
AK28
AP29AL29
AP30AN30AK29AL33AH30AJ31AJ32AH31AK33AG30AJ33
AF30
AJ34AG31
AH
32
AG32
AE
30
AH
34AF
31
AF32
AG33
AG34
AF33
AD
30AF
34
AE32AC30
AD31
AE33AC31
AE34
AB30
AD33
AB31AA30
AA31
AC33
AC34
AA32Y30
Y31
AB34
AA34
AA33W31
Y33
W32
V30V33V32U33U32
T33
T31
U30
R31R34
R33
P34
T30
P31P33
R30
N33N31
N34
M31M33
P30
L32
L31L33
K34K33
K32
K31
J34
H34
J33
J32
G34
M30
H33
H32
L30
H31
G33
F34
G32
K30
G31
E34D34F32F31E33D33H30E28B30A31D28B29E27C29E26A29D27C28B28E25A28C26B27D25A27A26B26
D24
A25
E22
D21
E21
E20
A21
B21
D19
B19
C19
B18
C18
D17
A16
D16
B15
D15
A14
B14
B13
C14A10B10C10D10E13
D8A6
E10A5B6A4B5C5E8
AL1
RD
_DAT
A/TD
O
RES
ET_N
RD
_CFG
_NPR
GR
M_N
PLL
_CK
0CPL
L_C
K0T
DAT
A5D
ATA6
HD
CLD
C_N
TEST
CFG
DAT
A7
ADDR17C
S0_N
CS
1
INIT
_N
DO
UT
ADDR16
ADDR15ADDR14
DATA4
RDY/BUSY_N/RCLK
ADDR13ADDR12ADDR11
RD_N/MPI_STRB_N
PLCK0CPLCK0T/SCKA
ADDR10ADDR9ADDR8
PLCK1CPLCK1T/SCKB
ADDR7ADDR6ADDR5
WR_N/MPI_RW
ADDR4ADDR3ADDR2ADDR1ADDR0
DP0DP1
DAT
A8D
ATA9
DAT
A10
DAT
A11
DAT
A12
DAT
A13
PLL
_CK
7CPL
L_C
K7T
PTE
MP
DP2
PLL_
CK6
TP
LL_C
K6C
DP3
DAT
A14
DAT
A15
DAT
A16
DAT
A17
DAT
A18
DAT
A19
DAT
A20
DAT
A21
DAT
A22
DAT
A23
DAT
A24
DAT
A25
DAT
A26
DAT
A27
DAT
A28
DAT
A29
DAT
A30
DAT
A31
PB
CK
0TP
BC
K0C
PB
CK
1TP
BC
K1C
PLL_CK5TPLL_CK5C
PLL_CK4TPLL_CK4C
PRCK1C
PRCK0T
PRCK1T
PRCK0C
PLL_
CK3
TP
LL_C
K3C
PLL
_VF
PLL
_CK
2CPL
L_C
K2T
DEB
UG
_BU
S3D
EBU
G_B
US4
DEB
UG
_BU
S5D
EBU
G_B
US6
DEB
UG
_BU
S7D
EBU
G_B
US8
DEB
UG
_BU
S9D
EBU
G_B
US1
0D
EBU
G_B
US1
1D
EBU
G_B
US1
2D
EBU
G_B
US1
3D
EBU
G_B
US1
4D
EBU
G_B
US1
5
DEB
UG
_BU
S2D
EBU
G_B
US1
DEB
UG
_BU
S0
PTC
K1C
PTC
K1T
PTC
K0C
PTC
K0T
MPI_RTRY_NMPI_ACK_N
M0
M1
MPI_CLK
A21/MPI_BURST_N
M2
M3
MPI_TEA_N
DAT
A0
TMS
ADDR20/MPI_BDIP_NADDR19/MPI_TSZ1ADDR18/MPI_TSZ0
DAT
A3
DAT
A1D
ATA2 TD
ITC
K
PLL
_CK
1CPL
L_C
K1T
CFG
_IR
Q_N
/MPI
_IR
Q_N
CC
LKD
ON
E
PL3DPL5DPL7DPL7CPL11DPL11CPL11APL13A
PL15DPL15CPL17DPL17CPL20DPL20CPL20APL21APL22DPL22CPL22APL22BPL23APL23BPL24BPL24APL25BPL25APL27DPL27CPL27APL28APL29APL31DPL33DPL33CPL35APL37A
PL38APL40DPL41DPL41CPL43DPL43CPL44BPL45DPL45APL46DPL46APL47BPL47APB2BPB3A P
B3C
PB
3DP
B5C
PB
5DP
B7C
PB
7DP
B9A
PB
10A
PB
11A
PB
12A
PB
13A
PB
13B
PB
14A
PB
14B
PB
15C
PB
15D
PB
17C
PB
17D
PB
19A
PB
20A
PB
21A
PB21
C/L
1T_D
2PB
21D
/L1C
_D2
PB
22A
PB
22D
/L2C
_A1
PB
23A
/L3T
_A1
PB
23B
/L3C
_A1
PB
24B
/L5C
_A1
PB
24A
/L5T
_A1
PB24
D/L
6C_D
0PB
25C
/L7T
_A0
PB
25D
/L7C
_A0
PB26
C/L
8T_A
0
PB
27A
PB27
C/L
9T_A
0P
B27
D/L
9C_A
0
PB
28A
PB
29A
PB29
C/L
11T_
A0P
B29
D/L
11C
_A0
PB
30A
PB30
C/L
12T_
A0PB
31C
/L13
T_D
2PB
31D
/L13
C_D
2PB
32C
/L14
T_A3
PB33
C/L
15T_
A0P
B33
D/L
15C
_A0
PB34
C/L
16T_
D2
PB34
D/L
16C
_D2
PB
35A
PB35
C/L
17T_
D3
PB
36A
PB36
C/L
18T_
A0P
B36
D/L
18C
_A0
PB
37A
PB37C/L1T_A0PB37D/L1C_A0PB38D/L2C_D0PB39C/L3T_D1PB39D/L3C_D1PB40C/L4T_A0PB41C/L5T_A0PB41D/L5C_A0
PB
42C
PB
43A
PB
43D
PB44C/L6T_D1
PB45B/L7C_A2PB45A/L7T_A2
PB45C/L8T_A0PB45D/L8C_A0PB46C/L9T_D1
PR45C/L12T_D2PR45D/L12C_D2PR44D/L13C_D2PR43C/L14T_D0PR43D/L14C_D0PR42C/L15T_D2PR42D/L15C_D2PR41D/L16C_D0
PR
40A
PR40C/L17T_D2PR40D/L17C_D2P
R39
A
PR39
C/L
18T_
D0
PR
38A
PR38
C/L
19T_
D2
PR38
D/L
19C
_D2
PR
37A
PR37
C/L
20T_
D1
PR
36A
PR
36B
PR36
C/L
21T_
D3
PR36
D/L
21C
_D3
PR35C/L1T_D1PR35D/L1C_D1
PR34A
PR34C/L2T_D1PR34D/L2C_D1
PR33B
PR33D/L3C_D1
PR32B
PR32C/L4T_D0PR32D/L4C_D0
PR31A
PR31C/L5T_A0
PR30A
PR30C/L6T_D1PR30D/L6C_D1
PR29B
PR29C/L7T_D3
PR28A
PR28C/L8T_D1PR28D/L8C_D1
PR27A
PR26A
PR26C/L10T_A0PR25C/L11T_A0PR25D/L11C_A0PR24A/L12T_A0PR24B/L12C_A0
PR23A
PR23D/L14C_A0
PR22A
PR22C/L15T_D1PR22D/L15C_D1
PR21A
PR21C/L16T_A1
PR20A
PR20C/L17T_A1PR20D/L17C_A1
PR19B
PR19C/L18T_A1PR19D/L18C_A1
PR18B
PR18C/L19T_A1PR18D/L19C_A1
PR17A
PR17D/L20C_D1
PR16DPR15A
PR15C/L21T_A0PR15D/L21C_A0
PR14A
PR14D/L22C_D2
PR
13B
PR
13A
PR13
CPR
12C
PR12
DP
R11
APR
11C
PR11
DP
R10
APR
10C
PR10
DP
R9A
PR9D
PR8C
PR8D
PR7CPR6APR6CPR6DPR5CPR5DPR4C
PT46DPT46CPT45CPT44DPT44CPT43DPT43CPT42CPT41DPT41CPT40DPT39DPT39CPT38DPT37DPT37APT36DPT36CPT36APT36B
PT3
5AP
T35B
PT31
DPT
31C
PT2
9AP
T28A
PT27
DPT
27C
PT2
7A
PT25
DPT
25C
PT2
4AP
T24B
PT2
3AP
T23B
PT2
2AP
T21A
PT20
DPT
20C
PT2
0AP
T19A
PT17DPT12DPT12CPT12APT11CPT11APT7CPT5DPT4BPT4APT3DPT3BPT3APT2BPT2A
LVD
S_R
R88 6KC14 10NF
C13 100PF
R89
100R
R87 4.7K
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROGRAM AND RESET SWITCHES
Vr2
GENERAL PURPOSE HEADER CONNECTED TO 16 LEDS
Vr1
DONE AND INIT_N STATUS LEDS
GREEN LED INDICATES COMPLETIONOF CONFIGURATION LOAD
RED LED INDICATES 1ST STAGE OFCONFIGURATIONIN PROGRESS
GENERAL PURPOSE BANANAS
Vtt
GENERAL PURPOSE FREQUENCY SOURCES
NOTE: THESE LEDs ARE DESIGNED TO OPERATEON 3.3V. IF A LOWER VOLTAGE IS APPLIEDLIGHT MAY BE DIM OR NIL.
RESISTOR SOCKETS
100R ARE INTENDED TO PROTECT IC AGAINSTEXTERNAL DRIVING OF PINS DURING CONFIG.OPERATION IS NOT GUARANTEED IF THESEPINS ARE DRIVEN DURING CONFIG/RESET.
POST CONFIG/MISC I/O HDR CS CONTROLS/GPIO
RESISTOR OPTIONS TOSUPPORTACTIVE LOW ORACTIVE HIGH ENABLE
DEFAULT CHIP SELECT: THIS BOARD
USE CAUTION IF JUMPING IS DESIRED
ASSUME POWER WILL BE SUPPLIED THROUGH PARALLEL CABLE
DIODE DROPS VOLTAGE FROM 5 TO 4.3V.RESULT IS AN OUTPUT VOLTAGE EQUAL TO 4.3V-1V = 3.3V
JUMPER MUST BE ONIN ORDER TO USEBUFFER
SERIAL PORT
SOCKET SUPPORT FOR DIP14 OSCILLATORS
PARALLELPORT
JTAG PORT
SHARED LVDS/SMA CONNECTORS
ALL BIASING NETWORKS ARE LEFT OPEN AT TIME OF BUILD
2.0
LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD
C
4 8Thursday, March 28, 2002
Title
Size Document Number Rev
Date: Sheet of
INIT_N
DONE
CCLKDATA0_A
PRGRM_N
DONE
DATA0_ADATA1DATA2DATA3DATA4DATA5DATA6DATA7
DATA0_A
PRGRM_N RESET_N
L17C_D3
L12T_A0
L12C_A0
CS0_N
CS1
INIT_NDONE
TMSTCK
INIT_NRD_CFG_N
INIT_N
RD_DATA/TDO
TDI
DONE
DOUT
M2LDC_N
INIT_N
HDCM3
M1M0
PTEMP
RD_CFG_N
TESTCFG
DONERESET_N
L17T_D3
PRGRM_NCCLK
DATA[31:0]
DATA0_A
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+5V +3.3V
+3.3V
+3.3V
+3.3V
+3.3V
23
1
J34
TSW-103-07-T -S1x3 0.100" Jumper Header
123
123
C5
100N
F
R D1
Y4
VCC1-B0B-66M00066MHz Oscillator
12
4 3
NCGND
VCC OUT
SW5
B3F-1150Momentary Switch
J38
901-143-6SMA 50r Connector
L5 LOPEN
R8 OPEN-0603
Y2
VCC1-B0B-15M00015MHz Oscillator
12
4 3
NCGND
VCC OUT
R6 OPEN-0603
R D4
R81 100R
R D3
R D2
R22 OPEN-0603R21 OPEN-0603
J57
103906-67 Pin Serial Connector
54
21
76
3
PROGDONE
CCLKVDD
GNDNC
D0
Y D7
Y D6
R47
4.7K
Y D5
J27
TSW-102-07-T-S1x2 0.100" Header
121
2
Y D10
J39
111-0102-001Red Banana Jack
1
R39 680R
J42
TSW-104-07-T -D2x4 0.100" Header
1234 5
6781
234 5
678
C130
J46
TSW-108-07-T-D2x8 0.100" Header
123456789
10111213141516
12345678910111213141516
R158
R1 1.6R
R83 100R
G D13
G D12
L1 1UH
R159
C131
J47
901-
143-
6SM
A 50
r Con
nect
or
C3
100N
F
G D14
J43
901-
143-
6SM
A 50
r Con
nect
or
G D11
R40 OPEN-0603R38 OPEN-0603
R161
R160
J54
TSW-102-07-T -S1x2 0.100" Header
12 1
2
R D16
R D15
R72
4.7K
C4
100N
F
L7 1UH
R D20
R84 100R
R D17
R86 100R
R11
4.7K
R10 100R
R48
4.7K
J45
111-0102-001Red Banana Jack
1
J49
TSW-104-07-T -D2x4 0.100" Header
1234 5
6781
234 5
678
J28
901-143-6SMA 50r Connector
C2
100N
F
R25 100R
R31100R
R26 100R R27100R
J52
111-0102-001Red Banana Jack
1
R41 680R
R33100R
23
1
J24
TSW-103-07-T -S1x3 0.100" Jumper Header
123
123
C1
100N
F
Q12N2222
31
2
J53
TSW-104-07-T -D2x4 0.100" Header
1234 5
6781
234 5
678
R42 680R
R44 680R
R36100R
R43 680R
R69 10K
R19 1.6R
L9 1UH
L2 1UH
J37
TSW-108-07-T-D2x8 0.100" Header
12345678 9
101112131415161
2345678 9
10111213141516
R50
100R
110-93-314-41-001DIP14 Oscillator Socket
Y1
17
14 8
NCGND
VCC OUT
L8 1UH
R45 680R
R49 680R
R46 680R
R52 680R
R54 680R
U2
IDTQS3861SO10 Bit Quick Switch
1
234567891011
1224
23
22212019181716151413
NC
A0A1A2A3A4A5A6A7A8A9
GNDVCC
BEn
B0B1B2B3B4B5B6B7B8B9
L4 1UH
R56 680R
R62 680R
L3 1UH
L6 1UH
C6
100N
F
R58 680R
R64 680R
R68 680R
R66 680R
L10 1UH
R2
4.7K
J55
103906-78 Pin JTAG Connector
12345678
VDDTDITMSTCKTDORD_CFGINIT_NGND
R34 1.6R
R51
100R
C7 100NF
R77
4.7K
R30 100RR28 100R
OPE
N2
OPE
N-0
603
OPE
N1
OPE
N-0
603
R73
4.7K
R35 100RR32 100R
OPE
N3
OPE
N-0
603
R75
4.7K
R74
4.7K
OPE
N4
OPE
N-0
603
D8
1N41
48
R78 100RR76
4.7K
110-93-314-41-001DIP14 Oscillator Socket
Y3
17
14 8
NCGND
VCC OUT
R80 100RR79 100R
R57
R55
C12
47P
F
R53
1/4W RESISTOR SOCKET (0.025")
R150 0R
R82 100R
R12 1.6R
R24 100R
C9
47P
F
R23 100R
R70
C10
47P
F
R67
R65
C11
47P
F
R63
R59
R29100R
D9
1N41
48
R151 0R
L11 1UH
J50
TSW-108-07-T -S1x8 0.100" Header
12345678
12345678
J23
TSW-102-07-T-S1x2 0.100" Header
121
2
C8 47UF
R152 0R
R153 0R
R1322R
J51
TSW-108-07-T -S1x8 0.100" Header
12345678
12345678
J56
747846-2Female DB25 w/ non-standard pinout
123456789
10
11
12
13
14
1516
17
1819202122232425
GNDCCLKPROG_ND7D6D5D4D3D2
GND
D1
GND
D0
GND
DONEINIT_N
VDD
GNDGNDGNDGNDGNDGNDGNDGND
R3 22R
R3722R
R20 22R
J40
901-
143-
6SM
A 50
r Con
nect
or
J35
901-
143-
6SM
A 50
r Con
nect
or
R60
680R
R15 OPEN-0603
C128
R154
R155
D21 1N4148 R71 10K
R61
680R
R14 OPEN-0603
R
D19
HLM
P-17
00G
D18
HLM
P-17
90C129
R156
R85 100R
R157
R7 100R
SW4
B3F-1150Momentary Switch
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
I N P U T / O U T P U THEADERS
(by bank)
BOTTOM CENTER BOTTOM RIGHT
CENTER RIGHT
TOP RIGHTTOP CENTER
BOTTOM LEFT
CENTER LEFT
TOP LEFT
ANY NETS SHOWING A TRUE AND COMPLEMENTWERE ROUTED AS LVDS PAIRS
GROUPED BUS LINES
2.0
LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD
C
5 8Thursday, March 28, 2002
Title
Size Document Number Rev
Date: Sheet of
GP4_7GP4_9
GP4_4
GP4_1GP4_2GP4_3
GP4_5GP4_6
GP4_0
GP4_8
GP1_4
GP1_16
GP1_1
GP1_5
GP1_10
GP1_7GP1_6
GP1_14
GP1_0
GP1_9
GP1_13
GP1_15
GP1_3
GP1_12
GP1_2
GP1_8
GP1_11
GP2_32
GP2_9
GP2_11
GP2_8GP2_41
GP2_33
GP2_13GP2_12
GP2_6
GP2_3
GP2_38
GP2_35
GP2_10
GP2_0
GP2_15
GP2_4
GP2_40
GP2_34
GP2_7
GP2_5
GP2_1
GP2_14
GP2_37GP2_36
GP2_39
GP2_2
GP5_2
GP5_0
GP5_6
GP5_1
GP5_5GP5_4GP5_3
GP5_7
GP1_17GP1_18GP1_19GP1_20
GP2_16GP2_17GP2_18GP2_19GP2_20GP2_21GP2_22GP2_23GP2_24GP2_25GP2_26GP2_27GP2_28GP2_29GP2_30GP2_31
GP3_14
GP3_2GP3_1
GP3_12
GP3_15
GP3_8
GP3_10
GP3_3
GP3_11
GP3_6
GP3_13
GP3_7
GP3_0
GP3_4
GP3_9
GP3_5
GP3_16GP3_17GP3_18
GP6_4
GP6_1GP6_32
GP6_9
GP6_6
GP6_2
GP6_0
GP6_12
GP6_34GP6_35
GP6_33
GP6_10
GP6_5
GP6_3GP6_36
GP6_13
GP6_7
GP6_15
GP6_11
GP6_8
GP6_16GP6_17GP6_18GP6_19GP6_20GP6_21GP6_22GP6_23GP6_24GP6_25
GP6_27GP6_28GP6_29GP6_30GP6_31
DEBUG_BUS2 DEBUG_BUS13
DEBUG_BUS0 DEBUG_BUS15
DEBUG_BUS5DEBUG_BUS6DEBUG_BUS7
DEBUG_BUS14DEBUG_BUS1
DEBUG_BUS4DEBUG_BUS3
DEBUG_BUS10
DEBUG_BUS8
DEBUG_BUS11
DEBUG_BUS9
DEBUG_BUS12
GP0_0
GP0_9
GP0_24
GP0_10
GP0_15
GP0_11
GP0_7
GP0_3
GP0_26
GP0_22
GP0_2
GP0_6 GP0_25
GP0_8
GP0_12GP0_20
GP0_4
GP0_13
GP0_23
GP0_1
GP0_14
GP0_19
GP0_5
GP7_13
GP7_25
GP7_28
GP7_12
GP7_5
GP7_0
GP7_15
GP7_8
GP7_17
GP7_7
GP7_29
GP7_24
GP7_11
GP7_3GP7_4
GP7_21GP7_20
GP7_2
GP7_9
GP7_18
GP7_1
GP7_10
GP7_14
GP7_19
GP7_26GP7_6
GP7_30
GP7_27
GP7_22
GP0_[26:0] GP2_[41:0]
GP5_[7:0]GP4_[9:0]
GP6_[36:0]
GP1_[20:0]
GP3_[18:0]GP7_[32:0]
L2T_A1
L7C_A0
L15T_A0
L8C_S0
L1T_D2
L4C_S0L5C_A1
L2C_A1
L4T_S0
L14T_A3
L6C_S0
L14C_A3
L1C_D2
L3C_A1
L5T_A1
L15C_A0L16C_D2
L3T_A1
L8T_S0L7T_A0L6T_S0
L16T_D2
L9C_S0
L1C_A0
L11C_D1L10T_D2
L12C_D2
L16C_D0
L4C_A0
L10C_D2
L15T_D2
L2T_D0
L9T_D1
L1T_A0L2C_D0
L14C_D0
L7T_A2L8C_A0L8T_A0
L12T_D2
L15C_D2
L11T_D1
L4T_A0
L16T_D0
L9C_D1
L7C_A2
L14T_D0
L17T_D3L18C_A0L17C_D3
L18T_A0DEBUG_BUS[15:0]
L22C_D2
L19T_A1
L22T_D2
L17C_A1L18T_A1
L21C_A0
L18C_A1L19C_A1
L21T_A0
L17T_A1
L19C_D2L19T_D2
L17T_D2
L20C_D1
L18T_D0
L21T_D3
L17C_D2L18C_D0
L21C_D3
L20T_D1
L20C_S1L20T_S1
L5C_A0
L8C_D1
L12T_A0
L6C_S1
L14C_A0
L16C_A1
L11T_A0
L12C_S0
L5T_S0
L12T_S0
L7C_D3
L13C_T 2
L6T_S1
L4C_D0
L14T_A0
L13T_T2
L1C_D1
L6C_D1
L9C_A0
L2C_D1
L11T_S0
L9T_S0
L4T_D0
L13T_D2
L2T_D1
L12C_A0
L7T_D3
L10C_A0
L3T_D1
L13C_D2
L6T_D1
L11C_S0
L15T_D1
L1T_D1
L13C_S2L13T_S2
L10T_S0
L16T_A1
L8T_D1
L10C_S0
L11C_A0
L15C_D1
L3C_S1
L3C_D1
L10T_A0
L3T_S1
L5C_S0
L9T_A0
L5T_A0
PTCK0T
PTCK0C
PTCK1T
PTCK1C
PLCK0C
PLCK0T
PLCK1T
PLCK1C
CCLK
J11
TSW-108-07-T -S1x8 0.100" Header
12345678
12345678
J20
TSW-108-07-T-D2x8 0.100" Header
12345678 9
101112131415161
2345678 9
10111213141516
J1
TSW-116-07-T -D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J6
TSW-116-07-T -D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J13
TSW-108-07-T -S1x8 0.100" Header
12345678
12345678
J5A
TSW-116-07-T-T3x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J4
TSW-116-07-T -D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J15A
TSW-116-07-T-T3x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J5B
TSW-116-07-T-T3x16 0.100" Header
33343536373839404142434445464748
33343536373839404142434445464748
J15B
TSW-116-07-T-T3x16 0.100" Header
33343536373839404142434445464748
33343536373839404142434445464748
J10
TSW-108-07-T -D2x8 0.100" Header
12345678 9
101112131415161
2345678 9
10111213141516
J18A
TSW-108-07-T-T3x8 0.100" Header
12345678 9
101112131415161
2345678 9
10111213141516
J18B
TSW-108-07-T-T3x8 0.100" Header
1718192021222324
1718192021222324
J3
TSW-108-07-T-D2x8 0.100" Header
12345678910111213141516
123456789
10111213141516
J19A
TSW-108-07-T-T3x8 0.100" Header
12345678 9
101112131415161
2345678 9
10111213141516
J9A
TSW-108-07-T-T3x8 0.100" Header
12345678 9
101112131415161
2345678 9
10111213141516
J9B
TSW-108-07-T-T3x8 0.100" Header
1718192021222324
1718192021222324
J19B
TSW-108-07-T-T3x8 0.100" Header
1718192021222324
1718192021222324
J2
TSW-116-07-T-D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J7
TSW-116-07-T -D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J14A
TSW-116-07-T-T3x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J8
TSW-108-07-T -S1x8 0.100" Header
12345678
12345678
J12
TSW-116-07-T-D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J14B
TSW-116-07-T-T3x16 0.100" Header
33343536373839404142434445464748
33343536373839404142434445464748
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
2.0
LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD
C
6 8Thursday, March 28, 2002
Title
Size Document Number Rev
Date: Sheet of
URPPLL_CULHPPLL_T
LLHPPLL_CLRPLL2_T
ULPPLL_C
LLPPLL_CLLHPPLL_T
URPLL1_C
LLPPLL_T
URPLL1_T
LRPPLL_C
ULHPPLL_C
LRPLL2_CLRPPLL_T
ULPPLL_TURPPLL_T
+3.3V+3.3V
+3.3V +3.3V
+3.3V +3.3V
+3.3V +3.3V
R123
R118
R119
C113
R122
J103
J105
R137
C122
R141
R130
C116
R136
J109
C117
J114
J107
R140
C123
J112
R126
R127
R145
R131
C126
R149
J118
J111
R138
C120
C127
J116
J113
R144
C121
R148
R134
R135
R139
J115
R146
C124
J117
C125
R142
R143
R147
R124
C114
J106
C115
J104
R120
R121
R125
C118
C119
J108
R132
J110
R128
R129
R133
C112
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CONFIG MODECONTROL
DIP SWITCHES
Note: It is preferrableto ensure switchesare OFF followingconfiguration if M[3:0]are to be usedas GPio.
GENERAL PURPOSE HEADER CONNECTED TO 16
2.0
LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD
C
7 8Thursday, March 28, 2002
Title
Size Document Number Rev
Date: Sheet of
M2M1M0
M3
+3.3V+3.3V
RN
3D47
K4
5
RN
5C47
K3
6
RN
9C47
K3
6
RN
2C47
K3
6
J121
111-0102-001Red Banana Jack
1
RN
8A47
K1
8
RN
10A
47K
18
J122
111-0102-001Red Banana Jack
1
RN
5D47
K4
5
RN
2A47
K1
8
23
1
J120123
123 R
N11
B47
K2
7
RN
3C47
K3
6
RN
11C
47K
36
RN
9D47
K4
5
RN
11D
47K
45
RN
10B
47K
27
RN
9B47
K2
7R
N3B
47K
27
RN
7C47
K3
6
RN
7A47
K1
8
10
SW7D
7
5
6
10
SW7C
9
8
4
10
SW7B
10
2
3
RN
11A
47K
18
RN
8D47
K4
5
RN
8B47
K2
7
RN
4A47
K1
8
RN
5B47
K2
7
RN
10C
47K
36
RN
1A47
K1
8
RN
1B47
K2
7
RN
1D47
K4
5
RN
8C47
K3
6
RN
2D47
K4
5
J29
TSW-108-07-T-D2x8 0.100" Header
12345678910111213141516
123456789
10111213141516
10
SW1A
12
11
1
RN
7B47
K2
7
RN
10D
47K
45
10
SW1C
9
8
4
10
SW1B
10
2
3
10
SW1D
7
5
6
RN
9A47
K1
8
RN
4B47
K2
7
RN
2B47
K2
7
RN
4D47
K4
5
23
1
J119123
123
RN
3A47
K1
8
RN
7D47
K4
5
RN
4C47
K3
6
RN
1C47
K3
6
10
SW7A
12
11
1
RN
5A47
K1
8
10
SW6C
9
8
4
10
SW6B
10
2
3
10
SW6A
12
11
1
10
SW6D
7
5
6
10
SW3C
9
8
4
10
SW3B
10
2
3
10
SW3A
12
11
1
10
SW3D
7
5
6
10
SW2C
9
8
4
10
SW2B
10
2
3
10
SW2A
12
11
1
10
SW2D
7
5
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Note: Jumper selectsDATA0 between 7 pinserial connector (page2) and 860 bus.
MPI_TSZ1MPI_TSZ0MPI_RWMPI_BURST_NMPI_BDIP_N
MPI_STRB_NMPI_ACK_NMPI_TEA_N
MPI_CLK
DP0DP1DP2DP3
MPI_RTRY_N
MPI_IRQ_N
2.0
LATTICE SEMICONDUCTOR CORP. OR4E FPGA EVALUATION BOARD
C
8 8Thursday, March 28, 2002
Title
Size Document Number Rev
Date: Sheet of
CONN_A19CONN_A20CONN_A21CONN_A22CONN_A23CONN_A24CONN_A25CONN_A26CONN_A27CONN_A28CONN_A29CONN_A30CONN_A31CONN_A32
CONN_A28
ADDR16ADDR15
CONN_A26CONN_A25
ADDR10ADDR11
CONN_A31
CONN_A19
CONN_A21
CONN_A30
ADDR5
CONN_A32
CONN_A23CONN_A24
ADDR9
ADDR6CONN_A27
ADDR13ADDR12
ADDR14
ADDR3ADDR2
ADDR0
CONN_A29
ADDR8
ADDR4
CONN_A20
ADDR17
CONN_A22
ADDR7
ADDR1
DATA0DATA1DATA2DATA3DATA4DATA5DATA6DATA7DATA8DATA9DATA10DATA11DATA12DATA13DATA14DATA15 DATA16
DATA17DATA18DATA19DATA20DATA21DATA22DATA23DATA24DATA25DATA26DATA27DATA28DATA29DATA30DATA31
ADDR21
ADDR19
GP7_31ADDR20
GP0_18
GP7_23
GP0_21
ADDR18
GP7_32GP6_26
GP0_17
GP7_16GP0_16
GP6_14
GP0_18
ADDR14ADDR13
ADDR20
GP7_23
GP0_21
GP7_16
GP0_16
GP6_26
ADDR10
GP0_18GP7_31
ADDR19
GP7_32
GP6_14
GP0_21
ADDR20
GP7_23
ADDR15
ADDR0
ADDR16
GP6_26
ADDR21
ADDR11
ADDR7
ADDR9
GP0_16
ADDR5
ADDR12
GP7_32
GP7_16ADDR8
ADDR3ADDR4
GP0_17
GP6_14
ADDR19
ADDR21
ADDR1
GP0_17
ADDR18
GP7_31
ADDR2
ADDR17
ADDR6
ADDR18
DATA14
DATA16
DATA7
DATA20
DATA1
DATA28
DATA5
DATA10
DATA15
DATA18
DATA22
DATA17
DATA11
DATA23
DATA29
DATA6
DATA3
DATA26
DATA4
DATA13
DATA9
DATA0_B
DATA21
DATA2
DATA31DATA30
DATA25DATA24
DATA27
DATA12
DATA19
DATA8
DATA0DATA0_BDATA[31:0]
ADDR[21:0]
ADDR[21:0]
GP0_[26:0]
GP7_[32:0]
GP6_[36:0]
CFG_IRQ_N
CFG_IRQ_N
DATA0_A
+3.3V
+3.3V +3.3V
23
1
J36123
123
J21
TSW-116-07-T -D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
R22
04.
7K
R16
34.
7K
R21
34.
7K
R21
74.
7K
R21
54.
7K
R16
44.
7K
R21
84.
7K
R16
74.
7K
650908
J11131234567891011121314151617181920212223242526272829303132
3334353637383940414243444546474849505152535455565758596061626364
6566676869707172737475767778798081828384858687888990919293949596
A1A2A3A4A5A6A7A8A9
A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32
B1B2B3B4B5B6B7B8B9
B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32
C1C2C3C4C5C6C7C8C9
C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32
R21
44.
7K
R16
64.
7KR
165
4.7K
650908
J11151234567891011121314151617181920212223242526272829303132
3334353637383940414243444546474849505152535455565758596061626364
6566676869707172737475767778798081828384858687888990919293949596
A1A2A3A4A5A6A7A8A9
A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32
B1B2B3B4B5B6B7B8B9
B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32
C1C2C3C4C5C6C7C8C9
C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32
R16
84.
7KR
169
4.7K
R17
14.
7K
R21
64.
7K
R17
04.
7K
R21
94.
7K
R17
34.
7KR
172
4.7K
R17
64.
7KR
175
4.7K
R17
44.
7K
R17
84.
7KR
177
4.7K
R18
04.
7KR
179
4.7K
R22
14.
7K
R21
24.
7K
R18
14.
7K
J17
TSW-116-07-T -D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
J16
TSW-116-07-T -D2x16 0.100" Header
123456789
10111213141516 17
1819202122232425262728293031321
2345678910111213141516 17
181920212223242526272829303132
650908
J11141234567891011121314151617181920212223242526272829303132
3334353637383940414243444546474849505152535455565758596061626364
6566676869707172737475767778798081828384858687888990919293949596
A1A2A3A4A5A6A7A8A9
A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25A26A27A28A29A30A31A32
B1B2B3B4B5B6B7B8B9
B10B11B12B13B14B15B16B17B18B19B20B21B22B23B24B25B26B27B28B29B30B31B32
C1C2C3C4C5C6C7C8C9
C10C11C12C13C14C15C16C17C18C19C20C21C22C23C24C25C26C27C28C29C30C31C32
R18
24.
7K
R18
44.
7KR
183
4.7K
R18
54.
7K
R18
74.
7K
R22
24.
7K
R18
64.
7K
R19
04.
7K
R22
34.
7K
R18
94.
7KR
188
4.7K
R22
74.
7K
R19
24.
7K
R22
64.
7KR
225
4.7K
R19
14.
7K
R22
44.
7K
R19
54.
7KR
194
4.7K
R19
34.
7K
R19
84.
7KR
197
4.7K
R19
64.
7K
R20
04.
7KR
199
4.7K
R20
24.
7KR
201
4.7K
R20
34.
7K
R20
64.
7KR
205
4.7K
R20
44.
7K
R20
84.
7KR
207
4.7K
R21
14.
7KR
210
4.7K
R20
94.
7K