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6.012 Spring 2007 Lecture 11 1
Lecture 11Digital Circuits (I)THE INVERTER
Outline Introduction to digital circuits
The inverter
NMOS inverter with resistor pull-up
Reading Assignment:Howe and Sodini; Chapter 5, Sections 5.1-5.3
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6.012 Spring 2007 Lecture 11 2
1. Introduction to digital circuits: the inverter
Logic 0: VMIN V VOL
Logic 1: VOH V VMAX
Undefined logic value: VOL
V VOH
In digital circuits, digitally-encoded information isrepresented by means of two distinct voltage ranges:
Logic operations are performed using logic gates.
Simplest logic operation of all: inversion inverter
V
logic 1
logic 0
undefinedregionVOL
VMAX
VMIN
VOH
The Static Definition
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6.012 Spring 2007 Lecture 11 3
Ideal inverter
VM input voltage for which VOUT = VIN For 0 VIN < VM VOUT = V
+
For VM < VIN V+ VOUT = 0
Defineswitching point or logic threshold:
Circuit representation and ideal transfer function:
Ideal inverter returns well defined logical outputs (0 or
V+) even in the presence of considerable noise in VIN(from voltage spikes, crosstalk, etc.)
signal isregenerated!
v+
+ +
- -
VIN VOUT
VOUT
VINV+
V+
V+2
VOUT=VIN
V+
2VM=
0
0
IN OUT=IN
IN OUT
0 1
1 0
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6.012 Spring 2007 Lecture 11 4
Real inverter
Logic 0:
VMIN output voltage for which VIN = V+
VOL smallest output voltage where slope = -1
Logic 1:
VOH largest output voltage where slope = -1 VMAX output voltage for which VIN = 0
In a real inverter, valid logic levels defined as follows:
VOUT
VINV+0
0
slope=-1VOH
VOLVMIN
VMAXlogic 1
logic 0
transitionregion
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6.012 Spring 2007 Lecture 11 5
Two other important voltages:
Define:
VIL smallest input voltage where slope = -1VIH highest input voltage where slope = -1
If range of output values VOL to VOH is wider than therange of input values VIL to VIH, then the inverter
exhibits some noise immunity. (|Voltage gain| > 1)
Quantify this throughnoise margins.
VOUT
VINV+
00
slope=-1
VOH
VIL VIH
VOL
VMIN
VMAXlogic 1
logic 0
undefinedregion
ran
geof
inputv
alues
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ucev
alidl
ogic
0
range
ofinputv
alues
thatpro
duce
valid
logic
1
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6.012 Spring 2007 Lecture 11 6
Chain of two inverters:
Definenoise margins:
NMH VOH - VIH noise margin highNML VIL - VOL noise margin low
noise
M N
inverter Moutput
inverter Ninput
VOH
VOUT VIN
NMH
NMLVOL
VIH
VIL
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6.012 Spring 2007 Lecture 11 7
Simplifications for hand calculations:Logic levels and noise margins
Assume VOL VMIN and VOH VMAX
Trace tangent of transfer function at VM Slope = small signal voltage gain (Av) at VM
VIL intersection of tangent with VOUT = VMAX VIH intersection of tangent with VOUT = VMIN
It is hard to compute points in transfer function with
slope = -1.
Approximate in the following way:
VOUT
VIHVIL VM
VM
VINV+
00
VOL=VMIN
VOH=VMAX
VOUT=VIN
slope= Av
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6.012 Spring 2007 Lecture 11 8
Transient Characteristics
Inverter switching in the time domain:
tR rise timebetween 10% and 90% of total swingtF fall timebetween 90% and 10% of total swingtPHL propagation delay from high-to-low between
50% points
tPLH propagation delay from low-to-high between50% points
Propagation delay : tP =1
2tPHL + tPLH( )
VOL
90%
50%
10%
tPHL
tPLH
VOH
tR
tCYCLE
50%
90%
10%
0 t
VIN
VOUT
0 t
tR
tF
VOH
VOL
tF
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6.012 Spring 2007 Lecture 11 9
Simplifications for hand calculations:Propagation delay
Consider input waveform is an ideal square wave
Propagation delay times = delay times to 50% point
SPICE essential for accurate delay analysis
VOH
VOH
VOL
VIN
VOUT
tPHL
tPLH
VOH
VOL
50%
t
t
tCYCLE
tCYCLE
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6.012 Spring 2007 Lecture 11 10
2. NMOS inverter with pull-up resistor
VBS = 0 (typically not shown)
CL summarizes capacitive loading of the following
stages (other logic gates, interconnect lines, etc.)
If VIN
< VT
, MOSFET is OFF
VOUT = VDD If VIN > VT, MOSFET is ON
VOUT small Value set by resistor / nMOS divider
Basic Operation:
Essential features:
VIN
VOUT
V+=VDD
IR
IDCL
R
load capacitance(from followingstages)
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6.012 Spring 2007 Lecture 11 11
Transfer function obtained by solving:
IR= ID
Can solve graphically: IV characteristics of load:
VIN
VR
VOUT
VDD
IR
ID
R
+
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6.012 Spring 2007 Lecture 11 12
Overlap IV characteristics of resistor pull-up on IV
characteristics of transistor:
Transfer function:
VDS
VGS=VDD
VGS=VIN
VGS=VT
00
IR=ID
VDD
VDD
R
load line
VOUT=VDS
VIN=VGS0
0 VDDVT
VDD
=VOUT
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6.012 Spring 2007 Lecture 11 13
For VMAX, transistor is cut-off, ID = 0:
VMAX = VDD
For VMIN, transistor is in linear regime; solve:
I D =W
LnCox VDD
VMIN
2 VT
VMIN = IR =
VDD VMINR
I D =W
2LnCox VM VT( )
2= I R=
VDD VMR
For VM, transistor is in saturation; solve:
Logic levels:
VOUT=VDS
VOUT=VIN
VIN=VGS0
0 VDDVT VM
VM
VMAX=VDD
VMIN
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6.012 Spring 2007 Lecture 11 14
Small signal equivalent circuit model at VM(transistor in saturation):
Av =vout
vin= gm ro //R( ) gmR
Noise Margins:VOUT=VDS
VOUT=VIN
VIN=VGS0
0 VDDVT
VMAX=VDD
VMIN
Av
G
S
D+
-
vin
+
-
vgs
+
-
voutgmvgs ro
R
+
-
vin
+
-
voutgmvin (ro//R)
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