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Transactional Memory – Implementation
Lecture 1
COS597C, Fall 2010Princeton University
Arun Raman
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Module Outline
Lecture 1 (THIS LECTURE)Transactional Memory System TaxonomySoftware Transactional Memory Hardware Accelerated STMs
Lecture 2 (Thursday)Hardware based TMsHybrid TMsWhen are transactions a good (bad) idea
AssignmentCompare lock-based and transaction-based implementations of a concurrent data structure 2
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[0] TL2 and STAMP Benchmark Suite --- For ASSIGNMENThttp://stamp.stanford.edu/
[1] Transactional Memory, Concepts, Implementations, and Opportunities -Christos Kozyrakishttp://csl.stanford.edu/~christos/publications/2008.tm_tutorial.acaces.pdf
[2] Transactional Memory - Larus and RajwarChapter 4: Hardware Transactional Memory
[3] McRT-STM: A High Performance Software Transactional Memory System for a Multi-core Runtimehttp://portal.acm.org/ft_gateway.cfm?id=1123001&type=pdf&CFID=109418483&CFTOKEN=70706278
[4] Architectural Support for Software Transactional Memory (Hardware Accelerated STM) - Saha et al.http://www.computer.org/portal/web/csdl/doi/10.1109/MICRO.2006.9
[5] Signature-Accelerated STM (SigTM)http://portal.acm.org/citation.cfm?id=1250673
[6] Case Study: Early Experience with a Commercial HardwareTransactional Memory Implementation [ASPLOS '09]http://delivery.acm.org/10.1145/1510000/1508263/p157-dice.pdf?key1=1508263&key2=2655478821&coll=GUIDE&dl=GUIDE&CFID=111387689&CFTOKEN=28498606
[7] The Transactional Memory / Garbage Collection Analogy - Dan Grossmanhttp://portal.acm.org/ft_gateway.cfm?id=1297080&type=pdf&coll=GUIDE&dl=GUIDE&CFID=111387606&CFTOKEN=67012128
[8] Subtleties of Transactional Memory Atomicity Semantics - Blundell et al.http://www.cis.upenn.edu/acg/papers/cal06_atomic_semantics.pdf
Resources
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Lot of the material in this lecture is sourced from here
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Lecture Outline
1.Recap of Transactions2.Transactional Memory System Taxonomy3.Software Transactional Memory4.Hardware Accelerated STM
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Lecture Outline
1.Recap of Transactions2.Transactional Memory System Taxonomy3.Software Transactional Memory 4.Hardware Accelerated STMs
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Parallel Programming
1.Find independent tasks in the algorithm2.Map tasks to execution units (e.g. threads)3.Define and implement synchronization among tasks
● Avoid races and deadlocks, address memory model issues, …
4.Compose parallel tasks5.Recover from errors6.Ensure scalability7.Manage locality8.…
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Parallel Programming
1.Find independent tasks in the algorithm2.Map tasks to execution units (e.g. threads)3.Define and implement synchronization among tasks
● Avoid races and deadlocks, address memory model issues, …
4.Compose parallel tasks5.Recover from errors6.Ensure scalability7.Manage locality8.…
Transactional Memory
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Transactional Programming
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void deposit(account, amount) { lock(account); int t = bank.get(account); t = t + amount; bank.put(account, t); unlock(account);}
void deposit(account, amount) { atomic { int t = bank.get(account); t = t + amount; bank.put(account, t); }}
1.Declarative Synchronization – What, not How2.System implements Synchronization transparently
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Transactional Memory
Memory Transaction - An atomic and isolated sequence of memory accesses
Transactional Memory – Provides transactions for threads running in a shared address space
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Transactional Memory - Atomicity
Atomicity – On transaction commit, all memory updates appear to take effect at once; on transaction abort, none of the memory updates appear to take effect
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void deposit(account, amount) { atomic { int t = bank.get(account); t = t + amount; bank.put(account, t); }}
Thread 1 Thread 2
RD A : 0RD
WRRD A : 0
WR A : 10
WR A : 5COMMIT
ABORT
CONFLICT
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Transactional Memory - Isolation
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Isolation – No other code can observe updates before commit
Programmer only needs to identify operation sequence that should appear to execute atomically to other, concurrent threads
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Transactional Memory - Serializability
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Serializability – Result of executing concurrent transactions on a data structure must be identical to a result in which these transactions executed serially.
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Some advantages of TM
1.Ease of use (declarative)2.Composability3.Expected performance of fine-grained locking
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Composability : Locks
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void transfer(A, B, amount) { synchronized(A) { synchronized(B) { withdraw(A, amount); deposit(B, amount); } }}
void transfer(B, A, amount) { synchronized(B) { synchronized(A) { withdraw(B, amount); deposit(A, amount); } }}
1.Fine grained locking Can lead to deadlock2.Need some global locking discipline now
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Composability : Locks
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void transfer(A, B, amount) { synchronized(bank) { withdraw(A, amount); deposit(B, amount); }}
void transfer(B, A, amount) { synchronized(bank) { withdraw(B, amount); deposit(A, amount); }}
1.Fine grained locking Can lead to deadlock2.Coarse grained locking No concurrency
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Composability : Transactions
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void transfer(A, B, amount) { atomic { withdraw(A, amount); deposit(B, amount); }}
void transfer(B, A, amount) { atomic { withdraw(B, amount); deposit(A, amount); }}
1.Serialization for transfer(A,B,100) and transfer(B,A,100)2.Concurrency for transfer(A,B,100) and transfer(C,D,100)
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Some issues with TM
1.I/O and unrecoverable actions2.Atomicity violations are still possible3.Interaction with non-transactional code
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Atomicity Violation
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atomic { … ptr = A; …}
atomic { … ptr = NULL;}
Thread 2Thread 1
atomic { B = ptr->field;}
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Interaction with non-transactional code
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lock_acquire(lock); obj.x = 1; if (obj.x != 1) fireMissiles();lock_release(lock);
obj.x = 2;
Thread 2Thread 1
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Interaction with non-transactional code
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atomic { obj.x = 1; if (obj.x != 1) fireMissiles();}
obj.x = 2;
Thread 2Thread 1
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Interaction with non-transactional code
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atomic { obj.x = 1; if (obj.x != 1) fireMissiles();}
obj.x = 2;
Thread 2Thread 1
Weak Isolation – Transactions are serializable only against other transactionsStrong Isolation – Transactions are serializable against all memory accesses (Non-transactional LD/ST are 1-instruction TXs)
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Nested Transactions
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void transfer(A, B, amount) { atomic { withdraw(A, amount); deposit(B, amount); }}
void deposit(account, amount) { atomic { int t = bank.get(account); t = t + amount; bank.put(account, t); }}
Semantics of Nested Transactions• Flattened• Closed Nested • Open Nested
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Nested Transactions - Flattened
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int x = 1;atomic { x = 2; atomic flatten { x = 3; abort; }}
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Nested Transactions - Closed
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int x = 1;atomic { x = 2; atomic closed { x = 3; abort; }}
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Nested Transactions - Open
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int x = 1;atomic { x = 2; atomic open { x = 3; } abort;}
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Nested Transactions – Open – Use Case
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int counter = 1;atomic { … atomic open { counter++; }}
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Nested Transactions ≠ Nested Parallelism!
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Intelligent Speculation for Pipelined Multithreading – Neil Vachharajani, PhD Thesis, Princeton University
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Transactional Programming - Summary
1. Transactions do not generate parallelism2. Transactions target performance of fine-grained locking @ effort of coarse-grained locking
5. Various constructs studied previously (atomic, retry, orelse,…) 4. Different semantics (Weak/Strong Isolation, Nesting)
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Lecture Outline
1.Recap of Transactions2.Transactional Memory System Taxonomy3.Software Transactional Memory4.Hardware Accelerated STMs
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TM Implementation
Data Versioning• Eager Versioning• Lazy Versioning
Conflict Detection and Resolution• Pessimistic Concurrency Control• Optimistic Concurrency Control
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Conflict Detection Granularity• Object Granularity• Word Granularity• Cache line Granularity
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TM Implementation
Data Versioning• Eager Versioning• Lazy Versioning
Conflict Detection and Resolution• Pessimistic Concurrency Control• Optimistic Concurrency Control
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Conflict Detection Granularity• Object Granularity• Word Granularity• Cache line Granularity
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Data Versioning
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Eager Versioning (Direct Update)Lazy Versioning (Deferred Update)
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TM Implementation
Data Versioning• Eager Versioning• Lazy Versioning
Conflict Detection and Resolution• Pessimistic Concurrency Control• Optimistic Concurrency Control
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Conflict Detection Granularity• Object Granularity• Word Granularity• Cache line Granularity
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Conflict Detection and Resolution - Pessimistic
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Tim
eNo
ConflictConflict with
StallConflict with Abort
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Conflict Detection and Resolution - Optimistic
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Tim
eNo
ConflictConflict with
AbortConflict with Commit
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TM Implementation
Data Versioning• Eager Versioning• Lazy Versioning
Conflict Detection and Resolution• Pessimistic Concurrency Control• Optimistic Concurrency Control
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Conflict Detection Granularity• Object Granularity• Word Granularity• Cache line Granularity
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Examples
Hardware TM • Stanford TCC: Lazy + Optimistic• Intel VTM: Lazy + Pessimistic• Wisconsin LogTM: Eager + Pessimistic• UHTM• SpHT
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Software TM • Sun TL2: Lazy + Optimistic (R/W)• Intel STM: Eager + Optimistic (R)/Pessimistic (W)• MS OSTM: Lazy + Optimistic (R)/Pessimistic (W)• Draco STM• STMLite• DSTM
Can find many more at http://www.dolcera.com/wiki/index.php?title=Transactional_memory
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Lecture Outline
1.Recap of Transactions2.Transactional Memory System Taxonomy3.Software Transactional Memory (Intel McRT-STM)4.Hardware Accelerated STMs
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Software Transactional Memory (STM)
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atomic { a.x = t1 a.y = t2 if (a.z == 0) { a.x = 0 a.z = t3 }}
tmTXBegin()tmWr(&a.x, t1)tmWr(&a.y, t2)if (tmRd(&a.z) != 0) { tmWr(&a.x, 0) tmWr(&a.z, t3)}tmTXCommit()
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Intel McRT-STM
Strong or Weak Isolation Weak
Transaction Granularity Word or Object
Lazy or Eager Versioning Eager
Concurrency Control Optimistic read, Pessimistic Write
Nested Transaction Closed
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McRT-STM Runtime Data Structures
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Transaction Descriptor (per thread)• Used for conflict detection, commit, abort, …• Includes read set, write set, undo log or write bufferTransaction Record (per datum)• Pointer-sized record guarding shared datum• Tracks transactional state of datum
Shared: Read-only access by multiple readersValue is odd (low bit is 1)
Exclusive: Write-only access by single ownerValue is aligned pointer to owning transaction’s descriptor
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atomic { t = foo.x; bar.x = t; t = foo.y; bar.y = t; }
T1
atomic { t1 = bar.x; t2 = bar.y; }
T2
• T1 copies foo into bar• T2 reads bar, but should not see intermediate values
Class Foo { int x; int y;};Foo bar, foo;
McRT-STM: Example
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stmStart(); t = stmRd(foo.x); stmWr(bar.x,t); t = stmRd(foo.y); stmWr(bar.y,t); stmCommit();
T1
stmStart(); t1 = stmRd(bar.x); t2 = stmRd(bar.y); stmCommit();
T2
• T1 copies foo into bar• T2 reads bar, but should not see intermediate values
McRT-STM: Example
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McRT-STM Operations
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STM read (Optimistic)• Direct read of memory location (eager versioning)• Validate read data
● Check if unlocked and data version <= local timestamp
● If not, validate all data in read set for consistency validate() {for <txnrec,ver> in transaction’s read set, if (*txnrec != ver) abort();}
• Insert in read set• Return valueSTM write (Pessimistic)• Validate data
● Check if unlocked and data version <= local timestamp
• Acquire lock• Insert in write set• Create undo log entry• Write data in place (eager versioning)
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stmStart(); t = stmRd(foo.x); stmWr(bar.x,t); t = stmRd(foo.y); stmWr(bar.y,t); stmCommit;
T1
stmStart(); t1 = stmRd(bar.x); t2 = stmRd(bar.y); stmCommit();
T2
hdr
x = 0
y = 0
5
hdr
x = 9
y = 7
3foo bar
Reads <foo, 3> Reads <bar, 5>
T1
x = 9
<foo, 3>Writes <bar, 5>Undo <bar.x, 0>
T2 waits
y = 7
<bar.y, 0>
7
<bar, 7>
Abort
•T2 should read [0, 0] or should read [9,7]
Commit
McRT-STM: Example
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Lecture Outline
1.Recap of Transactions2.Transactional Memory System Taxonomy3.Software Transactional Memory (Intel McRT-STM)4.Hardware Accelerated STMs (HASTM)
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Hardware Support?
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Types of Hardware Support
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Hardware-accelerated STM systems (HASTM, SigTM, …)Hardware-based TM systems (TCC, LTM, VTM, LogTM, …)Hybrid TM systems (Sun Rock)
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Hardware Support?
1.1.8x – 5.6x slowdown over sequential2.Most time goes in read barriers and validation
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Hardware Support?
Architectural Support for Software Transactional Memory – Saha et al.
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Hardware-accelerated STM (HASTM)
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ISA Extensions• loadSetMark(addr) – Loads value at addr and sets mark bit associated with addr• loadResetMark(addr) – Loads value at addr and clears mark bit associated with addr• loadTestMark(addr) – Loads the value at addr and sets carry flag to value of mark bit• resetMarkAll() – Clears all mark bits in cache and increments mark counter• resetMarkCounter() – Resets mark counter• readMarkCounter() – Reads mark counter value
Hardware Support• Per-thread mark bits at granularity of cache lines• New register (mark counter)• Used to build fast filters to speed up read barriers
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HASTM – Cache line transitions
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McRT-STM Operations
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stmRd = stmRdBar + RdstmRdBar(TxnRec* rec) { void* recval = *rec; void* txndesc = getTxnDesc(); if (recval == txndesc) return; if (isVersion(recVal) == false) recval = handleContention(rec); logRead(rec,recval);}
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McRT-STM Operations
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stmWr = stmWrBar + LogOldValue + WrstmWrBar(TxnRec* rec) { void* recval = *rec; void* txndesc = getTxnDesc(); i f (recval == txndesc) return; if (isVersion(recVal) == false) recval = handleContention(rec); while (CAS(rec,recval,txndesc) == false) recval = handleContention(rec); logWrite(rec,recval);}
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McRT-STM Operations
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mov eax, [rec] /* load TxRec */cmp eax, txndesc /* do I own exclusive */jeq done
test eax, #versionmask /* is a version no. */jz contention
mov ecx, [txndesc + rdsetlog] /*get log ptr*/test ecx, #overflowmaskjz overflow
add ecx, 8 /*inc log ptr*/mov [txndesc + rdsetlog], ecxmov [ecx – 8], rec /* logging */mov [ecx – 4], eax /* logging */
done:…
stmRd = stmRdBar + Rd
Manage Contentio
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Manage Overflow
Fast Path
Slow Path
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HASTM Operations
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loadTestMark eax, [rec] /* check 1st access */jnae done
test eax, #versionmask /* is a version no. */jz contention mov ecx, [txndesc + rdsetlog] /*get log ptr*/test ecx, #overflowmaskjz overflow
add ecx, 8 /*inc log ptr*/mov [txndesc + rdsetlog], ecxmov [ecx – 8], rec /* logging */mov [ecx – 4], eax /* logging */
done:…
stmRd = stmRdBar + Rd
Manage Contentio
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Manage Overflow
Fast Path
Slow Path
loadSetMark eax, [rec]
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HASTM Operations
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validatevalidate() { markCount = readMarkCounter(); resetMarkAll(); if (markCount == 0) /*no snoop or eviction*/ return; /* perform full read set validation */ for <txnrec,ver> in transaction’s read set if (*txnrec != ver) abort();}
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HASTM Performance Improvement
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HASTM Performance Improvement – Multicore
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Binary Search Tree B-Tree
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HASTM - Issues
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Insufficient Cache Capacity• Mark bits are only an acceleration mechanism• Cache evictions, cause mark bits to be lost – revert to slow software validation
Weak Isolation
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Other Slides
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Intel McRT-STM
Lazy/Eager Eager
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Other Transactional Programming Primitives1.User-triggered abort: abort
void transfer(A,B,amount) atomic{ try{ work(); } catch(error1) {fix_code();} catch(error2) {abort;} }
2.Conditional synchronization: retryObject blockingDequeue(q) atomic{ if(q.isEmpty()) retry;
return dequeue(); }
3.Composing code sequences: orelseatomic{q1.blockingDequeue();}orelse{q2.blockingDequeue();}
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