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NBTI in GaN MOSFETs: SiO2 vs. SiO2/Al2O3 gate dielectric
Alex Guo and Jesús A. del Alamo Microsystems Technology Laboratories (MTL)Massachusetts Institute of Technology (MIT)
Cambridge, MA, USA
Sponsor: MIT/MTL Gallium Nitride (GaN) Energy InitiativeUnited States National Defense Science & Engineering Graduate Fellowship (NDSEG)
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Outline
Motivation
Experimental setup
Results and discussion
Conclusions
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Outline
Motivation
Experimental setup
Results and discussion
Conclusions
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GaN for power electronics
Promising for a wide range of applications
Negative-Bias Temperature Instability (NBTI) is a major concern:– Operational instability– Long-term reliability
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30 V 600 V > 1200 V
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MIS-HEMT: Metal-Insulator-Semiconductor High Electron Mobility Transistor
Low gate leakage, large gate swingx Gate oxide brings stability and reliability concerns not present in HEMTs
GaN MIS-HEMT for high voltage applications
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[Lagger, TED 2014]
GaNBuffer
Substrate
Oxide
AlGaN
SG
D
GaN cap
Passivation Passivation
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This work: simpler GaN MOSFET structure
Industrial prototype devices
Isolate oxide and oxide/GaN interface SiO2 vs. SiO2/Al2O3 composite, EOT ~ 40 nm
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GaNBuffer
Si substrateMetal contact
OxideAlGaN
Field plate
SG
OxideD
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Three regimes: (Regime 1) Small negative ∆VT (regime 2) positive ∆VT (regime 3) negative ∆VT
Permanent negative ∆VT after TD
NBTI of GaN MOSFETs
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*TD: Thermal Detrapping
After TD
GaN MOSFET(SiO2/Al2O3 dielectric)
[Guo, IRPS 2016]
①
② ③
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NBTI of GaN MOSFETs
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Si HKMG p-MOSFET
[Zafar, TDMR 2005]
tHfO2 = 2.5 nm
*TD: Thermal Detrapping
After TD
GaN MOSFET(SiO2/Al2O3 dielectric)
[Guo, IRPS 2016]
①
② ③
Differences from NBTI of Si HKMG p-MOSFET: Larger |∆VT| Peculiar positive VT shift in regime 2
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NBTI of GaN MOSFETs
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Si HKMG p-MOSFET
[Zafar, TDMR 2005]
tHfO2 = 2.5 nm
Goal of this work: NBTI in SiO2 vs. SiO2/Al2O3 GaN MOSFETs
*TD: Thermal Detrapping
After TD
GaN MOSFET(SiO2/Al2O3 dielectric)
[Guo, IRPS 2016]
①
② ③
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Outline
Motivation
Experimental setup
Results and discussion
Conclusions
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Experimental flow and FOM definition
VT: VGS value when ID = 1 µA/mm S: Extracted at ID = 0.1 µA/mm gm,max: Extracted from ID-VGS ramp All at VDS = 0.1 V First sample: ~ 1- 2 s after removal of stress
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Device screening and initialization
Recovery and characterization
Stress and characterization
Thermal detrapping
I/V sweep
Increase stress voltage or T
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Outline
Motivation
Experimental setup
Results and discussion
Conclusions
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VGS,stress = -2 V (low-stress)
SiO2: No visible negative ΔVT; Positive ΔVT and ΔS for longer tstress; no regime 1 observedSiO2/Al2O3: Negative ΔVT, negligible ΔS regime 1
Both devices completely recovered after TD Lower level of oxide trapping/detrapping in SiO2 vs. SiO2/Al2O3
Stress time (tstress) evolution of ΔVT at RT
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*TD: Thermal detrapping
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VGS,stress = -10, -20, -30 V (mid-stress)
Positive ΔVT, both increase with tstress and VGS,stress regime 2 SiO2/Al2O3 device completely recovers after TD regime 2 only SiO2 device shows negative, permanent ΔVT that increases with VGS,stress regime 2 + 3
Stress time (tstress) evolution of ΔVT at RT
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Stress time (tstress) evolution of ΔS at RT
VGS,stress = -10, -20, -30 V (mid-stress)
Positive ΔS increases with tstress and VGS,stress regime 2 SiO2/Al2O3 device completely recovers after TD regime 2 only SiO2 device shows non-recoverable ΔS that increases with VGS,stress regime 2 + 3
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ΔVT and ΔS correlation after 1000 s stress
Correlation of ΔVT and ΔS
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Recoverable ΔVT vs. recoverable ΔS Permanent ΔVT vs. permanent ΔS
RT
Regime 2: Recoverable ΔVT vs. recoverable ΔS linearly
correlate Suggests same mechanisms
Regime 3: Permanent ΔVT and permeant ΔS linearly
correlate Suggests same mechanisms
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ΔVT mechanism (regime 1)
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Electron detrapping Electron retrappingInitial
GaN channel
Oxide
EF--------Metal
GaN channel
Oxide
EF--------Metal
GaN channel
Oxide
EF--------Metal
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More prominent electron detrapping in SiO2/Al2O3 devices than in SiO2 devices
Border traps in Al2O3, well studied in Si HK system [Jakschik, TED 2004]
Consistent with PBTI study [Guo, IRPS 2015]
ΔVT mechanism (regime 1)
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Electron detrapping Electron retrappingInitial
GaN channel
Oxide
EF--------Metal
GaN channel
Oxide
EF--------Metal
GaN channel
Oxide
EF--------Metal
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ΔVT mechanism (regime 2)
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[Jin, IEDM 2013]
x
y
[Guo, IRPS 2016]
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ΔVT and ΔS evolution in regime 2 independent of dielectric consistent with trapping in GaN substrate - more substrate traps in SiO2 device perhaps due to higher deposition temperature.
ΔVT mechanism (regime 2)
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[Jin, IEDM 2013]
x
y
[Guo, IRPS 2016]
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Interface state generation under high gate stress, well-studied mechanism in Si MOS system [Schroder, JAP 2007].
ΔVT mechanism (regime 3)
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GaN channelOxide
EF
Metal
---XX
Interface stategeneration
Oxide
Under stress After TD
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Interface state generation under high gate stress, well-studied mechanism in Si MOS system [Schroder, JAP 2007].
More severe in SiO2/GaN interface, consistent with PBTI study [Guo, IRPS 2015]
ΔVT mechanism (regime 3)
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GaN channelOxide
EF
Metal
---XX
Interface stategeneration
Oxide
Under stress After TD
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Outline
Motivation
Experimental setup
Results and discussion
Conclusions
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![Page 24: NBTI in GaN MOSFETs: SiO2 vs. SiO2/Al2O3 gate dielectric slides.pdf · Interface state generation under high gate stress, well -studied mechanism in Si MOS system [Schroder, JAP 2007](https://reader030.vdocuments.us/reader030/viewer/2022040113/5f1260c5a11ad7697d704e26/html5/thumbnails/24.jpg)
Conclusions
Understanding of NBTI in SiO2 vs. SiO2/Al2O3 GaN MOSFETs– Regime 1 (low-stress):
» Electron detrapping from pre-existing oxide traps
» More prominent in SiO2/Al2O3 due to higher concentration of border traps
– Regime 2 (mid-stress):
» Trapping in GaN substrate
» Greater magnitude in SiO2 devices, possibly due to defects created during SiO2deposition
– Regime 3 (high-stress):
» Interface state generation at oxide/GaN interface
» SiO2 devices exhibit more fragile interface with GaN (more interface state generation)
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