Download - Multicycle Approach
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• Break up the instructions into steps– each step takes one clock cycle– balance the amount of work to be done in each step/cycle so that they are
about equal– restrict each cycle to use at most once each major functional unit so that
such units do not have to be replicated– functional units can be shared between different cycles within one
instruction
• Between steps/cycles– At the end of one cycle store data to be used in later cycles of the same
instruction• need to introduce additional internal (programmer-invisible) registers for this
purpose
– Data to be used in later instructions are stored in programmer-visible state elements: the register file, PC, memory
Multicycle Approach
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• Note particularities of multicyle vs. single- diagrams
– single memory for data and instructions– single ALU, no extra adders– extra registers to hold data between clock cycles
Multicycle Approach
PC
Instructionmemory
Readaddress
Instruction
16 32
Add ALUresult
Mux
Registers
Writeregister
Writedata
Readdata 1
Readdata 2
Readregister 1Readregister 2
Shiftleft 2
4
Mux
ALU operation3
RegWrite
MemRead
MemWrite
PCSrc
ALUSrc
MemtoReg
ALUresult
ZeroALU
Datamemory
Address
Writedata
Readdata M
ux
Signextend
Add
PC
Memory
Address
Instructionor data
Data
Instructionregister
Registers
Register #
Data
Register #
Register #
ALU
Memorydata
register
A
B
ALUOut
Single-cycle datapath
Multicycle datapath (high-level view)
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Multicycle Datapath
Shiftleft 2
PC
Memory
MemData
Writedata
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Mux
0
1
Mux
0
1
4
Instruction[15– 0]
Signextend
3216
Instruction[25– 21]
Instruction[20– 16]
Instruction[15– 0]
Instructionregister
1 Mux
0
3
2
Mux
ALUresult
ALUZero
Memorydata
register
Instruction[15– 11]
A
B
ALUOut
0
1
Address
Basic multicycle MIPS datapath handles R-type instructions and load/stores:new internal register in red ovals, new multiplexors in blue ovals
![Page 4: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/4.jpg)
• Our goal is to break up the instructions into steps so that– each step takes one clock cycle
– the amount of work to be done in each step/cycle is about equal
– each cycle uses at most once each major functional unit so that such units do not have to be replicated
– functional units can be shared between different cycles within one instruction
• Data at end of one cycle to be used in next must be stored !!
Breaking instructions into steps
![Page 5: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/5.jpg)
Breaking instructions into steps
• We break instructions into the following potential execution steps – not all instructions require all the steps – each step takes one clock cycle1. Instruction fetch and PC increment (IF)
2. Instruction decode and register fetch (ID)
3. Execution, memory address computation, or branch completion (EX)
4. Memory access or R-type instruction completion (MEM)
5. Memory read completion (WB)
• Each MIPS instruction takes from 3 – 5 cycles (steps)
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• Use PC to get instruction and put it in the instruction register.
Increment the PC by 4 and put the result back in the PC.
• Can be described succinctly using RTL (Register-Transfer Language):
IR = Memory[PC]; PC = PC + 4;
Step 1: Instruction Fetch & PC Increment (IF)
IR = Instruction Register
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• Read registers rs and rt in case we need them.
Compute the branch address in case the instruction is a branch.
• RTL:A = Reg[IR[25-21]];B = Reg[IR[20-16]];ALUOut = PC + (sign-extend(IR[15-0]) << 2);
Step 2: Instruction Decode and Register Fetch (ID)
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• ALU performs one of four functions depending on instruction type– memory reference:
ALUOut = A + sign-extend(IR[15-0]);– R-type:
ALUOut = A op B;– branch (instruction completes):
if (A==B) PC = ALUOut;– jump (instruction completes): PC = PC[31-28] || (IR(25-0) << 2)
Step 3: Execution, Address Computation or Branch Completion (EX)
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• Again depending on instruction type:• Loads and stores access memory
– load MDR = Memory[ALUOut];– store (instruction completes) Memory[ALUOut] = B;
• R-type (instructions completes)Reg[IR[15-11]] = ALUOut;
Step 4: Memory access or R-type Instruction Completion
(MEM)
MDR = Memory Data Register
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• Again depending on instruction type:• Load writes back (instruction completes) Reg[IR[20-16]]= MDR;
Important: There is no reason from a datapath (or control) point of view that Step 5 cannot be eliminated by performing
Reg[IR[20-16]]= Memory[ALUOut]; for loads in Step 4. This would eliminate the MDR as well.
The reason this is not done is that, to keep steps balanced in length, the design restriction is to allow each step to contain at most one ALU operation, or one register access, or one memory access.
Step 5: Memory Read Completion (WB)
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Summary of Instruction Execution
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction for branches
Action for jumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completion
Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
1: IF
2: ID
3: EX
4: MEM
5: WB
Step
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Multicycle Execution Step (1):Instruction Fetch
IR = Memory[PC];PC = PC + 4;
4PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
IR = Instruction RegisterMDR = Memory Data Register
Must be MUX
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Multicycle Execution Step (2):Instruction Decode & Register Fetch
A = Reg[IR[25-21]]; (A = Reg[rs])B = Reg[IR[20-15]]; (B = Reg[rt])ALUOut = (PC + sign-extend(IR[15-0]) << 2) *
BranchTarget
Address
Reg[rs]
Reg[rt]
PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
*
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Multicycle Execution Step (3):Memory Reference InstructionsALUOut = A + sign-extend(IR[15-0]);
Mem.Address
Reg[rs]
Reg[rt]
PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (3):ALU Instruction (R-Type)
ALUOut = A op B
R-TypeResult
Reg[rs]
Reg[rt]
PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (3):Branch Instructions
if (A == B) PC = ALUOut;
BranchTarget
Address
Reg[rs]
Reg[rt]
BranchTarget
Address
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (3):Jump Instruction
PC = PC[31-28] concat (IR[25-0] << 2)
JumpAddress
Reg[rs]
Reg[rt]
BranchTarget
Address
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (4):Memory Access - Read (lw)
MDR = Memory[ALUOut];
Mem.Data
PC + 4
Reg[rs]
Reg[rt]
Mem.Address
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (4):Memory Access - Write (sw)
Memory[ALUOut] = B;
PC + 4
Reg[rs]
Reg[rt]
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (4):ALU Instruction (R-Type)
Reg[IR[15:11]] = ALUOUT
R-TypeResult
Reg[rs]
Reg[rt]
PC + 4
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
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Multicycle Execution Step (5):Memory Read Completion (lw)
Reg[IR[20-16]] = MDR;
PC + 4
Reg[rs]
Reg[rt]Mem.Data
Mem.Address
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
PC
IR
MDR
A
B
ALUOUT
![Page 22: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/22.jpg)
Multicycle Datapath with Control I
Shiftleft 2
MemtoReg
IorD MemRead MemWrite
PC
Memory
MemData
Writedata
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction[15– 11]
Mux
0
1
Mux
0
1
4
ALUOpALUSrcB
RegDst RegWrite
Instruction[15– 0]
Instruction [5– 0]
Signextend
3216
Instruction[25– 21]
Instruction[20– 16]
Instruction[15– 0]
Instructionregister
1 Mux
0
3
2
ALUcontrol
Mux
0
1ALU
resultALU
ALUSrcA
ZeroA
B
ALUOut
IRWrite
Address
Memorydata
register
… with control lines and the ALU control block added – not all control lines are shown
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Multicycle Datapath with Control II
Complete multicycle MIPS datapath (with branch and jump capability)and showing the main control block and all control lines
Shiftleft 2
PCMux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Instruction[15– 11]
Mux
0
1
Mux
0
1
4
Instruction[15– 0]
Signextend
3216
Instruction[25– 21]
Instruction[20– 16]
Instruction[15– 0]
Instructionregister
ALUcontrol
ALUresult
ALUZero
Memorydata
register
A
B
IorD
MemRead
MemWrite
MemtoReg
PCWriteCond
PCWrite
IRWrite
ALUOp
ALUSrcB
ALUSrcA
RegDst
PCSource
RegWrite
Control
Outputs
Op[5– 0]
Instruction[31-26]
Instruction [5– 0]
Mux
0
2
Jumpaddress [31-0]Instruction [25– 0] 26 28
Shiftleft 2
PC [31-28]
1
1 Mux
0
3
2
Mux
0
1ALUOut
Memory
MemData
Writedata
Address
New multiplexorNew gates For the jump address
![Page 24: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/24.jpg)
Multicycle Control Step (1):Fetch
IR = Memory[PC];PC = PC + 4;
1
0
1
0
1
0X
0X
0010
1
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
![Page 25: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/25.jpg)
Multicycle Control Step (2):Instruction Decode & Register Fetch
A = Reg[IR[25-21]]; (A = Reg[rs])B = Reg[IR[20-15]]; (B = Reg[rt])ALUOut = (PC + sign-extend(IR[15-0]) << 2);
0
0X
0
0X
3
0X
X
010
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
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0X
Multicycle Control Step (3):Memory Reference Instructions
ALUOut = A + sign-extend(IR[15-0]);
X
2
0
0X
0 1
X
010
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
![Page 27: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/27.jpg)
Multicycle Control Step (3):ALU Instruction (R-Type)
ALUOut = A op B;
0X
X
0
0
0X
0 1
X
???
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
![Page 28: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/28.jpg)
1 if Zero=1
Multicycle Control Step (3):Branch Instructions
if (A == B) PC = ALUOut;
0X
X
0
0
X0 1
1
011
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
![Page 29: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/29.jpg)
Multicycle Execution Step (3):Jump Instruction
PC = PC[21-28] concat (IR[25-0] << 2);
0X
X
X
0
1X
0 X
2
XXX
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
![Page 30: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/30.jpg)
Multicycle Control Step (4):Memory Access - Read (lw)MDR = Memory[ALUOut];
0X
X
X
1
01
0 X
X
XXX
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
![Page 31: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/31.jpg)
Multicycle Execution Steps (4)Memory Access - Write (sw)Memory[ALUOut] = B;
0X
X
X
0
01
1 X
X
XXX
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WDMemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
1
0
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
![Page 32: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/32.jpg)
10
0X
0
X
0
XXX
X
X
1
15 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
0
1
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite
Multicycle Control Step (4):ALU Instruction (R-Type)
Reg[IR[15:11]] = ALUOut; (Reg[Rd] = ALUOut)
![Page 33: Multicycle Approach](https://reader034.vdocuments.us/reader034/viewer/2022052312/568146a6550346895db3c2c8/html5/thumbnails/33.jpg)
Multicycle Execution Steps (5)Memory Read Completion (lw)
Reg[IR[20-16]] = MDR;
1
0
0
X
0
0X
0 X
X
XXX
0
5 5
RD1
RD2
RN1 RN2 WN
WD
RegWrite
Registers
Operation
ALU
3
EXTND
16 32
Zero
RD
WD
MemRead
MemoryADDR
MemWrite
5
Instruction I
32
ALUSrcB
<<2
PC
4
RegDst
5
IR
MDR
MUX
0123
MUX
0
1
MUX
0
1A
BALUOUT
0
1
2MUX
<<2 CONCAT28 32
MUX
0
1
ALUSrcA
jmpaddrI[25:0]
rd
MUX0 1
rtrs
immediate
PCSource
MemtoReg
IorD
PCWr*
IRWrite