M3 – RISC-V ALU Design
Appendix A.5
Module Outline
● Arithmetic and Logical Unit Design
Arithmetic Logic Unit
● Arithmetic operations● Logic operations● Comparison (Equal)
+ - * /==!=
& | ^
Arithmetic and Logic Unit
Control Signal
A
BOutput
ALU
● Start with the simplest operations.
ALU
● Start with the simplest operations.– AND, OR
– Control signal
ALU
● Start with the simplest operations.– AND, OR
– Control signal
● Incrementally add functionality and control
ALU
● Start with the simplest operations.– AND, OR
– Control signal
● Incrementally add functionality and control● Start with a 1-bit ALU
ALU
● Start with the simplest operations.– AND, OR
– Control signal
● Incrementally add functionality and control● Start with a 1-bit ALU● Modify design for a n-bit ALU
Basic ALU Design
AND, OR
Basic ALU Design
Include a Full AdderInclude a Full Adder
Full Adder
a
bSum
CarryOut
cin
S=( A⋅B⋅C i)+( A⋅B⋅C i)+(A⋅B⋅C i)+(A⋅B⋅C i)
Cout=(A+C i)⋅(B+C i)⋅(A+B)
Basic ALU Design
ADD, AND, OR
Basic ALU Design
ADD, AND, OR
1-bit ALU
CarryIn
Operation
a
b
Result
CarryOut
Basic 64b ALU
64 1-bit ALUs in Ripple Carry arrangement
Basic 1-bit ALU Design
Subtraction?Subtraction?ADD, AND, OR
Adder/Subtractor
+
0
S=a+b
Cout
a
b
Adder/Subtractor
+ -
0 1
S=a+b
Cout C
out
a
b
a
bS=a-b
Adder/Subtractor
+ -
0 1
S=a+b
Cout C
out
a
b
a
bS=a-b
-b = b + 1-b = b + 1
Adder/Subtractor
+ -
0 1
S=a+b
Cout C
out
a
b
a
bS=a-b
+/-+/-
cin
Cout
a
b
Cin== (0:1) ?
S=a+b : S=a-bb
ALU DesignA±B, AND, ORA±B, AND, OR
A–B: Binvert = 1; CarryIn = 1.A+B: Binvert = 0; CarryIn = 0.
A–B: Binvert = 1; CarryIn = 1.A+B: Binvert = 0; CarryIn = 0.
ALU DesignA±B, AND, ORA±B, AND, OR
NOR?NOR?A–B: Binvert = 1; CarryIn = 1.A+B: Binvert = 0; CarryIn = 0.
A–B: Binvert = 1; CarryIn = 1.A+B: Binvert = 0; CarryIn = 0.
NAND, NOR
A NAND B = (A AND B)
= A OR B
A NAND B = (A AND B)
= A OR BA NOR B = (A OR B)
= A AND B
A NOR B = (A OR B)
= A AND B
ALU Design
a NAND b: Ainvert=1;Binvert=1;Op=1a NAND b: Ainvert=1;Binvert=1;Op=1
a NOR b: Ainvert=1;Binvert=1;Op=0a NOR b: Ainvert=1;Binvert=1;Op=0
ALU Design
A±B, AND, OR, NOR, NAND
ALU Design
SLT?SLT?
Set Less Than
● Set a status bit if (a < b)
Set Less Than
● Set a status bit if (a < b)● If (a<b); (a-b) is -ve● Calculate (a-b). Observe sign bit of the result
ALU Design
slt(a,b): Binvert=1; CarryIn=1; Operation=3;
MSB
ALU Design
A±B, AND, OR, NOR, NAND, SLT
ALU Design
Overflow?Overflow?A±B, AND, OR, NOR, NAND, SLT
ALU Design
A±B, AND, OR, NOR,SLT, Overflow detection
ALU Design
1-bit ALU
Ainvert
Binvert
CarryIn
Operation
a
b
Sum
Set
Overflow
CarryOut
Less
64-bit ALU
Zero detection?Zero detection?
64-bit ALU
ALU
ALU – Control Signals
Ainvert Binvert CarryIn Operation
AND
OR
ADD
SUB
NAND
NOR
SLT
ALU – Control Signals
Ainvert Binvert CarryIn Operation
AND 0 0 0 00
OR
ADD
SUB
NAND
NOR
SLT
ALU – Control Signals
Ainvert Binvert CarryIn Operation
AND 0 0 0 00
OR 0 0 0 01
ADD
SUB
NAND
NOR
SLT
ALU – Control Signals
Ainvert Binvert CarryIn Operation
AND 0 0 0 00
OR 0 0 0 01
ADD 0 0 0 10
SUB 0 1 1 10
NAND
NOR
SLT
ALU – Control Signals
Ainvert Binvert CarryIn Operation
AND 0 0 0 00
OR 0 0 0 01
ADD 0 0 0 10
SUB 0 1 1 10
NAND 1 1 0 01
NOR 1 1 0 00
SLT
ALU – Control Signals
Ainvert Binvert CarryIn Operation
AND 0 0 0 00
OR 0 0 0 01
ADD 0 0 0 10
SUB 0 1 1 10
NAND 1 1 0 01
NOR 1 1 0 00
SLT 0 1 1 11
ALU – Control Signals
Ainvert Binvert CarryIn Operation
AND 0 0 0 00
OR 0 0 0 01
ADD 0 0 0 10
SUB 0 1 1 10
NAND 1 1 0 01
NOR 1 1 0 00
SLT 0 1 1 11
Ignore the effect of CarryIn during NAND and NOR execution. Binvert == CarryIn.
ALU – Control Signals
ABOp
AND 0000
OR 0001
ADD 0010
SUB 0110
NAND 1101
NOR 1100
SLT 0111
ALU Control
+ - * /==!=
& | ^
Arithmetic and Logic Unit
Control Signal
A
BOutput
ALUCONTROL
ALUCONTROL
Instruction
ALU Control – AND Instruction
+ - * /==!=
& | ^
0000
A
B
A & B
ALUCONTROL
ALUCONTROL
AND
ALU Control – AND Instruction
+ - * /==!=
& | ^
0000
A
B
A & B
ALUCONTROL
ALUCONTROL
AND
What info to pass to ALU Controlto identify AND Operation?
What info to pass to ALU Controlto identify AND Operation?
Control Signals for Implementation
ABOp
AND 0000
OR 0001
ADD 0010
SUB 0110
Control Signals for Implementation
ABOp
AND 0000
OR 0001
ADD 0010
SUB 0110
From ISA ManualFrom ISA Manual
Control Signals for Implementation
ABOp
AND 0000
OR 0001
ADD 0010
SUB 0110
All are R-type InstructionsAll are R-type Instructions
Control Signals for Implementation
ABOp
AND 0000
OR 0001
ADD 0010
SUB 0110
All are R-type InstructionsAll are R-type Instructions
Which fields identify operation?Which fields identify operation?
Control Signals for Implementation
ABOp
AND 0000
OR 0001
ADD 0010
SUB 0110
All are R-type InstructionsAll are R-type Instructions
opcode, funct7, funct3 identify operationopcode, funct7, funct3 identify operation
Instructions using the ALU
Instructions using the ALU
● Arithmetic and Logic Instructions– add, sub, and, or
– R-type
Instructions using the ALU
● Memory transfer instructions– Effective address
calculation– ld, sd– I-type, S-type– Identified by opcode
● Arithmetic and Logic Instructions– add, sub, and, or
– R-type
Instructions using the ALU
● Memory transfer instructions– Effective address
calculation
– ld, sd
– I-type, S-type
– Identified by opcode
● Branch instructions (beq)– For Zero detection
– SB type
– Identified by opcode
● Arithmetic and Logic Instructions– add, sub, and, or
– R-type
Instructions using the ALU
● Arithmetic and Logic Instructions (R-type)● ld (I-type), sd (S-type)● beq (SB-type)
Instructions using the ALU
● Arithmetic and Logic Instructions (R-type)● ld (I-type), sd (S-type)● beq (SB-type)
ALU – Control Signals
ABOp
AND 0000
OR 0001
ADD 0010
SUB 0110
Which control signals forLD, SD, BEQ?
Which control signals forLD, SD, BEQ?
ALU – Control Signals
Input to ALU CU Output Control SignalsABOp
AND 0000
OR 0001
ADD, LD, SD 0010
SUB, BEQ 0110
Main and ALU Control Units
+ - * /==!=
& | ^
ABOp
A
BResult
ALUCONTROL
ALUCONTROL
MAINCONTROL UNIT
MAINCONTROL UNIT
32b instructionInstruction
Type
Control Unit – R-type
+ - * /==!=
& | ^
ABOp
A
BResult
ALUCONTROL
ALUCONTROL
MAINCONTROL UNIT
MAINCONTROL UNIT
32b instruction
Control Unit – R-type
+ - * /==!=
& | ^
ABOp
A
BResult
ALUCONTROL
ALUCONTROL
MAINCONTROL UNIT
MAINCONTROL UNIT
32b instruction
ALU, R-type !ALU, R-type !
Control Unit – R-type
+ - * /==!=
& | ^
ABOp
A
BResult
ALUCONTROL
ALUCONTROL
MAINCONTROL UNIT
MAINCONTROL UNIT
32b instruction
R-type,funct7,funct3
ALU, R-type !ALU, R-type !
Control Unit – LD, SD
+ - * /==!=
& | ^
ABOp
A
BResult
ALUCONTROL
ALUCONTROL
MAINCONTROL UNIT
MAINCONTROL UNIT
32b instruction
EAC,opcode
LD, SDLD, SD
Ignoring funct3Ignoring funct3
Control Unit – BEQ
+ - * /==!=
& | ^
ABOp
A
BResult
ALUCONTROL
ALUCONTROL
MAINCONTROL UNIT
MAINCONTROL UNIT
32b instruction
Branch,opcode
BEQBEQ
Main CU to ALU CU
● Type of Instruction– ALU (R-type), Effective Address Calculation, Branch
Instruction
● Opcode (to identify operation)– funct7, funct3 in case of R-type
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD
SD
BEQ
R-type
R-type
R-type
R-type
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword
SD 00 Store doubleword
BEQ 01 Branch if equal
R-type 10 add
R-type 10 sub
R-type 10 and
R-type 10 or
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword XXXXXXX XXX add 0010
SD 00 Store doubleword
BEQ 01 Branch if equal
R-type 10 add
R-type 10 sub
R-type 10 and
R-type 10 or
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword XXXXXXX XXX add 0010
SD 00 Store doubleword XXXXXXX XXX add 0010
BEQ 01 Branch if equal
R-type 10 add
R-type 10 sub
R-type 10 and
R-type 10 or
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword XXXXXXX XXX add 0010
SD 00 Store doubleword XXXXXXX XXX add 0010
BEQ 01 Branch if equal XXXXXXX XXX subtract 0110
R-type 10 add
R-type 10 sub
R-type 10 and
R-type 10 or
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword XXXXXXX XXX add 0010
SD 00 Store doubleword XXXXXXX XXX add 0010
BEQ 01 Branch if equal XXXXXXX XXX subtract 0110
R-type 10 add 0000000 000 add 0010
R-type 10 sub
R-type 10 and
R-type 10 or
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword XXXXXXX XXX add 0010
SD 00 Store doubleword XXXXXXX XXX add 0010
BEQ 01 Branch if equal XXXXXXX XXX subtract 0110
R-type 10 add 0000000 000 add 0010
R-type 10 sub 0100000 000 subtract 0110
R-type 10 and
R-type 10 or
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword XXXXXXX XXX add 0010
SD 00 Store doubleword XXXXXXX XXX add 0010
BEQ 01 Branch if equal XXXXXXX XXX subtract 0110
R-type 10 add 0000000 000 add 0010
R-type 10 sub 0100000 000 subtract 0110
R-type 10 and 0000000 111 AND 0000
R-type 10 or
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword XXXXXXX XXX add 0010
SD 00 Store doubleword XXXXXXX XXX add 0010
BEQ 01 Branch if equal XXXXXXX XXX subtract 0110
R-type 10 add 0000000 000 add 0010
R-type 10 sub 0100000 000 subtract 0110
R-type 10 and 0000000 111 AND 0000
R-type 10 or 0000000 110 OR 0001
Truth Table of the ALU CU
InstrnOpcode
ALUOp
Operation funct7 funct3 ALU Action ALU Control Input
LD 00 Load doubleword XXXXXXX XXX add 0010
SD 00 Store doubleword XXXXXXX XXX add 0010
BEQ 01 Branch if equal XXXXXXX XXX subtract 0110
R-type 10 add 0000000 000 add 0010
R-type 10 sub 0100000 000 subtract 0110
R-type 10 and 0000000 111 AND 0000
R-type 10 or 0000000 110 OR 0001
Control Unit identifiesclass of instruction
Control Unit identifiesclass of instruction
Inputs to the ALU CUInputs to the ALU CU Output of ALU CUOutput of ALU CU
Truth Table of the ALU CU
Truth Table of the ALU CU
Truth Table of the ALU CU
ALU Control Unit
Module Outline
● Arithmetic and Logical Unit Design– ALU Design in HDL