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Analog and Low-Power Digital
VLSI Design
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Lecture 1
Introduction to Low-Power
Design Motivation
Historical Drivers of Low-Power Design
Microprocessor Scaling
Power Sources
Low-Power Design Methods
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Motivation for Low-Power Design
Scaling of Si CMOS technology Higher functionality with smaller chips
Higher performance at lower cost
Portability
New portable compute-intensive applications
Multi-media Video display and capture
Audio reproduction & capture
Handwriting recognition
Notebook computer Personal data assistant
Implantable medical electronics
Need for satisfactory battery life span
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Historical Drivers of Low-Power
Design
Pocket calculators
Hearing aids
Implantable pacemakers and cardiac
defibrilators
Portable military equipment for individual
soldiers
Wristwatches
Wireless computing
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Microprocessor Scaling
Problems
Feature sizes of transistors keep shrinking Magnitude of power/unit area keeps growing
Heat removal & cooling is worsening
Example: VDD5 V 3.3 V 2.5 V Power dissipation did not reduceplateaued at 30 W
Higher cooling costs for power densities of 50 W/cm2
Example: speech recognition needs a full PCB
and 20 Wof power to handle a 20,000 wordvocabulary NiCd batteries only provide 26 W / poundbattery
weight
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Sources of Power Dissipation
Charging current
Due to logic transitions causing logic gates to
charge/discharge load capacitance
Short-circuit current p-tree and n-tree momentarily shorted as logic gate
changes state
Leakage current
Diode leakages around transistors and n-wells
Increasing 20 times for each new fabrication
technology
Went from insignificant to a dominating factor
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Design for Low-Power Techniques
Reduced supply voltage Charging power varies as VDD2
Reduce transistor threshold voltages to maintain noise margins
But reduced thresholds increase leakage currents exponentially
Change your CMOS logic familyuse a low-power one
Transistor resizingto speed-up circuit and reduce power
Use parallelism and pipeliningin system architectureusemore, but slower, hardware
Standby modesclock disabling and power-down of
selected logic blocks Adiabatic computingavoid gain/loss of heat during
computing
Software redesignto lower power dissipation
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Outline
Power and Energy
Dynamic Power
Static Power Low Power Design
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Power and Energy
Power is drawn from a voltage source attached
to the VDDpin(s) of a chip.
Instantaneous Power:
Energy:
Average Power:
( ) ( )DD DD
P t i t V
0 0
( ) ( )
T T
DD DDE P t dt i t V dt
avg
0
1( )
T
DD DD
EP i t V dt
T T
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Dynamic Power
Cfsw
iDD
(t)
VDD
Dynamic power is required to charge and dischargeload capacitances when transistors switch.
One cycle involves a rising and falling output.
On rising output, charge Q = CVDDis required
On falling output, charge is dumped to GND
This repeats Tfswtimes
over an interval of T
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Dynamic Power Cont.
Cfsw
iDD
(t)
VDD
dynamic
0
0
sw
2
sw
1( )
( )
T
DD DD
TDD
DD
DD
DD
DD
P i t V dtT
Vi t dt
T
V
Tf CV T
CV f
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Activity Factor
Suppose the system clock frequency = f Let fsw= af, where a= activity factor
If the signal is a clock, a= 1
If the signal switches once per cycle, a= Dynamic gates:
Switch either 0 or 2 times per cycle, a=
Static gates: Depends on design, but typically a= 0.1
Dynamic power: 2dynamic DDP CV fa
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Short Circuit Current
When transistors switch, both nMOS and
pMOS networks may be momentarily ON
at once
Leads to a blip of short circuit current.
< 10% of dynamic power if rise/fall times
are comparable for input and output
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Example
200 Mtransistor chip
20M logic transistors
Average width: 12 l
180M memory transistors
Average width: 4 l
1.2 V 100 nm process
Cg= 2 fF/mm
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Dynamic Example
Static CMOS logic gates: activity factor =
0.1
Memory arrays: activity factor = 0.05
(many banks!)
Estimate dynamic power consumption perMHz. Neglect wire capacitance and
short-circuit current.
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Dynamic Example
Static CMOS logic gates: activity factor = 0.1
Memory arrays: activity factor = 0.05 (many
banks!)
Estimate dynamic power consumption per MHz.Neglect wire capacitance.
6
logic
6
mem
2
dynamic logic mem
20 10 12 0.05 / 2 / 24
180 10 4 0.05 / 2 / 72
0.1 0.05 1.2 8.6 mW/MHz
C m fF m nF
C m fF m nF
P C C f
l m l m
l m l m
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Ratio Example
The chip contains a 32 word x 48 bit ROM
Uses pseudo-nMOS decoder and bitline pullups
On average, one wordline and 24 bitlines are high
Find static power drawn by the ROM b = 75 mA/V2
Vtp= -0.4V
Solution: 2
pull-up
pull-up pull-up
static pull-up
24A2
29W
(31 24) 1.6 mW
DD tp
DD
V V
I
P V I
P P
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Leakage Example Cont.
Estimate static power:
High leakage:
Low leakage:
If no low leakage devices, Pstatic= 749 mW (!)
6 620 10 0.2 12 0.05 / 2.4 10m ml m l m
6
6 6
20 10 0.8 12 0.05 /
180 10 4 0.05 / 45.6 10
m
m m
l m l
l m l m
6
6
2.4 10 20 / / 2 3 /
45.6 10 0.02 / / 2 0.002 /
32
38
static
static static DD
I m nA m nA m
m nA m nA m
mA
P I V mW
m m m
m m m
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Low Power Design
Reduce dynamic power
a: clock gating, sleep mode
C: small transistors (esp. on clock), short wires
VDD: lowest suitable voltage
f: lowest suitable frequency
Reduce static power
Selectively use ratioed circuits
Selectively use low Vtdevices
Leakage reduction:
stacked devices, body bias, low temperature