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Linear Time Algorithm to Find All Relocation Positions for EUV Defect
Mitigation
Yuelin Du, Hongbo Zhang, Qiang Ma and Martin D. F. Wong
ASPDAC‘13
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Outline
• Introduction• Problem formulation• Algorithm• Experimental results • Conclusion
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Introduction
• With the current VLSI technology shrinking to sub-20nm, EUV lithography has become a leading candidate to replace the 193nm technology.
• But, the absence of defect-free blanks in EUV mask fabrication, a methodology that is able to deal with defective blanks will be required
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Introduction
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Introduction
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Problem formulation
• Maximize the number of valid dies within the exposure field.
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Problem formulation
• Find the all feasible regions.
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Algorithm
• Blank Region Partition– Blank Region with No Effective Defect– Blank Region with Single Effective Defect– Blank Region with Multiple Effective Defect
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Blank Region Partition
• no part of the die can be shifted outside the exposure field• Each defect has a unique impact range
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Blank Region with No Effective Defect
• The bottom left corner of the die is located within this region, no defect will locate within the die area, and hence all defect impact is completely mitigated.
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Blank Region with Single Effective Defect
• Step 1. Impacted Feature Extraction• Step 2. Impacted Feature Shrinking• Step 3. Shrunk Die Area Rotation and Shift
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Impacted Feature Extraction
• The width/height of 3’ is equal to the width/height of 3 plus the width/height of the defect.
• Impacted Feature: F2,F3
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Impacted Feature Shrinking
• In the second step, the impacted features and the impacted die area 3 are shrunk by the size of the effective defect.
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Shrunk Die Area Rotation and Shift
• Therefore, the shrunk features in 3’’ and the feasible regions in 3 are diagonally symmetric.
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Blank Region with Multiple Effective Defect
• The objective is to find the feasible regions to locate the die where all defects are covered by features simultaneously.
• We first consider each defect separately• And the sets of feasible regions are
intersected to obtain the final feasible region
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Time Complexity Analysis
• n: the number of features in the die.
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Improved Strategy for Layout Intersection
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Experimental result
• We implement our algorithm using C++ on a workstation with an Intel Xeon E5620 2.40GHz CPU and 36GB memory
• Then we carry out our experiments with a 11nm design
• The defects size form 50nm to 200nm• The size of the exposure field is 10.4cm by
13.2cm.
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Experimental results
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Experimental results
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Conclusion
• In this paper we propose an efficient algorithm to find all layout relocation positions to place a valid die on a defective blank for defect mitigation.
• By simple parallelism, the efficiency can be further improved.