Download - Lecture4: Sequential Circuits Continued
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Lecture 4: Sequential CircuitsContinued
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Clock signals§ “Clocks” are a regular
pulse signal, where the high value indicatesthat the output of the latch may be sampled.
§ Usually drawn as:
§ But looks more like:time
5Vvoltage
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Signal restrictions
§ What’s the limit to how fast the latch circuit can be sampled?
§ Determined by: ú latency time of transistors
Setup and hold timeú setup time for clock signal
Jitter Gibbs phenomenon
§ Frequency = how many pulses occur per second, measured in Hertz (or Hz).
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Clocked SR latch
§ Adding another layer of NAND gates to the SRlatch gives us a clocked SR latch or gated SR latch)ú Basically, a latch with a control input signal C.
§ The input C is often connected to a pulse signal that alternates regularly between 0 and 1 (clock)
Q
Q
S
R
C
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Clocked SR latch behaviour§ Same behaviour as SR
latch, but with timing:ú Start off with S=0 and R=1, like earlier example.
ú If clock is high, the first NAND gates invert those values, which get inverted again in the output.
ú Setting both inputs to 0maintains the output values.
Q
Q
S
R
C
0
1
1
0
10
1
Q
Q
S
R
C
0
1
1
0
10
10 1
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1
1
1
Clocked SR latch behaviour§ Continued from previous:
ú Now set the clock low.ú Even if the inputs change,
the low clock input prevents the change from reaching the second stage of NAND gates.
ú Result: the clock needs to be high in order for the inputs to have any effect.
Q
Q
S
R
C
0
0
1
1
00
1
1
1
0 Q
Q
S
R
C
0
0
0
1
1 1
1
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Clocked SR latch
§ This is the typical symbol for a clocked SR latch.§ This only allows the S and R signals to affect the
circuit when the clock input (C) is high.§ Note: the small NOT circle after the Q output is
simply the notation to use to denote the inverted output value. It’s not an extra NOT gate.
Q
Q
S
R
C
S
R
C
Q
Q
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Clocked SR latch behaviour
§ Wait!§ Where’s the clock?§ There’s a better way to look at this….
Q
Q
S
R
C
QT S R QT+1 Result
0 0 0 0 no change
0 0 1 0 reset
0 1 0 1 set
0 1 1 ? ???
1 0 0 1 no change
1 0 1 0 reset
1 1 0 1 set
1 1 1 ? ???
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Clocked SR latch behaviour
§ Assuming the clock is 1, we still have a problem when S and R are both 1, since the state of Q is indeterminate.ú Better design: prevent S and R from both going high.
Q
Q
S
R
C
C S R QT+1 Result
0 X X QT no change
1 0 0 QT no change
1 0 1 0 reset
1 1 0 1 set
1 1 1 ? Undefined
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D latch
§ By making the inputs to R and S dependent on a single signal D, you avoid the indeterminate state problem.
§ The value of D now sets output Q low or high whenever C is high.
Q
Q
D
C
QT D QT+1
0 0 0
0 1 1
1 0 0
1 1 1
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D latch
§ This design is good, but still has problems.ú i.e. timing issues.ú How can we maintain state?
Q
Q
D
CD
C
Q
Q
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Latch timing issues
§ Consider the circuit on the right:
§ When the clock signalis high, the output lookslike the waveform below:ú Output keeps toggling back and forth.
D
C
Q
Q
Q
C…what happens next?
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Latch timing issues
§ Consider the circuiton the right:
§ When the clock signalis high, the output lookslike the waveform below:ú Output keeps toggling back and forth.
D
C
Q
Q
Q
C
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D-Latch is transparent!
§ Transparent means thatú Any changes to its inputs are visible to the output
when control signal (Clock) is 1.
§ Key Take-away: The “output of a latch should not be applied directly or through combinational logic to the input of the same or another latch when they all have the same control (clock) signal.”
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Latch timing issues§ Preferable behaviour:
ú Have output change only once when the clock pulse changes.
ú Solution: create disconnect between circuit output and circuit input, to prevent unwanted feedback and changes to output.
S
R
C
Q
Q
S
C
Q
QR
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SR master-slave flip-flop
§ A flip-flop is a latched circuit whose output is triggered with the rising edge or falling edge of a clock pulse.
§ Example: The SR master-slave flip-flop
S1
R1
C
Q
Q
S0C
Q
QR0
S
R
Q
QC
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SR master-slave flip-flopS1
R1
C
Q1
Q1
S0C
Q0
Q0R0
S
C
R
Q
S
R
Q
QC
propa-gationdelay
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Edge-triggered D flip-flop
§ SR flip-flops still have issues of unstable behaviour.
§ Solution: D flip-flopú Connect D latch to the input of a SR latch.ú Negative-edge triggered flip-flop (like the SR)
S
R
C
Q
Q
D
C
Q
Q
D Q
QC
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Flip-flop behaviour§ Observe the behaviour:
ú If the clock signal is high, the input to the first flip-flop is sent out to the second.
ú The second flip-flop doesn’t do anything until the clock signal goes down again.
ú When it clock goes from high to low, the first flip-flop stops transmitting a signal, and the second one starts.
S
RC
Q
Q
DC
Q
Q
D Q
QC
0 0
0
Z
Z1
0
1
S
RC
Q
Q
DC
Q
Q
D Q
QC
0 0
1
01
0
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Flip-flop behaviour§ Continued from previous:
ú If the input to D changes, the change isn’t transmitted to the second flip-flop until the clock goes high again.
ú Once the clock goes high, the first flip-flop starts transmitting at the same time as the second flip-flop stops.
0
1
S
RC
Q
Q
DC
Q
Q
D Q
QC
0 0
10
1
0
1
0S
RC
Q
Q
DC
Q
Q
D Q
QC
1
01
1
0
0
1
1
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Confused yet?
§ Maybe a demonstration will help
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Edge-triggered flip-flop
§ Alternative: positive-edge triggered flip-flops
§ These are the most commonly-used flip-flop circuits (and our choice for the course).
DC
S
R
C
Q
Q
D
C
Q
Q
Q
Q
D
C
Q
Q
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Notation
§ Latches
§ Master-slave flip-flops
§ Edge-triggered flip-flops
D with 0 Control
Triggered D
S
R
SR SR
S
R
D
C
D with 1 Control
D
C
D
C
Triggered D
Triggered SR
S
R
C
D
C
Triggered SR
S
R
C
Triggered D
D
C
Triggered D
D
C
D
C
D
C
Note: While all these are possible, we mainly use edge-triggered D flip-flops in our designs.
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Other Flip-Flops§ The T flip-flop:
ú Like the D flip-flop, except that it togglesits value whenever the input to T is high.
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Other Flip-Flops
§ The JK Flip-Flop:ú Takes advantage of
all combinations of two inputs (J & K) to produce four different
behaviours: if J and K are 0, maintain output. if J is 0 and K is 1, set output to 0. if J is 1 and K is 0, set output to 1. if J and K are 1, toggle output value.
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Sequential circuit design
§ Similar to creatingcombinational circuits,with extra considerations:ú The flip-flops now provide
extra inputs tothe circuitú Extra circuitry needs to be
designed for the flip-flop inputs.ú …which is next J
Combinational Circuit
Inputs Outputs
Storage Units