Download - Lecture16 Logic Synthesis.ppt
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Logic Function Optimization
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Combinational Logic CircuitRegular SOP and POS designsDo not care expressionsDigital logic circuit applicationsKarnaugh MapsMinimization of logic functions
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Combinational Logic CircuitThe function D=ABC+ABC+ABC+ABCcan be implemented in the sum of products (SOP) form as follows:Minterm:Product that contains all input variables or their complements for which function value is 1
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Combinational Logic CircuitThe function D=(A+B+C)(A+B+C)(A+B+C)(A+B+C)can be implemented in the product of sums (POS) form as follows:Notice that SOP and POS forms can be implemented in such regular designs for any function.
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Combinational Logic CircuitFind canonical sum of products (SOP) form for the following function F=AB+AC+ABCcan be implemented in the :We have:F=ABC+ABC+ABC+ABC+ABC
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Combinational Logic CircuitTheorem:Each function can be represented in the unique form of SOP or POS.
Let us obtain POS from for the following function:D=ABC+ABC+ABC+ABC
Using DeMorgans lawD=(ABC+ABC+ABC+ABC)==(A+B+C)(A+B+C)(A+B+C)(A+B+C)
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Two Implementations of XOR Logic Circuit
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Do not Care - Logic CircuitDo not care condition is when the output function value is not important for a specific input combination
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Do not Care - Logic CircuitDo not care can be used to simplify the circuit implementation
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To design a digital logic circuit to control LED displaywe must first come up with a truth table.How to translate a desired circuit functionality into a truth table?How to Design a Digital Logic Circuit?
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Digital Logic Circuit OutputThen each output ABCDEFG must be implemented as a separate logic function of 4 input bits xywz that represent BCD code of integer value
Decimal IntegerBCDxywzABCDEFGsegments000001111110100010110000200101101101300111111001401000110011501011011011601100011111701111110000810001111111910011110011
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Digital Logic Circuit OutputFor instance to control the segment A the logic function is
FA=abcd+abc+abd+abc
or for segment BFB=ab+abcd+abcd+abc
Decimal IntegerBCDabcdABCDEFG000001111110100010110000200101101101300111111001401000110011501011011011601100011111701111110000810001111111910011110011
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Binary-OctalDecoder CircuitDesign example
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Karnaugh Maps in Logic CircuitKarnaugh maps can be used to simplify the logic function and its design
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Karnaugh Maps in Logic CircuitKarnaugh map uses hypercube with the same function value in the whole cube to reduce the number of terms in the logic function
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Karnaugh Maps in Logic CircuitThe whole cube in the Karnaugh map is represented by a single product term. For instance cubes in the example figure are.
(a) ab(b) ab(c) ab
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Karnaugh Maps in Logic Circuit
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Karnaugh Maps in Logic CircuitUse Karnaugh maps to obtain minimum SOP for these functions:
Z=WXY+WXY+WXY+WXYD=ABC+AB+ABCE=ABD+ABCD+ABCD
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Do not Care - Logic CircuitF=L+DH
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Digital Logic Circuit OutputUsing Karnaugh map we can minimize
FA=abcd+abc+abd+abc=bcd+abc+abd+abc
ACDB
Decimal IntegerBCDabcdABCDEFG000001111110100010110000200101101101300111111001401000110011501011011011601100011111701111110000810001111111910011110011
1111111
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Segment A logic function isFA=abcd+abc+abd+abc
With do not caresFA=a+abc+bd+cb
ACDBOutput A of 7 Segments Decoder
Decimal IntegerBCDabcdABCDEFG000001111110100010110000200101101101300111111001401000110011501011011011601100011111701111110000810001111111910011110011
10011xx1xxx0111
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Digital Logic Circuit OutputUsing Karnaugh map we can minimizeFB=ab+abcd+abcd+abc==bc+acd+acd+ ab
BACD
Decimal IntegerBCDabcdABCDEFG000001111110100010110000200101101101300111111001401000110011501011011011601100011111701111110000810001111111910011110011
11111111
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Digital Logic Circuit OutputUsing Karnaugh map we can minimizeFB=ab+abcd+abcd+abc==ab+ bc+acd+acdWith do not caresFB=cd+cd+b
BACD
Decimal IntegerBCDabcdABCDEFG000001111110100010110000200101101101300111111001401000110011501011011011601100011111701111110000810001111111910011110011
11011xx1xx1011
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