Download - Lecture05 Gatelevel Layout
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Lecture 5 ECE 425
Lecture 5 -- Gate-Level Layout
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Lecture 5 ECE 425
Outline
Stick Diagram Layouts
Complete Gate Layouts
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So, What is a Layout, Anyway?
We tend to think about circuits as collections oftransistors, capacitors, etc. that are connected by wires
As we discussed last time, these devices are physically
implemented as a set of regions of different materials
(diffusion, gate, poly, etc.) A layout for a circuit is a set of regions of different types of
material that implements the devices and wires that make
up the circuit
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Representing Layouts
To make layouts easier to read, weve adopted a standardset of colors for different layers
Polysilicon: red
N-diffusion: green
P-diffusion: yellow Contact/Via: black
Metal1: blue
Metal2: purple
These are just conventions, dont have any real meaning Theyre the most common conventions, but others exist
No real conventions for metal layers 3 and up
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Starting Simple -- Transistors
Any time poly runs over diffusion, a transistor is created
When we draw layouts, we draw the diffusion as
extending under the gate even though it doesnt actually.
Poly
Diffusion
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Stick Diagram Layouts
Motivation: Want way to estimate size of circuits withoutdoing full layout
Observation: Many designs are wire-limited, in that the
size of the layout is determined more by the number of
wires that have to flow over a given region than the
transistors.
Approach: Do dimensionless stick-figure layout that
shows important connections, spatial relationships without
the details of layout
p-MOS Transistor
polypoly
p-diffusionn-diffusion
n-MOS Transistor
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Stick Diagrams
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Stick Diagram Examples
In Out
Vdd
GND
Inverter 3-Input NANDVdd
GND
OutA B C
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Full Layout Example -- Inverter
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Better Inverter Layout
Vdd
Vss
Out
In
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NAND Gate
Vdd
A
B
Vss
Out
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Better NAND Layout
Vdd
Vss
A
B
Out
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Gate Design for Integrated Circuits
Integrated circuits contain many gates
Except for the most performance-critical cases, wed
generally prefer good gate designs that can easily be
assembled into systems over the best design for a gate
For performance-critical modules, often layout theentire module as a single block
Today, well present an approach that gives good layouts
with relatively low design effort and makes it easy to fit
gates together.
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Making Gates Fit Together
If you design gates to minimize the size of each gate,wind up with lots of random shapes that dont fit togetherwell.
Instead, typically require that one of the dimensions of
each gate be a constant value This constant is called the gatepitch, as it defines the
height of a row of gates
Different gates have varying width, but the same height
Require that all gates have power, ground, clock wires atthe same place to make them easy to wire up
Designs may also require that gates leave empty tracksfor routing signals between gates
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More Graph Theory
Apathin a graph is a series of connected edges An Euler path(Euler trail) is a path through a graph that
contains every edge exactly once
Not all graphs have Euler paths
Graph has Euler path iff either all vertices have evendegree or exactly two vertices have odd degree
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Ok, What Does that Have to do with Layout?
To lay out a gate with unbroken diffusion, find Euler pathsthrough the n- and p-networks in which the edges appear
in the same order
That gives you the ordering on the inputs to the gate
If you cant find such an ordering, have to break up one or
both the diffusion lines
Break the graphs into pieces, find Euler paths on the
pieces
In some cases, may have to stack the diffusion lines
vertically
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Example with one Euler Path
A B CD
Z
VDD
VSS
Z
IC D
A
AI2
B
B
C D
1
I3
V
VSS
DD
Z
CDBA
A
B
C D
I1
I2
I3
C D
B
A
C
D
BA
Z
A B D C
C D
A
B
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Gate That Requires Multiple Paths
1
3
ba
d
f
ec
4
2
a bf
c e d
3 4
5
1
2 a
c
ed
b
f
a fb
d e c
a b f
Two Paths: abf, dec
d ce
1
12 23
34 4
1
5
2 2
33
44
x
x
x x x
xxxxxxx
x x xx
Out
Vdd
Vss
d
e
f b
c
a
Vdd
a
b
d
f c
e
Vss
z
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Using Inputs Multiple Times May Require Stacked
Diffusion
F = a(b + c + d) + b c
b
Vdd
a b c d
1 12 3
3
4
4
4
4
3
32 11
Vss
Out
x x x xx
xx
x
x x xx x
x
a
d
b
a
a c
a
Vs s
Vdd a
cb
d
c
13
2
4
ac
d
4
3 1
2
a
ab
d
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XOR Gate -- Broken and Stacked Lines
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Wrapping Up
Reading -- Section 1.5 in your book
Next time: Clocked structures and latches