Xuan ‘Silvia’ Zhang Washington University in St. Louis
http://classes.engineering.wustl.edu/ese566/
Lecture 6 Sequential Circuits and Memory
Outline
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SR Latch
• Basic NOR latch
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S (set)
R (reset) Q
Q
S
R
0
0
not allowed
Q
Q
1
0
tpd
set
reset
unstable No change
Other SR Latches
• Clocked
• NAND SR latch
4
1
2
Q
Q
S
R
Clk
Q S (set)
R (reset) Q
S
R
C
Q
Q
S
R
D Latch
• Truth table
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S R Q+ Q+ 0 0 hold, 0 1 0 1 1 0 1 0 1 1 0 0
SR latch:
C
D Q
Q
D Q
C
Q
D Q(t+1) 0 0 1 1
D latch
Level-Sensitive Latch
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Flip-Flop
• Latch timing issue – transparent when C = 1 – state should change only once every new clock cycle
• Master-slave flip flop – break feedthrough
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Combina-tional Logic D Latch
(storage)
Inputs Outputs
State Next State
X0 X1 X0 X1
X2
C=0
X1 X1 X1 X2 X3
→1
C
S
R
Q
Q
Q
Q
C R
Q
Q
C
S
R
S Y
/Y
Flip-Flop Timing Issue
• 1’ catching
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C
S
R
Y
Q Slave out
Master out
Master active
Slave active
1’ catching
wrong output should have been 0
C
S
R
Q
Q
Q
Q
C R
Q
Q
C
S
R
S Y
Y’
Glitch
Edge-Triggered D Flip-Flop (DFF)
• Why edge trigger? • D replace S and R input
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C
S
R
Q
Q C
Q
Q C
D Q D
Q
C
D
Y
Q Slave out
Master out
Master active
Slave active no 1’ catching
correct output
Y
Edge-Sensitive Flip-Flop
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Outline
Sequential Circuits Timing Analysis Memory
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Timing in Digital Logic
• Setup time • Hold time
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Timing in Digital Logic
• Launch edge and latch edge
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Timing in Digital Logic
• Data arrival time: using launch edge
Tclk Clock Skew
Tco FF Clock-> Output
Tdata Logic Delay
14
Timing in Digital Logic
• Clock arrival time
15
Timing in Digital Logic
• Data required time (setup): latch edge
16
Timing in Digital Logic
• Data required time (hold): next launch = latch
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Timing in Digital Logic
• Setup slack
18
Timing in Digital Logic
• Hold slack
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Static Timing Analysis
• Timing Model and Timing Constraint • Arrival Time (AT) and Required Time (RT)
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Outline
Sequential Circuits Timing Analysis Memory
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Static RAM
• Applications – CPU register file, cache, embedded memory, DSP
• Characteristics – 6 transistor per cell, other topologies – no need to refresh – access time ~ cycle time – no charge to leak – faster, more area, more expensive
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SRAM Operation
• Standby – word line de-asserted
• Read – precharge bit lines – assert WL – BL rise/drop slightly
• Write – apply value to BL – assert WL – input drivers stronger
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SRAM Architecture
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source: semiengineering.com
Multi-Bank Layout
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source: semiengineering.com
Questions?
Comments?
Discussion?
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Design Tool Tutorials
• Standard-cell based design flow
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Design Tool Tutorials
• Functional Simulation – tool: Synopsys VCS – simulate your HDL (eg. Verilog) code to verify
functionality
• Logic Synthesis – tool: Synopsys Design Compiler (DC) – convert/synthesize behavioral/RTL level HDL to gate-
level netlist (i.e. connectivity list)
• Physical Design (Place & Route) – tool: Cadence Encounter – given the gate-level netlist, place and route the design
to complete an IC chip in its final physical form
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Acknowledgement
Jan Rabaey, “Digital Integrated Circuits”, 2006 Cornell University, ECE 5745
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