Lecture 18
ANNOUNCEMENTS• HW#10 will be posted tonight
OUTLINE
• HW#10 will be posted tonight
OUTLINE• Basic MOSFET amplifierMOSFET bi i• MOSFET biasing
• MOSFET current sourcesC lifi• Common‐source amplifier
EE105 Fall 2007 Lecture 18, Slide 1 Prof. Liu, UC Berkeley
Reading: Chapter 7.1‐7.2
Basic MOSFET Amplifier
• For large small‐signal gain, the MOSFET should be operated in the saturation region.
EE105 Fall 2007 Lecture 18, Slide 2 Prof. Liu, UC Berkeley
Vout should not fall below Vin by more than VTH.
MOSFET BiasingThe voltage at node X is determined by VDD, R1, and R2:Also
DDX VRR
RV21
2
+=
RIVV +=Also, SDGSX RIVV +=
( )21THGSoxnD VVWCI −= µ
( ) THDD
THGS VRR
VRVVVVV 2 21
211 ⎟
⎠
⎞⎜⎜⎝
⎛−
+++−−=⇒
( )2 THGSoxnD VV
LCµ
SRWCV
RR
µ
1 where 1
21
=
⎠⎜⎝ +
EE105 Fall 2007 Lecture 18, Slide 3 Prof. Liu, UC Berkeley
Soxn RL
Cµ
Self‐Biased MOSFET Stage• Note that there is no voltage dropped across RG
M1 is operating in the saturation region.M1 is operating in the saturation region.
DDDSGSDD VIRVRI =++
EE105 Fall 2007 Lecture 18, Slide 4 Prof. Liu, UC Berkeley
MOSFETs as Current Sources• A MOSFET behaves as a current source when it is operating in
the saturation region.g• An NMOSFET draws current from a point to ground (“sinks
current”), whereas a PMOSFET draws current from VDD to a point (“sources current”)point ( sources current ).
EE105 Fall 2007 Lecture 18, Slide 5 Prof. Liu, UC Berkeley
Common‐Source Stage: λ = 0Amplifier circuit Small-signal analysis circuit
for determining voltage gain, Av
RIWCRgA == µ2
Small-signal analysis circuit fordetermining output resistance, Rout
in
DDoxnDmv
R
RIL
CRgA
∞=
−=−= µ2
EE105 Fall 2007 Lecture 18, Slide 6 Prof. Liu, UC Berkeley
Dout RR =
Common‐Source Stage: λ ≠ 0• Channel‐length modulation results in reduced small‐signal
voltage gain and amplifier output resistance.g g p p
Small-signal analysis circuitfor determining voltage gain, Av
Small-signal analysis circuit fordetermining output resistance, Rout
( )||( )in
ODmv
RrRgA
||
||∞=−=
EE105 Fall 2007 Lecture 18, Slide 7 Prof. Liu, UC Berkeley
ODout rRR ||=
CS Gain Variation with L• An ideal current source has infinite small‐signal resistance.The largest Av is achieved with a current source as the load. g v
√• Since λ is inversely proportional to L, Av increases with √L.
Doxn WLCILWC µµ 22
EE105 Fall 2007 Lecture 18, Slide 8 Prof. Liu, UC Berkeley
D
oxn
Domv I
WLCI
LrgA µλ
2∝==
CS Stage with Current‐Source Load• Recall that a PMOSFET can be used as a current source from VDD.
Use a PMOSFET as a load of an NMOSFET CS amplifier.Use a PMOSFET as a load of an NMOSFET CS amplifier.
( )211
|||| OOmv
rrRrrgA
=−=
EE105 Fall 2007 Lecture 18, Slide 9 Prof. Liu, UC Berkeley
21 || OOout rrR =
PMOS CS Stage with NMOS Load • An NMOSFET can be used as the load for a PMOSFET CS amplifier.
212 )||( OOmv rrgA −=
21
212
|| OOout
OOmv
rrR =
EE105 Fall 2007 Lecture 18, Slide 10 Prof. Liu, UC Berkeley
CS Stage with Diode‐Connected LoadAmplifier circuit Small-signal analysis circuit
including MOSFET output resistances
:0≠λ
( )1/1
:0 If
LWA
=λ12
21 ||||1
OOm
mv rrg
gA ⎟⎟⎠
⎞⎜⎜⎝
⎛−=
A i l b t it i l d d t t
( )( )2
1
21 /LWg
gAm
mv −=⋅−=12
2
||||1OO
mout rr
gR =
EE105 Fall 2007 Lecture 18, Slide 11 Prof. Liu, UC Berkeley
Av is lower, but it is less dependent on process parameters (µn and Cox and drain current (ID).
CS Stage with Diode‐Connected PMOS Load
1 ⎞⎜⎛
:0≠λ
211
2
1
||||1oo
mmv rr
ggA ⎟
⎠
⎞⎜⎜⎝
⎛−=
211
||||1oo
mout rr
gR =
EE105 Fall 2007 Lecture 18, Slide 12 Prof. Liu, UC Berkeley
CS Stage with DegenerationAmplifier circuit Small-signal analysis circuit
for determining voltage gain, Av
S
Dv
Rg
RA+
−== 1 :0 If λ
EE105 Fall 2007 Lecture 18, Slide 13 Prof. Liu, UC Berkeley
mg
Example• A diode‐connected device degenerates a CS stage.
11D
v
gg
RA+
−=
EE105 Fall 2007 Lecture 18, Slide 14 Prof. Liu, UC Berkeley
21 mm gg
Rout of CS Stage with Degeneration• Degeneration boosts the output impedance:
Small-signal analysis circuit fordetermining output resistance, Rout
Current flowing down through r isCurrent flowing down through ro is
( )SXmX
SXmXmX
RigiRigivgi
+=−−=−
1
( )SX Riv −=1
SXmX g
( )
( )X
XSXSXmXO
RrgrRRgrvvRiRigir
+≅++
=++
1
EE105 Fall 2007 Lecture 18, Slide 15 Prof. Liu, UC Berkeley
( ) SOmOSSmOX
X RrgrRRgri
+≅++= 1
Output Impedance Examples
⎞⎛ 1⎟⎟⎠
⎞⎜⎜⎝
⎛+≅
211
11m
mOout ggrR 1211 OOOmout rrrgR +≈
EE105 Fall 2007 Lecture 18, Slide 16 Prof. Liu, UC Berkeley
CS Stage with Gate Resistance• For low signal frequencies, the gate conducts no current.
Gate resistance does not affect the gain or I/O impedancesGate resistance does not affect the gain or I/O impedances.
EE105 Fall 2007 Lecture 18, Slide 17 Prof. Liu, UC Berkeley
CS Core with Biasing
Dv
RRRR
RRA −⋅
+= 1||
|| 21Dmv Rg
RRRRRA 21
||||
−=S
m
G Rg
RRR ++ 1|| 21Dm
Gv g
RRR 21 ||+
EE105 Fall 2007 Lecture 18, Slide 18 Prof. Liu, UC Berkeley