Isolated, Half Bridge Gate Driver with Adjustable Dead Time, 4 A Output
Data Sheet ADuM4221
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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FEATURES 4 A peak current (<2 Ω RDSON_x) 2.5 V to 6.5 V logic input voltage 4.5 V to 35 V output supply voltage UVLO VDD1 positive going threshold: 2.5 V maximum Multiple UVLO options for VDDA and VDDB positive going
threshold Grade A: 4.5 V maximum Grade B: 7.5 V maximum Grade C: 11.6 V maximum
Precise timing characteristics 44 ns maximum propagation delay
Adjustable dead time CMOS input logic levels High common-mode transient immunity: 150 kV/µs High junction temperature operation: 125°C Default low output Safety and regulatory approvals (pending)
UL recognition per UL 1577 5700 V rms for 1 minute duration
CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending)
DIN V VDE V 0884-11 VIORM = 849 V peak
Increased creepage wide body, 16-lead SOIC_IC
APPLICATIONS Switching power supplies Isolated IGBT/MOSFET gate drives Industrial inverters Gallium nitride (GaN)/silicon carbide (SiC) compatible
FUNCTIONAL BLOCK DIAGRAM
1721
9-00
1
UVLO TSD
ENCODE
ADuM4221
CONTROLLOGIC
UVLO
DISABLE
DT
NC
VDD1
GND1
VDD1
VIB
VIA
5
6
7
8
4
3
2
1
NC = NO CONNECT
12
11
13
14
15
NC
VDDB
VOB
GNDB
NC
GNDA
VOA
VDDA
10
16
9
UVLO TSD
ENCODE
DECODEAND
LOGIC
DECODEAND
LOGIC
Figure 1.
GENERAL DESCRIPTION The ADuM4221 is a 4 A isolated, half bridge gate driver that employs the Analog Devices, Inc., iCoupler® technology to provide independent and isolated high-side and low-side outputs. The ADuM4221 provides 5700 V rms isolation in the increased creepage wide body, 16-lead SOIC_IC package. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to the alternatives, such as the combination of pulse transformers and gate drivers.
The isolators operate with a logic input voltage ranging from 2.5 V to 6.5 V, providing compatibility with lower voltage systems. In comparison to gate drivers employing high voltage level translation methodologies, the ADuM4221 offers the benefit of true, galvanic isolation between the input and each output.
The ADuM4221 has a built in overlap protection and allows for dead time adjustment. A single resistor between the dead time pin (DT) and the GND1 pin sets the dead time on the secondary side between the high-side and the low-side outputs.
An internal thermal shutdown (TSD) sets outputs low if the internal temperature on the ADuM4221 exceeds the TSD temperature. As a result, the ADuM4221 provides reliable control over the switching characteristics of the insulated gate bipolar transistor (IGBT)/metal-oxide semiconductor field effect transistor (MOSFET) configurations over a wide range of positive or negative switching voltages.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending.
ADuM4221 Data Sheet
Rev. 0 | Page 2 of 19
TABLE OF CONTENTS Features .............................................................................................. 1 Applications ...................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications .................................................................................... 3
Electrical Characteristics ............................................................. 3 Package Characteristics ............................................................... 4 Regulatory Information ............................................................... 5 Insulation and Safety Related Specifications ............................ 5 DIN V VDE V 0884-11 (VDE V 0884-11) Insulation Characteristics .............................................................................. 6 Recommended Operating Conditions ...................................... 6
Absolute Maximum Ratings ........................................................... 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions ............................ 8
Typical Performance Characteristics .............................................9 Theory of Operation ...................................................................... 13 Applications Information ............................................................. 14
PCB Layout ................................................................................. 14 Propagation Delay-Related Parameters .................................. 14 Peak Current Rating .................................................................. 14 Protection Features .................................................................... 14 Output Load Characteristics .................................................... 14 Adjustable Dead Time Control ................................................ 15 Boot Strapped, Half Bridge Operation .................................... 16 Power Dissipation ...................................................................... 17 DC Correctness and Magnetic Field Immunity .................... 17 Insulation Lifetime ..................................................................... 18
Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY 7/2020—Revision 0: Initial Version
Data Sheet ADuM4221
Rev. 0 | Page 3 of 19
SPECIFICATIONS ELECTRICAL CHARACTERISTICS Low-side voltages referenced to GND1, high-side voltages referenced to GNDA, GNDB, 2.5 V ≤ VDD1 ≤ 6.5 V, 4.5 V ≤ VDDA,VDDB ≤ 35 V, and TJ = −40°C to +125°C, unless otherwise noted. All minimum and maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TJ = 25°C, VDD1 = 5.0 V, and VDDA and VDDB = 15 V.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Logic Input Voltage VDD1 2.5 6.5 V Output Supply Voltage VDDA, VDDB 4.5 35 V Input Supply Current, Quiescent IDD1 (Q)
Input A High or Input B High 7.2 10 mA Both Inputs Low 1.4 2.4 mA
Output Supply Current, Per Channel, Quiescent
IDD2 (Q)
Output Channel High 1.4 2.6 mA Low 1.6 2.1 mA
Input Currents IIA, IIB −1 +0.01 +1 µA Input Voltage
Input Threshold Logic High VIH 0.7 × VDD1 V 2.5 V ≤ VDD1 ≤ 5 V 3.5 V VDD1 > 5 V Logic Low VIL 0.3 × VDD1 V 2.5 V ≤ VDD1 ≤ 5 V
1.5 V VDD1 > 5 V Undervoltage Lockout (UVLO)
VDD1 Positive Going Threshold VVDD1UV+ 2.45 2.5 V VDD1 Negative Going Threshold VVDD1UV− 2.3 2.35 V VDD1 Hysteresis VVDD1UVH 0.1 V VDDA and VDDB Positive Going Threshold VVDDAUV+,
VVDDBUV+ 4.4 4.5 V Grade A
7.3 7.5 V Grade B 11.3 11.6 V Grade C VDDA and VDDB Negative Going Threshold VVDDAUV−,
VVDDBUV−
4.1 4.2 V Grade A 6.9 7.1 V Grade B 10.8 11.1 V Grade C VDDA and VDDB Hysteresis VVDDAUVH,
VVDDBUVH
0.2 V Grade A 0.2 V Grade B 0.2 V Grade C
TSD Positive Edge TTSD_POS 155 °C Hysteresis TTSD_HYST 30 °C
Drive Strength Pull-Down Negative Metal Oxide
Semiconductor (NMOS) On Resistance RDSON_N 0.6 1.6 Ω Tested at 250 mA, VDDx = 15 V
0.6 1.6 Ω Tested at 1 A, VDDx = 15 V Pull-Up Positive Metal Oxide
Semiconductor (PMOS) On Resistance RDSON_P 0.8 1.8 Ω Tested at 250 mA, VDDx = 15 V
0.8 1.8 Ω Tested at 1 A, VDDx = 15 V Peak Current IPEAK 4 A VDDA,VDDB = 15 V, 2 Ω gate resistance
ADuM4221 Data Sheet
Rev. 0 | Page 4 of 19
Parameter Symbol Min Typ Max Unit Test Conditions SWITCHING SPECIFICATIONS
Pulse Width 50 ns Load capacitance (CL) = 2.2 nF, VDD1 = 5 V, VDDA and VDDB = 15 V, external gate resistor (RG) = 5.1 Ω
Propagation Delay1 CL = 2.2 nF, VDD1 = 5 V, VDDA and VDDB = 15 V, and RG = 5.1Ω Rising Edge tDLH 19 25 33 ns
Falling Edge tDHL 21 30 44 ns Time to Disable tDIS 21 25 44 ns Time to Enable tEN 19 25 33 ns
Delay Skew2 tPSK 22 ns CL = 2.2 nF, RG = 5.1 Ω Pulse Width Distortion tPWD 5 16 ns CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω Channel to Channel Matching3 tPSKCD 1.5 10 ns CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, see Figure 19 Output Rise and Fall Time (10% to 90%) tR/tF 14 25 34 ns CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω, see Figure 26 Adjustable Dead Time DT CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω 1809 2320 2831 ns Dead time resistor (RDT) = 500 kΩ 742 938 1135 ns RDT = 200 kΩ 48 62 76 ns RDT = 10 kΩ
1 tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 26 for the waveforms of the propagation delay parameters.
2 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 26 for the waveforms of the propagation delay parameters.
3 Channel to channel matching is the absolute value of the difference in propagation delays between two channels on a single device.
PACKAGE CHARACTERISTICS
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments Resistance (Input to Output)1 RI-O 1013 Ω Capacitance (Input to Output)1 CI-O 2.2 pF f = 1 MHz Input Capacitance2 CI 4.0 pF IC Junction to Ambient Thermal Resistance θJA 45 °C/W Thermocouple located at center of package underside 1 The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground.
Data Sheet ADuM4221
Rev. 0 | Page 5 of 19
REGULATORY INFORMATION The ADuM4221 is pending approval by the organizations listed in Table 3.
Table 3. UL (Pending) CSA (Pending) VDE (Pending) CQC (Pending) Recognized Under 1577 Component
Recognition Program1 Approved under CSA Component Acceptance Notice 5A
Certified according to DIN VDE V 0884-11 (VDE V 0884-11):2017-012
Certified by CQC11-471543-2012
Single Protection, 5700 V rms Isolation Voltage
IEC 62368, Third Edition Basic insulation, 900 V peak, VIOSM = 9850 V peak
GB4943.1-2011
Basic insulation at 830 V rms (1173 V peak)
Reinforced insulation, 849 V peak, VIOSM = 8000 V peak
Basic insulation at 800 V rms (1131 V peak)
Reinforced insulation at 415 V rms (586 V peak)
Reinforced insulation at 400 V rms (565 V peak)
IEC 60601-1, Edition 3.1 Reinforced insulation (2 MOPP),
250 V rms (353V peak)
CSA 61010-1-12 and IEC 61010-1, Third Edition
Basic insulation at 300 V rms mains, 800 V secondary (1089 V peak)
Reinforced insulation at 300 V rms mains, 400 V secondary (565 V peak)
File E214100 File 205078 File 2471900-4880-0003 File (pending) 1 In accordance with UL 1577, each ADuM4221 is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec. 2 In accordance with DIN VDE V 0884-11, each ADuM4221 is proof tested by applying an insulation test voltage ≥ 1592 V peak for 1 sec (partial discharge detection limit =
5 pC). The * marking branded on the component designates DIN VDE V 0884-11 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4. Parameter Symbol Value Unit Test Conditions/Comments Rated Dielectric Insulation Voltage 5700 V rms 1-minute duration Minimum External Air Gap (Clearance) L (I01) 8.3 mm Measured from input terminals to output
terminals, shortest distance through air Minimum External Tracking (Creepage) L (I02) 8.3 mm Measured from input terminals to output
terminals, shortest distance path along body Minimum Clearance in the Plane of the Printed Circuit
Board, PCB (PCB Clearance) L (PCB) 8.3 mm Measured from input terminals to output
terminals, shortest distance through air, line of sight, in the PCB mounting plane
Minimum Internal Gap (Internal Clearance) 25.5 μm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >600 V DIN IEC 112/VDE 0303 Part 1 Material Group I Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM4221 Data Sheet
Rev. 0 | Page 6 of 19
DIN V VDE V 0884-11 (VDE V 0884-11) INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation only within the safety limit data. Protective circuits ensure maintenance of the safety data.
Table 5. VDE Characteristics Description Test Conditions/Comments Symbol Characteristic Unit Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV For Rated Mains Voltage ≤ 300 V rms I to IV For Rated Mains Voltage ≤ 600 V rms I to IV
Climatic Classification 40/105/21 Pollution Degree per DIN VDE 0110, Table 1 2 Maximum Repetitive Peak Isolation Voltage VIORM 849 V peak Input to Output Test Voltage, Method B1 VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC Vpd (m) 1592 V peak
Input to Output Test Voltage, Method A Vpd (m) After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1274 V peak
After Input and/or Safety Test Subgroup 2 and Subgroup 3
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC
1019 V peak
Maximum Rated Transient Isolation Voltage VIOTM 8000 V peak Surge Isolation Voltage VIOSM
Basic V peak = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time
9850 V peak
Reinforced V peak = 12.8 kV, 1.2 µs rise time, 50 µs, 50% fall time
8000 V peak
Safety Limiting Values Maximum value allowed in the event of a failure (see Figure 2)
Maximum Junction Temperature TS 150 °C Total Power Dissipation at 25°C PS 2.77 W Insulation Resistance at TS VIO = 500 V RS >109 Ω
3.0
2.5
2.0
1.5
1.0
0.5
00 50 100 150 200
SAFE
OPE
RATI
NG P
VDD1
, PVD
DA,
OR
P VDD
B P
OW
ER (W
)
AMBIENT TEMPERATURE (°C) 1721
9-00
2
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN V VDE V 0884-11
RECOMMENDED OPERATING CONDITIONS
Table 6. Parameter Value TJ −40°C to +125°C Supply Voltages
VDD11 2.5 V to 6.5 V
VDDA and VDDB2 4.5 V to 35 V
Common-Mode Transient Immunity Static3 −150 kV/µs to +150 kV/µs Dynamic4 −150 kV/µs to +150 kV/µs
Dead Time Resistor Range 10 kΩ to 500 kΩ
1 Referenced to GND1. 2 Referenced to GNDA,GNDB. 3 Static common-mode transient immunity is defined as the largest dv/dt
between GND1 and GNDA and GNDB with the inputs held either high or low such that the output voltage remains either above 0.8 × VDDA and VDDB for output high or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets.
4 Dynamic common-mode transient immunity is defined as the largest dv/dt between GND1 and GNDA and GNDB with the switching edge coincident with the transient test pulse. Operation with transients above recommended levels can cause momentary data upsets.
Data Sheet ADuM4221
Rev. 0 | Page 7 of 19
ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.
Table 7. Parameter Rating Voltage Ranges
Supply VDD1 −0.2 V to +7 V VDDA and VDDB −0.3 V to +40 V
Input1 (VIA, VIB, and DISABLE) −0.3 V to +7 V Output2
VOA −0.3 V to VDDA + 0.3 V VOB −0.3 V to VDDB + 0.3 V VOA Transient for 200 ns −2 V to VDDA + 0.3 V VOB Transient for 200 ns −2 V to VDDB + 0.3 V
Temperature Range Storage (TST) −55°C to +150°C TJ −40°C to +125°C
Common-Mode Transients3 (CMH, CML) −200 kV/µs to +200 kV/µs
1 Rating assumes VDD1 is above 2.5 V. VIA and VIB are rated up to 6.5 V when VDD1 is unpowered.
2 Referenced to GND2, maximum of 40 V. 3 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum rating can cause latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL RESISTANCE Thermal performance is directly linked to the PCB design and operating environment. Careful attention to PCB thermal design is required.
θJA is the junction to ambient thermal resistance, and ΨJT is the junction to top characterization parameter.
Table 8. Thermal Resistance Package Type1 θJA ΨJT Unit RI-16-2 45 16.67 °C/W
1 4-layer PCB.
ESD CAUTION
Table 9. Maximum Continuous Working Voltage1
Parameter Rating Unit Constraint AC Voltage
Bipolar Waveform
Basic Insulation 900 V peak 20 year minimum insulation lifetime per VDE-0884-11 Reinforced Insulation 849 V peak 20 year minimum insulation lifetime per VDE-0884-11
DC Voltage
Basic Insulation 1660 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60664-1, Pollution Degree 2, Material Group I
Reinforced Insulation 830 V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60664-1, Pollution Degree 2, Material Group I
1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
ADuM4221 Data Sheet
Rev. 0 | Page 8 of 19
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES1. NC = NO CONNECT.
DO NOT CONNECT TO THESE PINS.
VIA 1VIB 2
VDD1 3GND1 4
VDDA16VOA15GNDA14NC13
DISABLE 5 NC12DT 6 VDDB11NC 7 VOB10
VDD1 8 GNDB9
ADuM4221TOP VIEW
(Not to Scale)
1721
9-00
3
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions Pin No.1 Mnemonic Description 1 VIA Logic Input A. 2 VIB Logic Input B. 3, 8 VDD1 Input Supply Voltage. 4 GND1 Ground Reference for Input Logic Signals. 5 DISABLE Input Disable. The DISABLE pin disables the isolator inputs and refresh circuits. 6 DT Dead Time Control Input. The resistor connected from the DT pin to ground sets the dead time between the
output transitions. 7, 12, 13 NC No Connect. Do not connect to these pins. 9 GNDB Ground Reference for Output B. 10 VOB Output B. 11 VDDB Output B Supply Voltage. 14 GNDA Ground Reference for Output A. 15 VOA Output A. 16 VDDA Output A Supply Voltage.
1 Pin 3 and Pin 8 are internally connected. Connecting both the VDD1 pins to the VDD1 input supply is recommended.
Table 11. Truth Table (Positive Logic with Dead Time) DISABLE1 VIA Input1 VIB Input1 VDD1 State VDDA and VDDB State VOA Output VOB Output Notes Low Low Low Powered Powered Low Low Output transition begins
after dead time expires Low Low High Powered Powered Low High Output transition begins
after dead time expires Low High Low Powered Powered High Low Output transition begins
after dead time expires Low High High Powered Powered Low Low Output transition begins
after dead time expires High X X Powered Powered Low Low Device is disabled X X X Unpowered Powered Low Low Output returns to input state
after VDD1 power restoration X X X Powered Unpowered Low Low Output remains low
1 X means don’t care.
Data Sheet ADuM4221
Rev. 0 | Page 9 of 19
TYPICAL PERFORMANCE CHARACTERISTICS
CH1 2.00V M40.0ns A CH1 2.04VT 159.800nsCH3 5.00V
3
1
VOx
VIx
1721
9-00
4
Figure 4. Output Waveform for 2 nF Load and 3.9 Ω Series Gate Resistor with 15 V Output Supply
CH1 2.00V M40.0ns A CH1 2.04VT 159.800nsCH3 5.00V
3
1
VOx
VIx
1721
9-00
5
Figure 5. Output Waveform for 2 nF Load and 0 Ω Series Gate Resistor with 15 V Output Supply
3, 4
CH1 2.00V CH2 2.00V M400ns A CH1 2.84VT 0.0000sCH3 5.00V
3 4
CH4 5.00VVALUE252.1ns252.9ns
MEAN163.8n165.4n
MIN–37.90n–22.80n
MAX252.1n254.0n
STD DEV120.6n121.5n
1, 2
34
VIB
VOB
VIA
VOA
1721
9-00
6
Figure 6. Dead Time Operation Between Input and Output with 50 kΩ
Dead Time Resistor
4
2
3
CH1 2.00V CH2 2.00V M2.00µs A CH1 2.84VT 16.0000µsCH3 5.00V
3 43 4
CH4 5.00VVALUE962.2ns34.27ns
MEAN961.6n34.21n
MIN961.6n34.15n
MAX962.2n34.27n
STD DEV353.6p82.50p
1
VIB
VIA
VOB
VOA
1721
9-00
7
Figure 7. Dead Time Operation Between Input and Output with 200 kΩ Dead Time Resistor and One Input Held High
4
M400µs A CH4 5.50VT 4.00000µsCH3 2.00V
3 4
CH4 5.00VVALUE14.33µs
MEAN14.33µ
MIN14.33µ
MAX14.33µ
STD DEV0.000
3
VDD1
VOx
1721
9-00
8
Figure 8. Typical VDD1 Delay to Output Waveform, VIx = VDD1
4
M400µs A CH4 5.50VT 4.00000µsCH3 5.00V
3 4
CH4 5.00VVALUE13.84µs
MEAN13.84µ
MIN13.84µ
MAX13.84µ
STD DEV0.000
3
VDD2
VOx
1721
9-00
9
Figure 9. Typical VDD2 Delay to Output Waveform, VIx = VDD1 (VDD2 Refers to VDDA or VDDB)
ADuM4221 Data Sheet
Rev. 0 | Page 10 of 19
I DD1
(mA)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 100 200 300 400 500 600 700 800 900 1000FREQUENCY (kHz)
VDD1 = 3.3VVDD1 = 5V
1721
9-01
0
Figure 10. VDD1 Current (IDD1) vs. Frequency for VDD1 = 3.3 V and VDD1 = 5 V,
50% Duty Cycle
0
5
10
15
20
25
30
35
40
0 100 200 300 400 500 600 700 800 900 1000
I DD2
(mA)
FREQUENCY (kHz)
VDD2 = 5VVDD2 = 10VVDD2 = 15V
1721
9-01
1
Figure 11. VDD2 Current (IDD2) vs. Frequency for VDD2 = 5 V, VDD2 = 10 V, and
VDD2 = 15 V, 50% Duty Cycle, 2 nF Load (VDD2 Refers to VDDA or VDDB)
I DD1
(mA)
0
1
2
3
4
5
6
7
8
9
10
0 10 20 30 40 50 60 70 80 90 100DUTY CYCLE (%)
VDD1 = 2.5VVDD1 = 5V
1721
9-01
2
Figure 12. IDD1 vs. Duty Cycle for VDD1 = 2.5 V and VDD1 = 5 V,
VDD2 = 15 V (VDD2 Refers to VDDA or VDDB)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 10 20 30 40 50 60 70 80 90 100
I DD2
(mA)
DUTY CYCLE (%)
VDD2 = 5VVDD2 = 10VVDD2 = 15V
1721
9-01
3
Figure 13. IDD2 vs. Duty Cycle for VDD2 = 5 V, VDD2 = 10 V, and VDD2 = 15 V,
VDD1 = 5 V (VDD2 Refers to VDDA or VDDB)
TEMPERATURE (°C)
0
5
10
15
20
25
30
–40 –20 0 20 40 60 80 100 120
RISE
AND
FALL
TIM
E (n
s)
RISE TIMEFALL TIME
1721
9-01
4
Figure 14. Rise and Fall Time vs. Temperature with a 3.9 Ω Series Gate
Resistor for a 2 nF Load and a 15 V Output Supply
0
5
10
15
20
25
30
5 10 15 20 25 30 35
RISE
AND
FALL
TIM
E (n
s)
OUTPUT SUPPLY VOLTAGE (V)
RISE TIMEFALL TIME
1721
9-01
5
Figure 15. Rise and Fall Time vs. Output Supply Voltage with a 3.9 Ω Series
Gate Resistor for a 2 nF Load
Data Sheet ADuM4221
Rev. 0 | Page 11 of 19
TEMPERATURE (°C)
0
5
10
15
20
25
30
35
40
–40 –20 0 20 40 60 80 100 120
PRO
PAG
ATIO
N DE
LAY
(ns)
RISINGFALLING
1721
9-01
6
Figure 16. Propagation Delay vs. Temperature
0
5
10
15
20
25
30
35
40
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
PRO
PAG
ATIO
N DE
LAY
(ns)
INPUT SUPPLY VOLTAGE (V)
RISINGFALLING
1721
9-01
7
Figure 17. Propagation Delay vs. Input Supply Voltage, Rising and Falling,
VDD2 = 15 V (VDD2 Refers to VDDA or VDDB)
0
5
10
15
20
25
30
35
40
4 8 12 16 20 24 28 32 36
PRO
PAG
ATIO
N DE
LAY
(ns)
OUTPUT SUPPLY VOLTAGE (V)
RISINGFALLING
1721
9-01
8
Figure 18. Propagation Delay vs. Output Supply Voltage, Rising and
Falling, VDD1 = 5 V
0
3
6
9
12
15
4 8 12 16 20 24 28 32 36
CHAN
NEL
TO C
HANN
EL M
ATCH
ING
(ns)
OUTPUT SUPPLY VOLTAGE (V)
CHANNEL TO CHANNEL RISINGCHANNEL TO CHANNEL FALLING
1721
9-01
9
Figure 19. Channel to Channel Matching vs. Output Supply Voltage,
Rising and Falling
0
3
6
9
12
15
–40 –20 0 20 40 60 80 100 120
CHAN
NEL
TO C
HANN
EL M
ATCH
ING
(ns)
TEMPERATURE (°C)
CHANNEL TO CHANNEL RISINGCHANNEL TO CHANNEL FALLING
1721
9-12
0
Figure 20. Channel to Channel Matching vs. Temperature, Rising and
Falling, VDD2 = 15 V (VDD2 Refers to VDDA or VDDB)
0
1
2
3
4
5
6
7
8
0 5 10 15 20 25 30 35 40
PEAK
OUT
PUT
CURR
ENT
(A)
OUTPUT SUPPLY VOLTAGE (V)
SOURCE CURRENTSINK CURRENT
1721
9-12
1
Figure 21. Peak Output Current vs. Output Supply Voltage with a 2.2 Ω
Series Gain Resistor
ADuM4221 Data Sheet
Rev. 0 | Page 12 of 19
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
4 8 12 16 20 24 28 32 36
R DS(
ON)
(Ω)
OUTPUT SUPPLY VOLTAGE (V)
NMOSPMOS
1721
9-12
2
Figure 22. Output Resistance (RDS(ON)) vs. Output Supply Voltage for
NMOS and PMOS, VDD1 = 5 V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
–40 –20 0 20 40 60 80 100 120
RDS
(ON)
(Ω)
TEMPERATURE (°C)
NMOSPMOS
1721
9-12
3
Figure 23. RDS(ON) vs. Temperature for NMOS and PMOS
Data Sheet ADuM4221
Rev. 0 | Page 13 of 19
THEORY OF OPERATION Gate drivers are required where fast rise times of switching device gates are desired. The gate signal for most enhancement type power devices is referred to a source or emitter node. The gate driver must have the ability to follow this source or emitter node, necessitating isolation between the controlling signal and the output of the gate driver in topologies where the source or emitter nodes swing, such as a half bridge. Gate switching times are a function of the drive strength of the gate driver. Buffer stages before a CMOS output reduce the total delay time and increase the final drive strength of the driver.
The ADuM4221 achieves isolation between the control side and output side of the gate driver by means of a high frequency carrier that transmits data across the isolation barrier using iCoupler chip scale transformer coils separated by layers of polyimide isolation.
The encoding scheme used by the ADuM4221 is a positive logic on/off keying (OOK), a high signal transmitted by the presence of the carrier frequency across the iCoupler chip scale transformer coils. Positive logic encoding ensures that a low signal is seen on the output when the input side of the gate driver is unpowered. A low state is the most common safe state in enhancement mode power devices, driving in situations where shoot through conditions can exist. The architecture is designed for high common-mode transient immunity and high immunity to electrical noise and magnetic interference. Radiated emissions are minimized with a spread spectrum OOK carrier and other techniques such as differential coil layout. Figure 24 illustrates the encoding used by the ADuM4221.
TRANSMITTER
GND1 GND2
VIN VOUT
RECEIVER
REGULATOR REGULATOR
1721
9-02
0
Figure 24. Operational Block Diagram of OOK Encoding (VIN Is the Input Voltage, and VOUT Is the Output Voltage.)
ADuM4221 Data Sheet
Rev. 0 | Page 14 of 19
APPLICATIONS INFORMATION PCB LAYOUT The ADuM4221 requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins, as shown in Figure 25. Use a small ceramic capacitor with a value between 0.01 μF and 0.1 μF to provide a good high frequency bypass. On the output power supply pin, VDDA or VDDB, it is also recommended to add a 10 μF capacitor to provide the charge required to drive the gate capacitance at the ADuM4221 outputs. On the output supply pin, avoid the use of vias with a bypass capacitor or use multiple vias to reduce the inductance in the bypassing. The total lead length between both ends of the smaller capacitor and the input or output power supply pin must be as short as possible.
VIA VDDA
VIB VOA
GNDA
NC
NC
NC VDDB
NC VOB
GNDB
VDD1
GND1
DISABLE
VDD1
DT
17219-021
Figure 25. Recommended PCB Layout
PROPAGATION DELAY-RELATED PARAMETERS Propagation delay parameter describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output. The ADuM4221 specifies the rising edge propagation delay (tDLH) as the time between the rising input high logic threshold (VIH) to the output rising (tR) 10% threshold (see Figure 26). Likewise, the falling edge propagation delay (tDHL) is the time between the input falling logic low threshold (VIL) and the output falling (tF) 90% threshold. The rise and fall times are dependent on the loading conditions and are not included in the propagation delay, which is the industry standard for gate drivers.
OUTPUT
INPUT
tDLH
tR
90%
10%
VIH
VIL
tF
tDHL
17219-022
Figure 26. Propagation Delay Parameters
Channel to channel matching is the maximum amount that the propagation delay differs between channels within a single component.
Propagation delay skew is the maximum amount that the propagation delay differs between multiple components operating under the same conditions.
PEAK CURRENT RATING The ADuM4221 has two output channels, and each channel connects to the gate of the power device through an external series gate resistor. The output driver MOSFETs of the gate driver IC can source or sink more than 6 A (per VOA and VOB). In a practical application, to control the drive strength and to spread the power dissipation of driving the gate to outside of the gate driver IC, standard external series gate resistors are used. The output current of the gate driver is shown in Figure 21 of the Typical Performance Characteristics section.
PROTECTION FEATURES TSD
If the internal temperature of the ADuM4221 exceeds 155°C (typical), the device enters TSD. During the TSD time, the gate drive is disabled. When TSD occurs, the device does not leave TSD until the internal temperature drops below 125°C (typical), at which time, the device exits shutdown.
UVLO
The ADuM4221 has UVLO protections for both the primary and secondary side of the device. If either the primary or secondary side voltages are below the falling edge UVLO, the device outputs a low signal. After the ADuM4221 is powered above the rising edge UVLO threshold, the device outputs the signal found at the input. To account for small voltage source ripple, hysteresis is built into the UVLO. The primary side UVLO thresholds are common among all models.
OUTPUT LOAD CHARACTERISTICS The output signals depend on the characteristics of the output load, which is typically an N channel MOSFET. The driver output response to an N channel MOSFET load with a gate voltage (VGATE) can be modeled with a switch output resistance (RSW), an inductance due to the PCB trace (LTRACE), a series gate resistor (RGATE), and a gate to source capacitance (CGS), as shown in Figure 27.
ADuM4221VIA VOA
RSW RGATE
CGSLTRACE
VGATE
17219-023
Figure 27. Resistor, Inductor, and Capacitor (RLC) Model of the Gate of an
N Channel MOSFET
Data Sheet ADuM4221
Rev. 0 | Page 15 of 19
RSW is the switch resistance of the internal driver output, which is approximately 2 Ω. RGATE is the intrinsic gate resistance of the MOSFET and any external series resistance. A MOSFET that requires a 4 A gate driver has a typical intrinsic gate resistance of approximately 1 Ω and a CGS of between 2 nF and 10 nF. LTRACE is the inductance of the PCB trace, typically a value of 5 nH or less for a well designed layout with a short and wide connection from the ADuM4221 output to the gate of the MOSFET. The following equation defines the Q factor of the RLC circuit, which indicates how the output responds to a step change. For a well damped output, Q is less than 1.
1( )
TRACE
SW GATE GS
LQR R C
= ×+
Output ringing is reduced by adding a series gate resistance to dampen the response. The waveforms in Figure 4 show a correctly damped example with a 2 nF load and a 3.9 Ω external series gate resistor. The waveforms in Figure 5 show an underdamped example with a 2 nF load and a 0 Ω external series gate resistor.
ADJUSTABLE DEAD TIME CONTROL The ADuM4221 includes overlap protection such that the gate driver outputs (VOA and VOB) cannot simultaneously go high even if both inputs are high. Additionally, the ADuM4221 also has a dead time control pin (DT) that can adjust the delay between the output high-side and low-side transitions by using a single resistor
between the DT pin and ground (see Figure 30). The relation between RDT and the obtained dead time is shown in Figure 28.
2400
0 50 100 150 200 250 300 350 400 450 500
DEAD
TIM
E (n
s)
2100
1800
1500
1200
900
600
300
RDT (kΩ)
0
1721
9-12
4
Figure 28. Dead Time vs. Dead Time Resistor
Use the following equation, to calculate the required amount of dead time:
DT (ns) ≈ 5 × RDT (kΩ)
The VOx pin reacts to the VIx pin depending on the dead time value set by the RDT resistor. The DT pin controls the edge transitions between VOA and VOB. Dead time only affects the rising edge transition of the gate drive signal, and dead time operation is shown in Figure 29.
1721
9-02
9
VOA
90%
10%
VIB
VIH
VIL
VIA
VIH
VIL
VOB
90%
10%
DT DT
DT DT
Figure 29. Dead Time Operation for Different Input Transitions
ADuM4221 Data Sheet
Rev. 0 | Page 16 of 19
BOOT STRAPPED, HALF BRIDGE OPERATION The ADuM4221 is well suited for operating two output gate signals referenced to separate grounds, as in the case for a half bridge configuration. Because isolated auxiliary supplies are often expensive, it is beneficial to reduce the amount of supplies.
One method to reduce power supplies is to use a boot strapped configuration for the high-side supply of the ADuM4221. In this topology, the decoupling capacitor (CA) acts as the energy storage for the high-side supply and is filled whenever
the low-side switch is closed, bringing GNDA to GNDB (see Figure 30). During the CA charging time, control the dv/dt of the VDDA voltage to reduce the possibility of glitches on the output. To control the dv/dt of the VDDA voltage, introduce a series resistance (RBOOT) into the CA charging path.
Note that in Figure 30, DBOOT is the bootstrapped diode, CDD1 is the decoupling capacitor on the input side, and CB is the decoupling capacitor for the driver low-side supply.
ENCODE DECODE
ENCODE DECODE
DISABLE
DT
NC
VDD1
NC
VDDB
VOB
GNDB
5
6
7
8
12
11
GND1 NC4 13
VDD1 GNDA3 14
VIB VOA2 15
VIA VDDA1 16
10
9
NC = NO CONNECT
ADuM4221
CA
CB
VDDB
RBOOT
RGA
RGB
CDD1VDD1
VDD1
VDD1
VBUS
DBOOT
DELAY
RDT
1721
9-02
4
Figure 30. Circuit of Bootstrapped Half Bridge Operation
Data Sheet ADuM4221
Rev. 0 | Page 17 of 19
POWER DISSIPATION When driving a MOSFET or IGBT gate, the driver must dissipate power. This power is not insignificant and can lead to TSD if considerations are not made. The gate of an IGBT can be approximately simulated as a capacitive load. Due to Miller capacitance and other nonlinearities, it is common practice to take the stated input capacitance of a given MOSFET or IGBT, CISS, and multiply this capacitance by a factor of 3 to 5 to arrive at a conservative estimate of the approximate load being driven. With this value, the estimated total power dissipation in the system due to the switching action is given by
PDISS = CEST × (VDD2 − GND2)2 × fSW
where: CEST = CISS × 5. fSW is the switching frequency of the IGBT.
Alternately, use the gate charge as follows:
PDISS = QG × (VDD2 − GND2) × fSW
where QG is the total gate charge of the device being driven. This power dissipation is shared between the internal on resistances of the internal gate driver switches and the external gate resistances, RGON and RGOFF. The ratio of the internal gate resistances to the total series resistance allows the calculation of losses seen within the ADuM4221device.
PDISS_ADuM4221 = PDISS × 0.5(RDSON_P/(RGON + RDSON_P) + 0.5(RDSON_N/(RGOFF + RDSON_N))
Take the power dissipation found inside the chip and multiply it by θJA to see the rise above ambient temperature that the ADuM4221 experiences, then multiplied this value by two because there are two channels.
TADuM4221 = θJA × 2 × PDISS_ADuM4221 + TA
For the device to remain within specification, TADuM4221 must not exceed 125°C. If TADuM4221 exceeds the TSD rising edge, the device enters TSD, and the output remains low until the TSD falling edge is crossed.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY The ADuM4221 is resistant to external magnetic fields. The limitation on the ADuM4221 magnetic field immunity is set by the condition in which the induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which falsely sets or resets of the decoder can occur (see Figure 31 and Figure 32).
100
10
1
0.1
0.01
0.0011k 10k 100k 1M 10M 100M
MAX
IMUM
ALL
OW
ABLE
MAG
NETI
C FL
UXDE
NSIT
Y (k
gaus
s)
MAGNETIC FIELD FREQUENCY (Hz) 1721
9-02
6
Figure 31. Maximum Allowable External Magnetic Flux Density
1k
100
10
1
0.1
0.011k 10k 100k 1M 10M 100M
MAX
IMUM
ALL
OW
ABLE
CUR
RENT
(kA)
MAGNETIC FIELD FREQUENCY (Hz)
DISTANCE = 1m
DISTANCE = 100mm
DISTANCE = 5mm
1721
9-02
7
Figure 32. Maximum Allowable Current for Various Current to
ADuM4221 Spacings
ADuM4221 Data Sheet
Rev. 0 | Page 18 of 19
INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM4221.
Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage.
The values detailed in Table 9 summarize the peak voltage for 20 years of service life for a bipolar ac operating condition, and the maximum CSA and VDE approved working voltages. In many cases, the approved working voltage is higher than the 20 year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM4221 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 33, Figure 34, and Figure 35 illustrate these different isolation voltage waveforms.
A bipolar ac voltage environment is the worst condition for iCoupler products and is the 20 year operating lifetime that
Analog Devices recommends for the maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. Unipolar ac or dc voltage operation allows operation at higher working voltages while still achieving a 20 year service life. Any cross insulation voltage waveform that does not conform to Figure 34 or Figure 35 must be treated as a bipolar ac waveform, and its peak voltage must be limited to the 20 year lifetime voltage value listed in Table 9.
The voltage presented in Figure 34 is shown as sinusoidal for illustration purposes only. This voltage is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
0V
RATED PEAK VOLTAGE
1721
9-03
3
Figure 33. Bipolar AC Waveform
0V
RATED PEAK VOLTAGE
1721
9-03
4
Figure 34. Unipolar AC Waveform
0V
RATED PEAK VOLTAGE
1721
9-03
5
Figure 35. DC Waveform
Data Sheet ADuM4221
Rev. 0 | Page 19 of 19
OUTLINE DIMENSIONS
16 9
81
COPLANARITY0.10
1.27 BSC
12.9512.8012.65
7.607.507.40
2.642.502.36
1.270.41
2.442.24
0.250.10
10.5510.3010.05
0.490.35
8°0°
0.330.23
0.760.25 45°0.25 BSC
GAGEPLANE
COMPLIANT TO JEDEC STANDARDS MS-013-AC 12-1
3-20
17-B
PKG
-004
586
TOP VIEW
SIDE VIEW
END VIEW
PIN 1INDICATOR
SEATINGPLANE
Figure 36. 16-Lead Standard Small Outline Package with Increased Creepage [SOIC_IC]
(RI-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model1 Inputs Minimum Output Voltage (V)
Adjustable Dead Time
Temperature Range
Package Description
Package Option
Ordering Quantity
ADuM4221ARIZ VIA, VIB 4.5 Yes −40°C to +125°C 16-Lead SOIC_IC RI-16-2 1 ADuM4221ARIZ-RL VIA, VIB 4.5 Yes −40°C to +125°C 16-Lead SOIC_IC,
13” Tape and Reel RI-16-2 1,000
ADuM4221BRIZ VIA, VIB 7.5 Yes −40°C to +125°C 16-Lead SOIC_IC RI-16-2 1 ADuM4221BRIZ-RL VIA, VIB 7.5 Yes −40°C to +125°C 16-Lead SOIC_IC,
13” Tape and Reel RI-16-2 1,000
ADuM4221CRIZ VIA, VIB 11.6 Yes −40°C to +125°C 16-Lead SOIC_IC RI-16-2 1 ADuM4221CRIZ-RL VIA, VIB 11.6 Yes −40°C to +125°C 16-Lead SOIC_IC,
13” Tape and Reel RI-16-2 1,000
EVAL-ADuM4221EBZ Evaluation Board 1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D17219-7/20(0)