Download - Introduction to Programmable Logic John Coughlan RAL Technology Department Electronics Division
Introduction toProgrammable Logic
John Coughlan
RAL Technology Department
Electronics Division
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Data Transport
Triggering
Computers interacting with Hardware (VME Bus)
Silicon Trackers (Millions of Data Channels)
Programmable Logic is Key Underlying Technology.
Commercial Devices. Driven by Industry.
PPD Lectures
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
CMS
CERN LHC
Electronics “Counting” Room(s)
Particle Physics Electronics
Trigger Systems. DAQ Systems.
Custom Electronics ChipsRadn Hard, Low Power
Purpose Built Digital Processing BoardsIn VME Bus Crates
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics
Special Dedicated Logic Functions (not possible in CPUs) Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate
Timing Massively Parallel Data Processing (Silicon Trackers with Millions of
Channels)
Custom DesignedPrinted Circuit Boards PCBs.
CommercialProgrammable LogicDevices
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Lecture Outline
Programmable Logic Devices Basics Evolution
Field Programmable Gate Arrays (FPGAs) Architecture
Design Flow Design Tools Hardware Description Languages
Industry Trends
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Connect Standard Logic ChipsVery Simple Glue Logic
Black Box SUM of PRODUCTS
FIXED Logic
Truth Table
Boolean Logic Minimisation
Transistor Switches
Digital Logic Function
3 InputsProduct AND (&)Sum OR (|)
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Programmable Logic Devices PLDs
Sum of Products
Un-programmed State Different Types SUM of PRODUCTS Prefabricated Programmble Links Reconfigurable Logic Function
Programmed PLD
Product Terms
Sums
Planes ofANDs, ORs
ANDs
OR
Inputs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Complex PLDs
CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links
CPLD Architecture
Feedback Outputs
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Application Specific Integrated Circuits ASICs
PLDs ASICs
Standard Cell
Full Custom
Gate Arrays
Structured ASICs*
SPLDs
CPLDs
*Not available circa early 1980s
TheGAP
Large Complex Functions . Millions of GatesCustomised for Extremes of Speed, Low Power, Radiation Hard
(Very) Expensive (in small quantities) > $1 Million mask set(Very) Hard to Design.Long Design cycles.NOT Reprogrammable. High Risk
Limited ComplexityThousands of Gates
CheapEasy to DesignReprogrammable.
Custom FabricatedDesign from Scratch
PrefabricatedProgrammed
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Application Specific Integrated Circuits ASICs
PLDs ASICs
Standard Cell
Full Custom
Gate Arrays
Structured ASICs*
SPLDs
CPLDs
*Not available circa early 1980s
TheGAP
Large Complex Functions
InexpensiveEasy to DesignReprogrammable.
FPGA
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays FPGA
Field Programmable Gate Array New Architecture ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects
Large Number of Logic Block ‘Islands’
1,000 … 100,000+
in a ‘Sea’ of Interconnects
FPGA Architecture
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks
Logic Functions implemented in Lookup Table LUTs Multiplexers (select 1 of N inputs) Flip-Flops. Registers. Clocked Storage elements.
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
FPGA Fabric Logic Block
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Lookup Tables LUTs
LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
3 Inputs LUT -> 8 Memory Cells
SRAM
Static Random Access MemorySRAM cells
SRAM
3 – 6 Inputs
Multiplexer MUX
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks
Larger Logic Functions built up by connecting many Logic Blocks together
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Clocked Logic
Flip Flops on outputs. CLOCKED storage elements. Sequential Logic Functions (cf Combinational Logic LUTs) Pipelines. Synchronous Logic Design FPGA Fabric driven by Global Clock (e.g. BX frequency)
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
FPGA Fabric
Clock
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Design Synchronous Logic
Pipelining Logic Combinational Logic
Data In
CombinationalLogic
CombinationalLogic
CombinationalLogic
etc.
&
|
AND
OR
|
NORFrom previous
bank of registersTo next bankof registers
Three levels of logic
Result
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Design Synchronous Logic
Pipelining Logic Combinational Logic Stored in Registers. Clocked Logic (e.g. at LHC BX 40 MHz)
Data In
CombinationalLogic
CombinationalLogic
CombinationalLogic
etc.
Clock
Data In
Registers Registers RegistersCombinationalLogic
CombinationalLogic
etc.Once Pipeline FullNew Result every Clock Period
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Design Synchronous Logic
Pipelining Combinational and Sequential Logic. Clocked Logic (e.g. at LHC BX 40 MHz)
Data In
CombinationalLogic
CombinationalLogic
CombinationalLogic
etc.
Clock
Data In
Registers Registers RegistersCombinationalLogic
CombinationalLogic
etc.
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Clocked Logic
FPGA Fabric driven by Global Clock (e.g. BX frequency)
16-bit SR
flip-flop
clock
muxy
qe
abcd
16x1 RAM
4-inputLUT
clock enable
set/reset
FPGA Fabric
Clock
Clock
Data In
Registers Registers RegistersCombinationalLogic
CombinationalLogic
etc.
Register Transfer Logic RTL
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Routing
Connections Routing signals between Logic Blocks Determined by SRAM cells
SRAM
Around Fabric Edges Configurable Input Output I/O Blocks100’s – 1,000 Pins
Special Routing for Clocks
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Configuring an FPGA Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Loses configuration when board power is
turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. ROM or Digital Camera card Configuration takes ~ secs
Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
SRAM
JTAG Testing
JTAG Port
ProgrammingBit File
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Designing Logic with FPGAs
High level Description of Logic Design Hardware Description Language (Textual)
Compile (Synthesise) into Netlist. Boolean Logic Gates.
Target FPGA Fabric Mapping Routing
Bit File for FPGA
Commercial CAE Tools(Complex & Expensive)
Logic Simulation
Gate-levelnetlist
BEGIN CIRCUIT=TEST INPUT SET_A, SET-B, DATA, CLOCK, CLEAR_A, CLEAR_B; OUTPUT Q, N_Q; WIRE SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A, IN2=SET_B, OUT1=SET); GATE G2=NOT (IN1=DATA, OUT1=N_DATA); GATE G3=OR (IN1=CLEAR_A, IN2=CLEAR_B, OUT1=CLEAR); GATE G4=DFF (IN1=SET, IN2=N_DATA, IN3=CLOCK, IN4=CLEAR, OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Fully-routed physical(CLB-level) netlist
Schematiccapture
Mapping
Packing
Place-and-Route Timing analysis
and timing report
Gate-level netlistfor simulation
SDF (timing info)for simulation
Design Flow
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Hardware Description Languages
High Level Description of Logic Program Statements. Loops. If Statements …etc
Describing Mixture of Combinational and Sequential (Clocked) Logic and Signals between.
Register Transfer Level Description
Program Describes how to construct Hardware logic. Unlike conventional Programming Language generating machine code for
Sequential Processor In practice often closely tied to Hardware (like Assembly Language)
Non Portable
Electronics Engineers call code “Firmware”
VHDL (VHSIC Hardware Description Language) Very High Speed Integrated Circuit
VERILOG Language
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
architecture Behavioral of dpmbufctrl is
signal acount : std_logic_vector(31 downto 0); signal dcount : std_logic_vector(31 downto 0); signal bram_addr_i : std_logic_vector(31 downto 0); begin
bram_en <='1';bram_rst <= '0';
--bit order reverse address and data buses to match EDK schemebram_addr(0 to 31) <= bram_addr_i(31 downto 0);
--N.B. EDK DOCM addresses are byte orientated count in 4s for whole words
g1 : process(clk, rst) variable state : integer range 0 to 3;
variable buf_zone: integer range 0 to 1;
begin
if clk'event and clk = '1' thenif rst = '1' then buf_zone:=0;
acount <= (others => '0'); dcount <= (others => '0'); bram_wen <= (others => '0'); bram_addr_i <= X"00001FFC"; -- bram_dout_i <= (others => '0'); state:=0;
elsif state = 0 then --wait for din(0) at address 1FFC to be set to zero --what about pipeline of BRAM - need to wait before polling? bram_wen <= (others => '0'); acount <= (others => '0'); bram_addr_i <= X"00001FFC"; bram_dout_i <= (others => '0'); dcount <= dcount; if bram_din_i = X"00000000" then
state := 1; else
state := 0; end if;
VHDL Firmware
Signals
Parallel Processes
Flip Flop Registers
If Else Blocks
Variables
Signal Assignments
Architecture
Cf High Level Software LanguageC, Pascal
Code Blocks
Functions
Multiplexers
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays FPGA
Large Complex Functions Programmability, Flexibility.
Massively Parallel Architecture Processing many channels simultaneously cf MicroProcessor
sequential processing
Fast Turnaround Designs SRAM Based. Standard IC Manufacturing Processes (Memory Chips) Leading Edge of Moore’s Law Mass produced. Inexpensive. Many variants. Sizes. Features.
Not Radiation Hard Power Hungry
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Trends
State of Art is 65nm on 300 mm wafers Top of range 100,000+ Logic Blocks 1,000 pins (Fine Pitched Ball Grid Arrays)
Logic Block cost ~ 1$ in 1990 ; $0.002 in 2005
Challenges Power. Leakage currents. Signal Integrity Design Gap
CAE Tools
CLB Capacity
Speed
Power per MHz
Price
ITRS Roadmap
Virtex &Virtex-E
XC4000
100x
10x
1x
Spartan-2
1000x
Virtex-II &Virtex-II Pro
Virtex-4
XC4000 &Spartan
Spartan-3
'91 '92 '93 '94 '95 '96 '97 '98 '99 '00 '01 '02 '03 '04
Year
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Summary
Programmable Logic Devices Basics Evolution
Field Programmable Gate Arrays (FPGAs) Architecture
Design Flow Hardware Description Languages Design Tools
Trends
Importance for Particle Physics Experiments
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Highly Recommended Books
Bebop to the Boolean Algebra Clive Maxfield Published by Newnes
The Design Warrior’s Guide to FPGAs Clive Maxfield Published by Newnes
Fundamentals of Digital Logic with VHDL Stephen Brown, Zvonko Vranesic Published by McGraw Hill