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Qi Mi & Zhi LiECE 632 – Fall, 2008University of Virginia
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OutlineIntroductionProblem StatementContributionDesignSimulationConclusionFuture WorkQ & A
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IntroductionRFID applications
RFID security issues
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Problem StatementConstraint:
Energy – foremost constraintSizeComplexity
Problem: We seek to find a feasible way of implementing low-power data encryption on RFID tags.
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ContributionImplemented the core hash function (i.e., CRC-
Half) of CRC-MAC with PTM 90nm technology.
Analyzed energy at different operating voltages.
Gave an optimal operating voltage point for CRC-MAC.
Analyzed the trend of leakage current of the circuit.
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CRC-MAC Briefing
Fig 1. A hardware implementation of CRC-MAC
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CRC-MAC Briefing (cont’d)
Fig 2. C implementation of CRC-MAC as keyed one-way function
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Circuit Design
Fig 3. A symbol view of CRC-Half
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Simulation
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Optimization DesignMetric: Total energy consumption
E/op = Eactive + Eleakage = CeffVDD2 + IlkgVDDTD
KnobsLower VDD (subthreshold design)
Robust, require CMOSShorten operation duration
th
DSDSTGSV
V
s
VVV
oLKG eL
WII 110
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SimulationTechnology: PTM 90nm TechnologyCircuit Description: netlistsSimulation Environment
Schematic-level Software: FPGA Advantage 7.0 LS
Circuit-level Software: Cadence 2005 Simulator: Ocean with Spectre
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Simulation (cont’d)Approach
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Spectre Simulation Result
Data word: 0010 1001 0010 1101Key word: 1101 0010 0001 0111Output: 1011 0001 0001 0111
1
1
1
0
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Leakage Current Simulation
s
VVV
oD
DSTGS
L
WII
10
Exponential Reduction as VDD decreases due to DIBL effect
Leakage Current is independent of CLK rate
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Current Waveform in One Cycle
Pavg = α0→1fCeffVDD2
A higher CLK rate helps reduce energy consumption for a certain VDD
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Total Energy per CRC cycleVDD
(V)
Tcr (ns) Iavg (A) Etotal (nJ)
0.5 10 3.09E-05 1.55E-03
0.45 15 1.98E-05 1.33E-03
0.4 20 1.33E-05 1.06E-03
0.35 40 6.20E-06 8.68E-04
0.3 70 3.50E-06 7.36E-04
0.25 200 1.53E-06 7.63E-04
0.2 700 7.16E-07 1.00E-03
0.15 1800 4.84E-07 1.31E-03
/total DD avg CRC CLKE V I n f
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Energy Consumption Plot• The optimal supply voltage is around 0.3V• Leakage energy consumption starts to dominate in the sub-threshold region• Leakage current is taking up a large proportion of average current
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ConclusionCRC-processing circuit is simulated in FPGA
and CadenceAverage and leakage currents are simulatedEnergy consumption comparison for different
VDD and VDD optimization for minimum energy consumption
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Future WorkUse multiple power supplies to speed up the
critical pathSize up some parts of the circuit to increase
speedAdd high VT NMOS to the PDN to reduce
leakage
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Q and A?
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Thank you!