Download - IMPLEMENTATION OF µ - PROCESSOR DATA PATH
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IMPLEMENTATION OF IMPLEMENTATION OF µ - PROCESSORµ - PROCESSOR
DATA PATHDATA PATH
Project By:Project By:Daniel BrauchDaniel BrauchElad ShabtaiElad Shabtai
Barak SchlosserBarak Schlosser
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Project Goals
• Designing and implementing the schematic and layout design of an 8 bit µProcessor data path , which will include an ALU Manchester carry look ahead and a barrel shifter.
• Testing the design for accuracy and performance.
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Data Path overall design
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Applications:
• The data path is the core element of every micro processor and thus included in every application that performs arithmetic calculations ,logic evaluation and data movement.
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Implementation Notes :
• The ALU will be built from a Manchester carry look ahead adder and eight 1 bit ALU.
• The output of the ALU will be inserted into the shift register for shifting operations.
• The barrel shifter can perform up to 3 bit shifts in a single combinational function.
• The inputs for the ALU are valid on the rise of the clock.
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Design Specifications:
• ALU:
• Inputs: two 8-bit words (A,B)3-bit ALU controls.
3-bit shift controls.
1-bit clock.
* Cin bit will be generated from the ALU control bits
• Output: 8-bit word (F), 1 carry out.
• Functions:A or B, A and B, A xor B, A + B,
A – B , B – A , Pass A, Pass B
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Design Specifications:
• Barrel Shifter: • Can multiply by 1, 2 , 4 or 8 by shifting left 0, 1 ,2 or 3 bits.
• General:• Power supply: Vdd is set to 5 volts referenced to
ground.
• Size specifications: Final physical size must be optimized.
• Time specifications: All data and control bits are set on the rise of the clock. The maximum propagation delay for all functions must be less than 100ns.
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Manchester Carry
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Manchester Carry Chain
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Manchester Carry explanation
• For each bit 2 values are calculated:• Pi = Ai XOR Bi• Gi = Ai AND Bi• On the rise of the clock the upper PMOS gates
are closed and the bottom NMOS are open enabling the pull down of the carry out bar.
• The Pi controls enables the propagation of the Cout signals.
• The max propagation delay is caused by the pulling down of all the carry out bar signals.
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Manchester Carry cont.
• The main advantage of the Manchester chain is its small physical size.
• In terms of propagation delay the Manchester chain is situated in the middle of the scale.
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Comparison between different Full Adders
0 10 20N
0.0
20.0
40.0
60.0
80.0
t p (
nse
c)
0 10 20N
0.0
0.2
0.4
Area
(m
m2
)look-ahead
select
bypass
manchester
mirrorstatic
manchester
look-ahead
select
static
mirrorbypass
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1 bit ALU implementation
FULL
ADDER
XOR
MUX 4:1
MUX 4:1
LOGIC
AND
OR
B
A’
B
A
A’
0
0
B’
S2 S1
S1 S0
Cin
Out
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ALU control bitsS2 S1 S0 OPERATION
0 0 0 B - A
0 0 1 OR
0 1 0 AND
0 1 1 A + B
1 0 0 XOR
1 0 1 PASS B
1 1 0 PASS A
1 1 1 A - B
000 : B - A
111 : A - B
001 : OR
010 : AND
100 : XOR
011 : A + B110 : PASS A101 : PASS B
CHAIN
F.A
XOR - 111
Equivalence
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MUX 4:1 implementation
A
B
C
D
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1 bit FULL ADDER implementation
C B A
SUM = A xor B xor C
** no need to compute carry out – calculated by Manchester carry look ahead
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Tanner S-Edit
modules implementation
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Manchester – module :
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Simulation results :
0 5 10 15 20 25 30 35 40 45 50
Time (ns)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Vo
lta
ge
(V
)
v(Out3)5.00
v(Out4)5.00
v(Out5)5.00
v(Out6)4.99
v(Out7)4.99
x1= x2= dx=-912.46p 14.14n 15.06ntest_manchester_carry
Carry all:
Carry last – worst case propagation ~10ns:
0 5 10 15 20 25 30 35 40 45 50
Time (ns)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Vo
lta
ge
(V
)
v(Out3)
v(Out4)
v(Out5)
v(Out6)
v(Out7)
test_manchester_carry
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Barrel shifter – module :
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Simulation results - shifting 01001011:
0 5 0 1 0 0 1 5 0 2 0 0
Tim e ( ns )
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
5 .0
Vo
ltag
e (
V)
v (Q 0 )
Unti tl ed
0 5 0 1 0 0 1 5 0 2 0 0
Tim e ( ns )
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
5 .0
Vo
ltag
e (
V)
v (Q 1 )
Unti tl ed
0 5 0 1 0 0 1 5 0 2 0 0
Tim e ( ns )
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
5 .0
Vo
ltag
e (
V)
v (Q 2 )
Unti tl ed
0 5 0 1 0 0 1 5 0 2 0 0
Tim e ( ns )
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
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4 .0
4 .5
5 .0
Vo
ltag
e (
V)
v (Q 3 )
Unti tl ed
0 5 0 1 0 0 1 5 0 2 0 0
Tim e ( ns )
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
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3 .5
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4 .5
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Vo
ltag
e (
V)
v (Q 4 )
Unti tl ed
0 5 0 1 0 0 1 5 0 2 0 0
Tim e ( ns )
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
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5 .0
Vo
ltag
e (
V)
v (Q 5 )
Unti tl ed
0 5 0 1 0 0 1 5 0 2 0 0
Tim e ( ns )
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
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Vo
ltag
e (
V)
v (Q 6 )
Unti tl ed
0 5 0 1 0 0 1 5 0 2 0 0
Tim e ( ns )
0 .0
0 .5
1 .0
1 .5
2 .0
2 .5
3 .0
3 .5
4 .0
4 .5
5 .0
Vo
ltag
e (
V)
v (Q 7 )
Unti tl ed
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1 bit ALU :
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Data Path – modules :Define Cin :
Shifter :
Calculate Cin :
Alu1bit * 8 - 8 bit output :
Choose output from Alu / Manchester :
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8 bit ALU - module :
Including :- Cin logic- Manchester chain- Alu- Cout logic
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8 bit ALU - design :
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8 bit ALU simulation - pass A (00000001) :
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8 bit ALU simulation - AND A (10001001) B (10000001) :
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DataPath –module :
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DataPath simulation : (A + B) * 4
A=00001010 B=00000011
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DataPath simulation : (A + B) * 4 A=00001010 B=00000011
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VHDL
Simulation
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VHDL – simulation resaults :
End – opCode 111 :
Start – opCode 000 :
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Advantages of design :
• Parallel implementation of calculations.• Minimal number of transistors in current
implementation ~ 600 transistors
- Trivial implementation using mux 8*1 with scmos
implementation ~ 1300 transistors
- Less transistors thus low on power consumption
and faster in propagation ~ 40 ns
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Milestones• Studying design options for the ALU, Manchester carry
look ahead and shifter - Due 01/06/04• Implementing all 3 units in gate level and testing them for
correctness and performance - Due 08/06/04• Combining units and testing overall design - Due 15/06/04• Creating VHDL test bench and comparing designs
- Due 22/06/04 • Grade : ?