A Low-Power Robust GFSK DemodulationTechnique for WBAN Applications
Pengpeng Chen∗ , Bo Zhao∗, Rong Luo∗, Yong Lian† and Huazhong Yang∗∗Tsinghua National Laboratory for Information Science and Technology
Department of Electronic Engineering, Tsinghua University, Beijing, 100084, China
Email: [email protected], zhao [email protected]†Department of Electrical Engineering and Computer Science, York University
Email: [email protected]
Abstract— This paper presents a low-power Gaussian fre-quency shift keying (GFSK) demodulation technique for wirelessbody area network (WBAN) applications. The demodulator iscomposed of a digital pulse generator (DPG), a low-pass filter(LPF), a band-pass filter (BPF), and a hysteresis comparator.The robustness under frequency deviations is realized by a DPG,which outputs an optimized pulse width insensitive to variationsof process, voltage, and temperature (PVT). The demodulator isdesigned with 0.18 μm CMOS technology, and the input testingGFSK signal is 200 kHz, with a data rate of 100 kb/s anda modulation index of 1.0. Simulation results show that theminimum input signal-to-noise ratio (SNR) is 18 dB for 0.1%bit error rate (BER), which falls in the same level with state-of-the-art. Nevertheless, the proposed demodulator can tolerate-15%∼+10% frequency deviation, and consumes only 0.52 mAunder 1.8 V supply.
I. INTRODUCTION
Wireless body area network (WBAN) will play an important
role in future healthcare applications, especially in ageing so-
ciety. A WBAN typically consists of several wireless wearable
sensors distributed around human body to collect vital signs
while sending collected information to remote doctors. For
many WBAN applications, two considerations are vital, i.e.
(1) power consumption which directly decides the life time
and battery volume of sensor nodes; and (2) robustness which
is critical for reliable operation.
Frequency shift keying (FSK)/ Gaussian FSK (GFSK) is
usually adopted for the communication in WBAN because of
its power efficiency, simplicity, and robustness. For instance,
the transceiver in [1] used double-FSK modulation for body
channel communication (BCC) transceiver. In addition, Blue-
tooth low-energy PHY standards adopt GFSK modulation [2],
[3]. Limiter based transceivers are usually employed to replace
analog to digital converters (ADCs) [4]–[6]. As shown in
Fig. 1, the limiters remove the amplitude processing while
keeping the FSK/GFSK information of zero-crossing points,
so a large dynamic range can be achieved with low power
consumption.
The demodulation of FSK/GFSK is a design bottleneck
for its strict requirements on power and robustness. It has
attracted much research effort in designing FSK/GFSK de-
modulation circuit [4], [7]–[11]. A conventional way is to use
time-domain differentiator and mixer [7], but this approach
LNA
Mixer
Mixer
Filter Limiter
Limiter
FSK/GFSK
Demodulator
0o
90o
Fig. 1. Limiter based FSK/GFSK receiver.
increases receiving power consumption to 8.1 mW. Moveover,
this demodulation method depends on the values of on-chip
resistors and capacitors, which are very sensitive to variations
of process, voltage, and temperature (PVT). An improved
method was reported in [8] that uses the input GFSK signal
as clock of a delay chain for demodulation, but it requires a
Sallen-Key filter which consumes 4 mW power. For robustness
design, pulse generation techniques were proposed in [4] and
[11]. However, on-chip capacitors in [4], [11] are sensitive to
PVT variations [9]. Frequency deviations are canceled in [10]
by a digital estimation method, but the tolerance of frequency
deviations is not quantified.
In this work, we present a novel GFSK demodulation
technique with low power consumption. To be robust under
frequency deviations, a PVT-insensitive digital pulse gener-
ator (DPG) is designed, and the pulse width is optimized
by analysis and simulation. Following the DPG, active-RC
filters are employed for good linearity and robustness against
interferers. Different from the work using Sallen-Key filter
[8], the adopted active-RC filters are low-order and dissipate
much less power. Low power consumption is achieved owing
to digitalization of pulse generator and active-RC circuits with
low operating frequency.
The paper is organized as follows. Section II presents the
design considerations of the proposed demodulation technique.
The circuit design is introduced in detail in Section III. Section
978-1-4799-1471-5/13/$31.00 ©2013 IEEE 366
IV discribes the final simulation results of the demodulator.
Section V concludes the paper.
LPFI
Q outDPG BPF
Hysteresis
ComparatorLimiter
Proposed Demodulator
VI
VQ
RC
Calibration
Crystal
Oscillator
Fig. 2. System architecture.
II. DESIGN CONSIDERATIONS
System architecture of the proposed GFSK modulator is
given in Fig. 2. The signals from limiters are fed into a
DPG, which produces a pulse with a fixed width at each zero-
crossing point. The DPG is followed by a low-pass filter (LPF),
and the information expressed by pulse number is changed
into different voltage levels. The combination of band-pass
filter (BPF) and hysteresis comparator is adopted to cancel DC
offset and interferences and perform data decision [12]. The
signals at each stage in the demodulator are shown in Fig. 3.
Because the signals are differential, the voltage for zero-
crossing points are 0.9 V. From top to bottom, the waveforms
are corresponding to the outputs of limiter, DPG, LPF, BPF,
and comparator, respectively.
The principle of our demodulation technique is analyzed
as follows. Representing the carrier frequency by fc, data
rate by fs, pulse width by w, and modulation offset by fd,
we can express the number of zero-crossing points at high-
frequency (nH ) and low-frequency (nL) segments of FSK
signal, respectively (Note that both I branch and Q branch
produce zero-crossing points):
nH = [4fs
(fc + fd)], (1)
nL = [4fs
(fc − fd)]. (2)
Thus difference of the zero-crossing numbers between high-
frequency and low-frequency segments is:
ND = nH − nL =4fs
(fc + fd) − 4fs
(fc − fd) =8fd
fs. (3)
For the number of zero-crossing points n in each symbol,
wn > w nH+nL
2 means data ’1’, while wn < w nH+nL
2represents data ’0’. Then, we can treat wn as an amplitude-
shift keying (ASK) signal with two extreme values of wnH
and wnL.
Based on the analysis method in [13], we can obtain the
distance d between two waveforms s1(t) and s2(t) (i.e. wnH
and wnL in our case):
d =√
E1 + E2 − 2ρ√
E1E2 (4)
E1 =∫ Ts
0
s1(t)2dt, s1(t) = wnH (5)
Time (s)
Time (s)
Time (s)
Time (s)
Time (s)
Time (s)
VI
(V)
VQ
(V
)P
uls
es (
V)
LP
F O
ut
(V)
BP
F O
ut
(V)
Dem
Ou
t (V
)
Fig. 3. Signal waveforms at each interface.
E2 =∫ Ts
0
s2(t)2dt, s2(t) = wnL (6)
where ρ is correlation coefficient, and can be expressed as:
ρ =
∫ Ts
0s1(t)s2(t)dt√
E1E2
. (7)
This leads to probability of correct reception, i.e.
P [C] = 1 − Q(d
2σs), (8)
where Q is described by:
Q(α) =1√2π
∫ ∞
α
e−y2/2dy, (9)
and σ2s is noise variance. With s1(t) = wnH and s2(t) =
wnL, d and P [C] can be expressed by:
d = w√
Ts(n2H + n2
L − 2nHnL)= w(nH − nL)
√Ts
= w 8fd√f3
s
(10)
367
P [C] = 1 − Q(w 4fd
σs
√f3
s
) (11)
From equation (11) we can see that a larger w means larger
probability of correct reception. In addition, the basic range
of w should be taken into account:
0 < w <Ts
4(fc + fd)/fs=
14(fc + fd)
. (12)
Note that a lower fc ensures a larger w, but leads to larger
flicker noises.
DPG is one of the key sub-modules in our demodulator.
Width of pulse has a great effect on probability of correct
reception. The digital circuit ensures a much more accurate
w than analog pulse generators using capacitors which have
large PVT variations.
Following the DPG, a LPF is used to filter the pulses
into low-frequency signals. The output voltage of LPF is
determined by two factors: 1) bandwidth of LPF, and 2) pulse
width input to LPF. The bandwidth of LPF is between 1 to 2
times of baseband width.
The combination of BPF and comparator is designed to deal
with the DC offset and interferences. The BPF helps remove
the low frequency components, and filter out high-frequency
noise at the same time. The comparator is a hysteresis one to
avoid the influence of interferences.
III. CIRCUIT DESIGN
The proposed demodulation circuit is designed in 0.18 μm
CMOS technology. As an experiment, the circuit is designed
for an input signal with a carrier frequency of 200 kHz, a data
rate of 100 kb/s, and a modulation index of 1.0.
The block diagram of DPG is shown in Fig.4. A 20 MHz
crystal is utilized to provide clock for all digital blocks.
The Zero Detector detects all zero-crossing points in I/Q
limited signals V I and V Q, and the pulse generator outputs
pulses whose width is consistent with the mode of counter.
The counter mode is controlled by a pulse-width controller
with optimized setting. In this work, the carrier frequency is
200 kHz with 50 kHz modulation offset, which means the
minimum sine wave cycle is 4 μs. Therefore, the pulse width
should be between 0 μs∼1 μs. A larger pulse width results in
a larger frequency-to-voltage gain. However, if pulse width is
too large, there will be pulse overlap especially when there is a
frequency deviation, and bit error rate (BER) will be degraded.
Zero Detector
VI
VQ
Output
Crystal Oscillator
Pulse Generator
Counter
Pulse-Width
Controller
Fig. 4. Architecture of DPG.
To achieve an optimized pulse width, BER is simulated at
different pulse widths and different frequency deviations as
shown in Fig.5. The carrier frequency is set at 220 kHz and
180 kHz. To make the data more clearly, 15 dB SNR is used
for 200 kHz signal and 19 dB SNR for 180 kHz and 220 kHz
signals. To tolerate 20 kHz frequency deviation, pulse width
should be smaller than 15 clock periods, as displayed by curve
B in Fig.5. Taking into account of the requirements on SNR
and immunity to frequency deviations, we set the pulse width
to 14 clock periods.
10 12 14 16 18 2010
−5
10−4
10−3
10−2
10−1
100
Pulse Width (number of clock periods)
BER
200 kHz, 15 dB
220 kHz, 19 dB
180 kHz, 19 dB
C
A
B
Fig. 5. BER versus pulse width of DPG.
An active-RC LPF is adopted to remove high frequency
components of pulses. Because data rate is 100 kbps, so the
cutoff frequency should be larger than 50 kHz to remove high
frequency components, and 60 kHz cutoff frequency is chosen.
The active-RC BPF is used to cancel DC offset and filter
out high-frequency interferences. Simulation results show that
the performance is the best when center frequency is 50 kHz.
Taking into account of robustness performance, the demod-
ulator should be immunity to frequency deviations and PVT
variations. Pulse width is optimized to maximize the tolerance
of frequency deviations. The time constants of active-RC
modules are calibrated to deal with PVT variations [9]. The
calibration is carried out only in set-up stage of the circuit, so
it does not add extra power consumption.
A hysteresis comparator is connected to the output of BPF.
The threshold of the hysteresis comparator is 34 mV to prevent
bit errors caused by jitters.
IV. SIMULATION RESULTS
Firstly, the BER performance is simulated. GFSK data with
white Gauss noise is generated by Matlab, the BER curve is
plotted in Fig.6. It can be seen that less than 18 dB SNR is
required for 10−3 BER requirement.
Secondly, the robustness of proposed demodulator is vali-
dated by simulation presented here. The carrier frequency is
swept from 120 kHz to 260 kHz with an input SNR of 18 dB.
The resulted BER curve is plotted in Fig.7. Simulation results
show that BER is kept below 0.1% when carrier frequency
deviations are -15%∼+10%.
Lastly, the power consumption of proposed demodulator is
only 1 mW under 1.8 V power supply. Table I summarizes
368
TABLE I
PERFORMANCE COMPARISON.
References CMOS Technology Frequency Data Rate SNR Frequency Deviation Power Consumption(μm) (Hz) (b/s) (dB) Tolerance (mW)
[8], 2006 0.25 2 M 1 M 16.5 10% 6[5], 2007 0.18 5 M 1 M/250 k 14.9/7.4 7%/-12%∼+9% 3.6
[14], 2007 0.18 3 M N/A 19.5 3.3% 2.64[15], 2009 0.18 2 M 0.1 to 2.0 M 16.0 N/A 0.81This work 0.18 200 k 100 k 18.0 -15%∼+10%a 1
aThe demodulator is simulated at 18 dB input SNR to get the frequency deviation tolerance.
14 15 16 17 18 1910
−5
10−4
10−3
10−2
10−1
SNR (dB)
BER
Fig. 6. BER versus SNR.
120 140 160 180 200 220 240 26010
−4
10−3
10−2
10−1
Carrier Frequency (kHz)
BER
Fig. 7. BER versus carrier frequency.
the performance, and compares to state of the art. Comparison
results indicate that the solution presented in our work has the
advantage on robustness and power consumption, which meet
the basic requirements of WBAN applications.
V. CONCLUSION
A low-power robust GFSK demodulator has been presented
for WBAN applications in this paper. The proposed digital
pulse generator produces pulses with an accurate width which
is immune to PVT induced variations. The pulse width is
optimized to realize the robustness under frequency deviations
of -15%∼+10%. In addition, the total power consumption of
proposed demodulator is 1 mW, which is also an advantage
compared with state-of-the-art.
ACKNOWLEDGMENT
This work was supported by the National Natural Science
Foundation of China (NSFC) under Grant 61204032.
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