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NAME
H.T.No
YEAR/SEMESTER
DEPARTMENT OF ELECTRONICS &COMMUNICATION ENGINEERING
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S.NO DATE NAME OF THE EXPERIMENT
PAGE
NO REMARKS
INDEX
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AIM:
To verify the operation of 741 Op-Amp as
a) Adder
b) Subtractor
c) Comparator
Apparatus :
IC 741 1 No
Resistors: 10k,
1k
4 Nos
1 No
Potentio meter: 10k 1 NoRPS 2 No.
Function Generator 1 No.
Connecting wires =====
Bread Board 1 No
CRO 1 No
CRO Probes 2 Nos
Digital Multi Meter 1 No.
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EXP NO:1OP AMP Applications Adder,
Subtractor, Comparator Circuits
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Circuit Diagrams:
Inverting Adder
Fig-(a): Inverting Adder
Non-Inverting Adder:
Fig.(b): Non-Inverting Adder:
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THEORY:
a)ADDER: OP-AMP is used to design a circuit whose output is the
sum of several input signals. Such a circui t is cal led Summing
amplifier (summer) or adder.
b) SUBTRACTOR: we can also connect signals to both of the inputs at the same time
producing another common type of operational amplifier circuit called a Differential
Amplifier.
By connecting one voltage signal onto one input terminal and another voltage signal onto
the other input terminal the resultant output voltage will be proportional to the
"Difference" between the two input signals of V1 and V2 and this type of circuit can alsobe used as a Subtractor.
C) COMPARATOR: In electronics, a comparator is a device which compares twovoltages orcurrents and switches its output to indicate which is larger.
.
A standard op-amp operating in open loop configuration (without negative feedback) canbe used as a comparator. When the non-inverting input (V+) is at a higher voltage than the
inverting input (V-), the high gain of the op-amp causes it to output the most positive
voltage it can. When the non-inverting input (V+) drops below the inverting input (V-),the op-amp outputs the most negative voltage it can. Since the output voltage is limited by
the supply voltage, for an op-amp that uses a balanced, split supply, (powered by VS)
this action can be written:
Vout = Ao(V1 V2)
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SUBTRACTOR:
Fig(c) subtractor
Comparator:
Fig.(d) comparator
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Model Wave forms:
For positive reference voltage
For negative reference voltage
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Tabular columns:
Inverting adder
S.No. V1 in
volts
V2 in
volts
Practical value
V0=-(V 1+V 2)volts
Theoretical value
V0=-(V 1+V 2)volts1.
2.
3.
4.
Non-inverting adder
S.No. V1 in
volts
V2 in
volts
Practical value
V0=+(V 1+V 2)
Theoretical value
V0=+(V 1+V 2)
1.
2.
3.
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4.
Subtractor
S.No. V1 in
volts
V2 in
volts
Practical value
V0=(V 1-V 2)volts
Theoretical value
V0=(V 1-V 2)volts
1.
2.
3.
4.
Zero crossing detector
Zero crossing detector
PINDIAGRAM OF IC 741
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Precautions:
Avoid the loose connections.
Supply voltage should not exceed + 15V.
Discussions :
1. What is an op-amp?
2. Give the characteristics of an ideal op-amp:3 How a non-inverting amplifier can be converted into voltage follower?
4. What is inverting adder?
5 What is the difference between subtractor and difference amplifier?
6. What is the difference between a basic comparator and the Schmit t
trigger?
Result:
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Aim:
(a)To design a Low Pass Filter and High Pass Filter at a cut off
frequency of 1 KHz with a pass band gain of 2.
(b) To plot the frequency response of the filter in part (a).
Apparatus :
IC 741 1 No
Resistors:10k,
20k Pot
2 Nos
1 No
Capacitors:0.01 F 1 NoFunction Generator 1 No.
Connecting wires =====
Bread Board 1 No
CRO 1 No
CRO Probes 2 Nos
THEORY:
HPF: A frequency selective electric circuit that passes electric signals of specified band
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EXP NO:2 FIRST ORDER LOW PASS AND HIGH
PASS FILTERS USING 741 OP-AMP
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Of frequencies and attenuates the signals of frequencies outside the brand is called an
electric filter. The first order high pass filter consists of a single RC network connected to
the non-inverting input terminal of the operational amplifier. ResistersR1 and RFdetermine the gain of the filter in the pass band. The high pass filter has Maximum gain at
f = fl Hz. The frequency range from 0 to Fl is called the stop band the frequency range f >
fl is called the pass band.
LPF: A frequency selective electric circuit that passes electric signals of specified band of
frequencies and attenuates the signals of frequencies outside the brand is called an electricfilter. The first order low pass filter consists of a single RC network connected to the non-
inverting input terminal of the operational amplifier. Resisters Ri and RF determine the
gain of the filter in the pass band. The low pass filter as maximum gain at f = 0Hz. The
frequency range from 0 to FH is called the pass band the frequency range f > fh is calledthe stop band.
Circuit Diagrams :
Fig (1): Low pass first order Butterworth filter:
Fig.(2): High pass first order Butterworth Filter
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Design:
Low pass filter:
Let fh = 1 KHz A v = 2
Choose C = 0.01 F
Since fh =CR2
1
CfR
h2
1=
R( )
( )KPOTK 209.1501.0102
13
==
Pass band gain, A v = fiL
F RRR
R==+ 21
Let Ri = Rf = 10 K.
R = 15.9 K, C = 0.01 F, Ri = Rf = 10 K.
High Pass Filter:
Let fL = 1 KHz A v = 2
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4 400
5 500
6 600
7700
8 800
9 900
10 1k
11 1.5k
12 2k
13 2.5k
14 3k
15 4k
Procedure:
Low Pass Filter Connect the circuit as shown in figure (1) for Low Pass Filter
and f igure (2) for High Pass Fil ter , with the values of the
components obtained from the design.
Given an input signal V i of 1V peak to peak and measure the
output voltage for different input frequencies.
Plot the frequency response 20 log V 0 /V i versus input signalfrequency and find the 3 dB frequency from here.
Calculate the theoretical value of upper cutoff frequency f n and
the pass band gain A 0 .
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fh = CR2
1
. A 0 (dB) = 20 log (1+i
t
R
R
).
High Pass Filter:
Interchange the resistor R with the capacitor C to make the high
pass filter and repeat step 2 and 3.
Calculate the theoretical value of the lower cutoff frequency f L
and pass band gain A 0 using that formula.
CR
fL2
1= ,
( )
+=
L
f
R
RA
dB
1log200
High Pass Filter: V i =
S.NO.Frequency
f in Hz
Output Voltage V 0
in VoltsGain |V 0 /V i |
Gain in dB
20 log|V 0/V i |
1 100
2 200
3 300
4 400
5 500
6 600
7 700
8 800
9 900
10 1k
11 1.5k
12 2k
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13 2.5k
14 3k
15 4k
Precautions:
1. The supply voltage should not exceed 15 V.
2. Always give +Ve and Ve supply voltage to 7th pin and 4th
pins re spect ive ly.
Discussions:
1. What is an active fil ter?
2. Why are active fil ters preferred?
3. List the commonly used filter s.
4 . What i s the s tandard form of the t ransfer funct ion of a f i rs t o rder
low-pass system?
5. What is roll-off rate of a first order fil ter?
Result:
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Aim:
To construct a triangular wave generator using 741 Operational
Amplifier.
To observe the output waveform and measure their frequency.
Apparatus :
IC 741 2 Nos.
Resistors: 47K,100k, ,22k
10k
Each 1 No.
2 Nos
Capacitors: 0.047 F,
0.05 F
1 Nos.
1 Nos
RPS 1 No.
DRB /20KPOT 1 No
CRO 1 No
CRO Probes 2 Nos
Connecting wires =====
CIRCUIT DIAGRAM:
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EX NO:3 FUNCTION GENERATOR DATE:
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Astable multivibrator Integrator
Fig: FUNCTION GENERATOR
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Theory:
A function generator is a piece of electronic test equipment or
software used to generate electrical waveforms. These waveforms can be
either repetitive, or single-shot in which case some kind of triggering source
is required (internal or external).
Function generator is astable multivibrator followed by an integrator. The
output of the astable multivibrator is Square wave
Triangular wave can be simply obtained by integrating a square wave as
shown in the fig. It is obvious that the frequency of the square wave and
triangular wave is same as shown in the waveform. Although the amplitude
of the square wave is constant at Vsat, the amplitude of the triangular wavewill decrease as the frequency increases. This is because the reactance of
the capacitor in the feedback circuit decreases at high frequencies. The
resistance is connected across the capacitor to avoid the saturation problem
at low frequencies as in the case of practical integrator.
Procedure : Connect the circuit as per the circuit diagram.
Note that the ou tput of first oper at ional amplifier is a square
wave.
Output of Operational Amplifier1 is given to the inverting
input terminal of operational amplifier.
Observe the output, which is a triangular wave.
Note down the waveforms for di ffe rent values of R2.
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TabularColumn:
26
S.No
.
R2Theoretical
Time period
t ( ms)
Practical
Time period
t ( ms)
Square wave
output
Vo(volts)
Triangular
wave output
Vo(volts)
1. 10k
2. 22k
3. 47k
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Precautions :
Inverting terminal of Operational Amplifier 1 must be
grounded through a capacitor.
For proper operating a voltage compensating network is
connected at non inverting te rminal.
Time constant of integrator should be proper.
Calculations :
T= 2 RC ln(1+2(R1/R2))
For R2=10K
R=10K, R1 = 10K, R2= 10K, C=0.05F
T=2x 10 4 x 0.05x 10 -6 ln [1+ ]
T=1.09msec (1msec)
For R2=22K
T=
For R2=47K
T=
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Outputwaveform
For R=10k
For R=22k
For R=47k
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Discussions:
1. What happens if the capacitor at the non-inverting
terminal is removed and what happens i f the
capacitor is replaced by a resistor?
2. What changes wi ll occur in ampl itude of a
triangular wave as frequency increases?
3. What happens to frequency of oscillation as R 2increases?
4. What does the factor indicates?
Result:
Conclusion :
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PINDIAGRAM OF IC 555
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Aim:
To design an Astable and monostable Multivibrator using IC
555 and observe the output waveforms.
Apparatus:
IC 555 1 No
Resistors:2.2k,3.9k,10k Each 1 NoCapacitors:0.1 F,
0.01 F,1F
Each 1 No.
RPS 1 No.
Millimeter 1 No.
Connecting wires =====
DRB 1 No
Bread Board 1 No
CRO 1 No
CRO Probes 2 Nos
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EX NO:IC 555 AS AN ASTABLE AND
MONOSTABLE MULTIVIBRATOR
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Circuit Diagram:
Fig (1) Astable Multivibrator:
Circuit Diagram :
Fig (2) Monostable Multivibrator
THEORY:
The 555 t imer can be used with supply vol tage in the range of +5v to
+18v and can drive up to 200mAmp. It is compatible with both TTL and
CMOS logic circuits because of the wide range of supply voltage the 555
timer is versatile and easy to use in the astable multivibrator. The timer
is oscillated between two threshold levels 1/3Vcc and 2/3Vcc in order to
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generate a square wave form. No external signal source is required for
such generation and hence this is called as a free running multivibrator
The 555 timer can be used with supply voltage in the range of +5 v
to+18v and can drive up to 200mAmps. It is compatible with both TTL
and CMOS logic circuits because of the wide range of supply voltage the
555 timer is versatile and easy to use in monostable multivibrator we will
provide external trigg ering in order to make the time r to switch ov er to
high state (unstable). This is also called as one-shortmultivibrator.
Procedure :
Astable Multivibrator
Connect the circuit as per the circuit diagram(1)
Observe the output at the 3rd pin.
Note down the time period and verify the theoretical charging
and discharging periods.
Monostable Multivibrator:
Connect the circuit as per the circuit diagram(2)
Apply the trigger at Pin No 2
Observe the output the 3 r d pin.
Note down the time per iod and ve rif y the theoretical values
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Model Waveforms:
Monostable multivibrator:
Astable multivibrator:
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Design procedure: (for Monostable Multivibrator)Pulse width T=1.1 RC;
Let C=1F & T=1msec
1 msec= 1.1 (R) (1 F)=>R=10K
For Astable Multivibrator:
Let f=1.45KHz,C=0.1F
t c=0.0693(R1+R2)C for charging
td=0.693(R2)C for discharging
The total period of output waveform,T = t c + t d
= 0.693(R1+2R2)C
Frequency of oscillation f = 1/T =1.45/[(R 1+2R2)C]
1.45=1.45/[(R 1+2R2)C]
(R1+2R2 )=1/[0.01x10- 6
](R1+2R2 ) = 10K .. (1)
Let Duty cycle,D =40%
D=R2 /[R1+2R2]
0.4= R2 /[R1+2R2 ]
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From eqn (1),
0.4= R2 /10K
R2=4K
R1=2K
Precautions:
Reset pin 4 is connected to V c c when it is not used.
Pin 5 is grounded through a capacitor in order to reduce the
noise.
Reset pin is connected to V CC when it is not used.
Pin5 is grounded through a capacitor in order to reduce the
noise.
Trigger input is not necessary.
R1 should not be zero, if R 1 = 0 V CC is directly connected to pin
7 and IC may get damage.
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Discussions:
1. Explain the function of reset
2. What are the modes of operation of timer?
3. What is the expression of time delay of a monostable multivibrator?4. Discuss some applications of timer in monostable mode.
5. Define duty cycle
6. How is a monostable multivibrator connected into a pulse position modulator?
7. What is the expression of time delay of a astable multivibrator?
Result :
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Aim :
To find the line regulation and load regulations of a given
IC A 723.
Apparatus:
IC A 723 1 N0
Resistors:47 ,680,8.2K,
1K,1KPOT
Each 1 No
Capacitors: 100 pF 2 Nos
RPS 1 No.
Multimeter 1 Nos
Connecting wires =====
DRB 1 No
Bread Board 1 No
Theory:
The limitations of 3 terminal regulators have been overcome
in the 723 general purpose regulators, which can be adjusted
over a wide range of both positive and negative regulated
voltage. This IC is inherently low current device, but can be
boosted to provide 5Amps or more cur rent by connecting
external components. The limitation of 723 is that it has no
inbuilt thermal protection. I t also has no short circuit
current limits.
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EX NO:5 723 AS A VOLTAGE REGULATOR DATE:
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Circuit Diagram: Model Wave Form for Line
regulation:
Regulation:
Fig (1): Line Regulation
Tabular Columns:
Line Regulation:
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S.No. V i n (volts) Vo( Volts)1.
2.
3.
4.
5.
5.
7.
8.
9.
10.
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Procedure :
For line regulation ;
Connect the circuit as per the c ircuit diagram.(fig1)
Verify the input vol tage and note the corresponding
values of the output voltage.
Plot the graph between the input and output voltage.
For load regulation ;
Connect the circuit diagram as shown in figure2
Increase the value of the potentiometer gradually fromminimum value to a maximum value.
Note down the cor re sponding values of the load current
and the output voltage.
At some point, we find that the load voltage is being
maintained constant.
Plot a graph between the load current and load voltage.
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Fig(2) Load Regulation: Model Wave Form for Load
Regulation:
Load Regulation:
S.NO. RL IL (mA) V0 (Volts)
1.
2.
3.
4.
5.
6.
7.
8.
9.
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10.
Precautions:
The 13 t h pin must be connected to the 4 t h pin
through a di scharging capac itor so as to improve
efficiency.
Discussions:
1 What output voltage range we can obtain from 723 regulator?
2. What are the applications of 723 regulators?
3. Define line regulation
4. Define load regulation
5 .Define ripple rejection
Result:
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Aim :
To convert a digital signal to its equivalent analog signal
using 741 operational amplifier.
To verify practical output voltage with theoretical values
for a given binary inputs.
Apparatus:
IC 741 1 No.
Resistors:1K,5K,10 K
20K,40K
each 1 No.
RPS 1 No.
Multimeter 1 Nos
Connecting wires =====
THEORY:
Most of the real world physical quanti t ies such as vol tage current
temperature pressure are available in analog form. It is very difficult to
process the sign al in analog form; hence ADC and DAC are used. The
DAC is to convert digital signal into analog and hence the functioning of
DAC is exactly opposite to that of ADC. The DAC is usually operated at
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EX NO:6 D/A CONVERTER DATE:
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the same frequency as the ADC. The output of the DAC is commonly
staircase. This staircase like digital output is passed through a smoothing
filter to reduce the effect of quantization noise. There are three types of
DAC techn iques ( i ) Weigh ted res is to r DAC ( ii ) R-2R l adde r. ( ii i)
Inver ted R-2R ladder . Wide range of resi s tors i s requi red in b inary
weighted resistor type DAC. This can be avoided by using R-2R ladder
type DAC where only two values of resistors are required it is well suited
for integrated circuit realization.
Circuit Diagram :
Model Graphs:
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Procedure:
Connect the circuit as per the c ircuit diagram.
Give eight different combinations of inputs and note
down the corresponding outputs.
Compar e t he obt ained practi cal val ues with t he
theoretical values.
Plot the graph.
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Tabular Columns :
Decimal
Equivalent
Binary
Inputs
Inputs OutputsV1=
100
th
thP
V
VVb 3 b2 b1 b0
Theoretica (
V)Practical (VP)
1.
2.
3.
4.
5.
6.
7.
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Observations :
Output voltage V0 theoretically is
Rf VR
b
R
b
R
b
R
bRV
+++=
842
0123
0
For example;
For b 3 = 1, b 2 = 1, b 1 = 1, b 0=0
Theoretical output voltage V 0 = 0.75 V
Practical output voltage V 0=___V.
Precautions :
Take care in selecting the polar ity of the reference
voltage, which is chosen in accordance with the type of
switch is used.
The choice of smallest value is reasonable, otherwise
loading effect will occur.
Discussions : .
1. Name the essential parts of a DAC.
2. How many resistors are required in 12 bit weighted resistor DAC?
3. Why is an inverted R-2R ladder network DAC is bet ter than R-2R
ladder DAC.
4. Define
i) resolution ii) l inearity ii i) monotonicity iv) settling time.
5. Define step size.
Result :
Theoretical values V 0 = V.
Practical Values V 0 = V.
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PINDIAGRAM OF IC74X74:
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elsif(pr1='1' and clr1='0')then
q1
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OUT PUT WAVEFORMS:
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00
1
00
0
00
0
Count
00
1
XL
H
X
L
L
X
LX
H
L
X
X
L
HH
L
X
L
X
L
HH
L
L
X
L
X
Q(3)Q(2)Q(1)Q(0)MS2MS1MR2MR1
TRUTH TABLE:
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AIM: To write the structural program for IC 74x95 SHIFT REGISTER.
APPARATUS: 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bitregister4 isPort ( s : in STD_LOGIC;
cp1 : in STD_LOGIC;
cp2 : in STD_LOGIC;
ds : in STD_LOGIC;d : in STD_LOGIC_vector(0 to 3);
q : input STD_LOGIC_vector(0 to 3));
end bitregister4;
architecture Behavioral of bitregister4 is
begin
process(s,cp1,cp2,ds,d)
begin
if(s='1') then
if(cp2='0' and cp2'event) then
q
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else
if(cp1='0' and cp1'event) then
q
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PIN DIAGRAM:
CIRCUITDIAGRAM:
74
IC74X138
G1
G2A
G2B
A
B
C
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
G1
G2A_L
G2B_L
A
B
C
Y0_L
Y1_L
Y2_L
Y3_L
Y4_L
Y5_L
Y6_L
Y7_L
G1
G2A_L
G2B_L
A
B
C
Y0_L
Y1_L
Y2_L
Y3_L
Y4_L
Y5_L
Y6_L
Y7_L
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AIM: Write a VHDL code for IC74138-3X8 Decoder
APPARATUS: 1.XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM:
VHDL CODE FOR 3 t0 8 DECODER-BEHAVIORAL MODEL IC-
74138
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dec3to8_beh isPort ( g1 : in STD_LOGIC;g2a_l : in STD_LOGIC;
g2b_l : in STD_LOGIC;
a : in STD_LOGIC_vector(2 downto 0);
y_l : out STD_LOGIC_vector(0 to 7));
end dec3to8_beh;
architecture Behavioral of dec3to8_beh is
TRUTH TABLE:
75
EX NO: IC 74X138-3x8 DECODER DATE:
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OUTPUT WAVEFORM:
begin
process (g1,g2a_l,g2b_l,a)
76
G1 G2A_L G2B_L C B A Y7_L Y6_L Y5_L Y4_L Y3_L Y2_L Y1_L Y0_L
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 11 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1
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begin
if (g1='0' and g2a_l='0' and g2b_l='0')then
y_l
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AIM: Write a VHDL code for IC 74x85 4-bit comparator.
APPARATUS: 1 .XILINX PROJECT NAVIGATOR.
2. MODELSIM SIMULATOR.
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity comparator is
Port(A,B:in STD_LOGIC;
ALTBIN ,AEQBIN,AGTBIN:INOUT STD_LOGIC;
AGTBOUT,AEQBOUT,ALTBOUT:INOUT STD_LOGIC);
End comparator;
Architecture comparator_b of comparator is
Begin
ALTBIN
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Begin
If(A>B)then
ALTBOUT
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LOGIC DIAGRAM OF 8X1 MUX:
A
C
EN_L
D0
D1
D2
D3
D4
D5
D6
D7
B
84
PIN DIAGRAM OF IC 74X151
IC74X151
EN
AB
C
D0
D1
D2
D3
D4
D5D6
D7
EN_L
AB
C
D0
D1
D2
D3
D4
D5
D6
D7
Y_L
YY
Y
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TRUTH TABLE
1
D0
D1
D2
D3
D4
D5
D6
D7
0
D0
D1
D2
D3
D4
D5
D6
D7
X
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
X
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
Y-LYS0S1S2EN_L
OUTPUTSINPUTS
AIM: Write a VHDL code for IC741518x1 multiplexer
APPARATUS:1.XILINX PROJECT NAVIGATOR.2.MODELSIM SIMULATOR.
PROGRAM:library IEEE;
85
EXp NO: IC74X151-8x1 MULTIPLEXER DATE:
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when "000"=>y
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