04/22/23

How to measure Multi-Instruction, Multi-Core

Processor Performance using Simulation

Deepak ShankarDarryl Koivisto

Mirabilis Design Inc.

04/22/23 Mirabilis Design Inc Confidential Slide 5

Multi-Core/Processor Benchmarking Solution Speedup equations that take into account parallel execution

• Speedup_Factor, Multi_Instr_Mhz, Multi_Core_Mhz Modeling Platform that supports multi-instruction, multi-core

topologies using routing tables• Create models for different processor memory, and connectivity

configurations• Scaleable infrastructure for end-users to experiment with their specific

variations Processor Models that support published benchmarks

• Key parameters, multi-instruction per cycle, shared cache• Multiple instances, scriptable pipeline

Ability to correlate baseline results to hardware tests• Interactive and graphical demonstration of the benchmark results• Hundreds of built-in statistics

04/22/23 Mirabilis Design Inc Confidential Slide 9

Multi-Processor Benchmark Model

04/22/23 Mirabilis Design Inc Confidential Slide 10

Detailed Benchmark Results