Download - Hardware Slides 17
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DOC 112: Computer Hardware Lecture 17 Slide 1
Lecture 17
Designing a Central Processor Unit:
Part 1: Architecture and Instructions
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DOC 112: Computer Hardware Lecture 17 Slide 3
The Manual Processor Execution Cycle
Data Stream
Instruction Pt 1
DataData
Instruction Pt2Unused
Insruction Pt 1Data
DataInstruction Pt2
Unused
etc
cC
cRES
cIR
cB
cC
cA
cIR
Idle0
1,0
1,01,0
1,0
1
0
1
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DOC 112: Computer Hardware Lecture 17 Slide 4
Executing Instructions
1. Set the multiplexers so that the correctregisters are connected together
2. Set the arithmetic hardware to compute thecorrect function
3. Provide a clock pulse to the registers that are
to change.
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DOC 112: Computer Hardware Lecture 17 Slide 6
So why not put the two together
SHIFTER
C
A
B
ALU
A
B
CY-in
CY-out
Res
MPX
MPX
1
8
8
8
8
f2 f1 f0s2
select
select
f5 f4 f3
s1
select
select
MDR
c4
c3
c1
c1
IR
c6
PC
MPX+1
c5
s3
MARMPX
c8
Read/Write
Address In
Data In Data Out
MEMORYc7s4
Controller
c0 . . . c8 f0 . . . f5 s0 . . . s4
Go
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Changes to the Maunal Processor
1. The Result register now becomes the MDRready to send data to memory
2. MAR can be loaded direct from memory
3. Memory "data out" separated from "data in",
and always enabled
4. IR bits now used as in ut to the controller
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A Simple Controller
State FunctionIdle Wait for the start signal
1 Set address to get next byte
2 Load the instruction,Set address to get next byte
3 Load Data to Reg A
Set address to get next byte4 Load Data to Regs B and C
Set address to get next byte
5 Load the Instruction
Load Data to Regs C and MDRSet address to get next byte
7 Load Result Address to MAR8 Store the Result
Set Address to get next byte
1,0
1,0
4
3
1,0
1,0
1,0
1,0
1Idle
0
1
2
5
7
81,0
0
1
6
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Have we done the job?
Unfortunately not:-
We will never sell a processor that:
1. Continually needs to read and write to memory 2. Has a large number of execution cycles per
instruction
3. Processes only integers up to 255
4. Has cumbersome 5 byte instructions
We need to find wa s of s eedin it u .
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How can we speed things up
1. Change all the buses from 8 bits to 32 bit,and thus do four times as much in each cycle.
2. Provide local registers which can beprogrammed to store partial results.
3. Reduce the size of the combinatorial logic byputting the ALU and shifter in parallel
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How can we speed things up
4. Design a controller with as small a numberof execution cycles as possible.
5. Remove elaborate carry arrangements, bydoing our arithmetic on big integers
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A real processor at last
IR
c12
PC
MPX
+1
c10
s3
MDR
c14c13
Address
In Data Out
MEMORY
MAR
c11
MPX
s0 s1 s2
select
R0
c0
R3
c3
R2
c2
R1
c1
MPX
select
s4 s5 s6
Internal 32 bit Bus
MASKf5
ALU
A
B
Cin
Cout
Res
f2 f1 f0
select
f4 f3
SHIFTER
select
B
c8
A
c7
C
c9
R6c6
R4
c4
R5
c5
C
Controller
c0 . . . . c14 f0 . . . f5 s0 . . . s
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Problem Break
If we wanted to exchange the contents ofregister R0 and Register R1, what operations
must our processor carry out?
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DOC 112: Computer Hardware Lecture 17 Slide 14
Problem Break
If we wanted to exchange the contents ofregister R0 and Register R1, what operations
must our processor carry out?
AR0 //Load A from R0
R1A,AR1 //Load R1 from A and A from R1
//at the same time!
R0A //Load R0 from A
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DOC 112: Computer Hardware Lecture 17 Slide 15
A few observations
Registers A, B, PC, MAR, MDR, IR and C belongto the hardware designers.
Registers R0, R1, R2, R3, R4, R5 and R can bemanipulated by the programmers.
Most arithmetic operations will no longer require acarry in, so we can set the ALU Cin directly from
the controller if required (eg for an increment
instruction
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DOC 112: Computer Hardware Lecture 17 Slide 16
The Controller Specification
The controller is going to be a sequentialcircuit looking something like this:
F1
F2
F3
E1
E2
E3 During the F states
instructions are fetchedfrom memory
During the E states
instructions are executed
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DOC 112: Computer Hardware Lecture 17 Slide 17
The Controller Specification
The fetch cycle will get one 32 bit instructionfrom the memory.
The execute cycles will make the processorcarry out that instruction.
So, to formalise our specification we need todefine what the instructions will do.
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DOC 112: Computer Hardware Lecture 17 Slide 18
The program instructions
Assembler instructions are decided between thesoftware specialists and the hardware designers.
From the software point of view:
Instructions should be few but very powerful
From the hardware point of view
Instructions should be simple and take only a few clockpulses to execute
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DOC 112: Computer Hardware Lecture 17 Slide 19
Instruction Format
We need to be very precise about our instructionformat so that we can easily interpret it inhardware.
We will assume that there will be 255 or lessinstructions, and the top eight bits will define theinstruction.
Most instructions will act on a register, so we willlet the next four bits define the destination register.
31 24 23 20 19 0
Opcode Rdest
31 24 23 0
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DOC 112: Computer Hardware Lecture 17 Slide 21
The function of the Mask is revealed
The memory reference instructions
contain a memory address in thebottom 20 bits.
The mask converts this unsigned 20bit number to a 32 bit number by
masking the top bits.
I32
.
.
.I21
I20I19
.
.
.
I1I0
O32
O21
O20O19
O1O0
Gnd
31 24 23 20 19 0
Opcode Rdest Address
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DOC 112: Computer Hardware Lecture 17 Slide 22
Memory Reference Instructions
20 bit addresses are a little small - they can only
address 4M, so we introduce indirect addressing.Indirect instructions are slower, but make things
easier for the software department.
LOADINDIRECT Reg1, Reg2
STOREINDIRECT Reg1, Reg2
JUMPINDIRECT Reg
CALLINDIRECT Reg1, Reg2
31 24 23 20 19 16 15 0
Opcode Rdest UnusedRsrc
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DOC 112: Computer Hardware Lecture 17 Slide 23
Two Register internal Instructions
MOVE Rdest, RscrADD Rdest, Rscr
SUBTRACT Rdest, Rscr
AND Rdest, RscrOR Rdest, Rscr
XOR Rdest, Rscr
COMPARE Rdest, Rscr(Subtract but without storing the result)
31 24 23 20 19 16 15 0
Opcode Rdest UnusedRsrc
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DOC 112: Computer Hardware Lecture 17 Slide 24
One Register Instructions
CLEAR Rdest INCREMENT (INC Rdest)
DECREMENT (DEC Rdest)
COMPLEMENT (COMP Rdest)
ARITHMETIC SHIFT LEFT (ASL Rdest)
ARITHMETIC SHIFT RIGHT (ASR Rdest)
ROTATE RIGHT (ROR Rdest)
RETURN31 24 23 20 19 0
Opcode Rdest Unused
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DOC 112: Computer Hardware Lecture 17 Slide 25
No Register Instructions
SKIP Following an arithmetic or compare operation
SKIPPOSITIVE
SKIPNEGATIVE and
NOP
These are ver wasteful of memor !
31 24 23 0
Opcode Unused
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DOC 112: Computer Hardware Lecture 17 Slide 26
Input and Output
Input and output will be achieved using theLOAD and STORE instructions.
Many peripherals, disks, serial ports, etc canbe read or written to as if they were memory.
They can also be connected directly with thememory so that input and output can be done
while the rocessor is otherwise en a ed.
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DOC 112: Computer Hardware Lecture 17 Slide 27
Register Transfers
We continue our design, by determining theregister transfers that will be needed to carry
out each instruction.
These register transfers will become the formal
specification of the processor controller.
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DOC 112: Computer Hardware Lecture 17 Slide 28
Register Transfers and processor operation
At each step of the the execution cycle a
number of register transfers take place.
In the fetch steps the register transfers are
always the same.
In the execute steps the register transfers
depend on the instruction being executed.
F1
F2F3
E1
E2
E3
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DOC 112: Computer Hardware Lecture 17 Slide 29
Fetch Register Transfers
In this version of the processor the MDR is the only
register connected to the memory data out bus. Three
states are required to fetch an instruction:
F1: MARPC; PCPC+1 F2: MDRMemory
F3: IRMDR
After F3 has finished the instruction is in both IR and
MDR
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DOC 112: Computer Hardware Lecture 17 Slide 30
Memory Reference Instructions
31 24 23 20 19 0
Opcode Rdest Address
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DOC 112: Computer Hardware Lecture 17 Slide 31
Indirect Memory Reference Instructions
31 24 23 20 19 16 15 0
Opcode Rdest UnusedRsrc
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DOC 112: Computer Hardware Lecture 17 Slide 32
Two Register Instructions
31 24 23 20 19 16 15 0
Opcode Rdest UnusedRscr
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DOC 112: Computer Hardware Lecture 17 Slide 33
One Register Instructions
31 24 23 20 19 0
Opcode Rdest Unused
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DOC 112: Computer Hardware Lecture 17 Slide 34
No Register Instructions
The NOP instruction doesnt even need one cycle
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To be continued
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