![Page 1: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/1.jpg)
William Stallings Computer Organization
and Architecture7th Edition
Chapter 12CPU Structure and Function
Group 5
Alain J. PercialPaula A. OrtizFrancis X. Ruiz
![Page 2: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/2.jpg)
Program Status Word (PSW)
Many processors include registers, known as the PSW , which contain status information such as condition codes plus other status information. Common fields include:
A set of bits Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor
![Page 3: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/3.jpg)
CPU Structure
The CPU consists of several sections and it must do the following:› Fetch instructions: The CPU reads an instruction from the
memory. › Interpret instructions: Decoding determines what action will
be taken.› Fetch data: Sends a control signal to and receives control
signals from other devices.› Process data: Where an instruction may need performing
arithmetic or logical operation on the data. › Write data: Depending on the performance it may require
writing data to memory or an I/O module. A CPU is known to carry out instructions and makes the rest of
the computer carry out their task.
![Page 4: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/4.jpg)
CPU With Systems Bus
![Page 5: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/5.jpg)
CPU Internal Structure
![Page 6: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/6.jpg)
Registers
A register is a small amount of available storage on the CPU where it can be reached quickly.
They are special memory used by the CPU for temporarily storing data during execution of instruction.
Number and function vary between processor designs among registers.
Registers are measured by the number of bits they can hold, for example, we call a register holding 8 bits an 8 bit register.
Registers have top level of memory hierarchy.
![Page 7: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/7.jpg)
User Visible Registers
User Visible Registers are those that can be referenced by the machine language that the processor executes.
They enable the machine to minimize main memory references by modifying the use of registers.
General Purpose: can be assigned to a variety of functions.
Data: used to hold data and cannot be employed in the calculation of an operand address.
Address: can be general purpose or can be for one particular addressing mode.
Condition Codes: also called flags, they are bits set by the processor hardware due to the operations.
![Page 8: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/8.jpg)
Control & Status Registers
In order to control the operation of the processor, there are a few registers that are to be used.
Program Counter(PC): PC contains the action that will be fetched either the address of the instruction being executed, or the address of the next instruction to be executed.
Instruction Register(IR): It contains the instruction currently being executed.
Memory Address Register(MAR): Contains the address of a location in memory.
Memory Buffer Register(MBR): It stores the data being transferred to and from the immediate access store.
![Page 9: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/9.jpg)
Control Registers
![Page 10: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/10.jpg)
INSTRUCTION CYCLE
An instruction cycle is the sequence of actions that the CPU performs to execute each machine code instruction in a program.
![Page 11: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/11.jpg)
It includes the following subcycles:
Fetch: Read the next instruction from memory to processor.
Execute: Interpret the opcode and perform the indicated operation.
• May take many forms; it depends on instruction being executed.
• May include:• Memory read/write• Input/Output• Register transfers• ALU operations
Interrupt: If enabled and it has occurred, save process state and service the interrupt.
![Page 12: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/12.jpg)
Indirect Cycle The execution of an instruction may
involve one or more operant in memory, each of which requires memory access
Indirect addressing is used, then additional memory accesses are required.
Can be thought of as additional instruction subcycle
![Page 13: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/13.jpg)
Instruction Cycle with Indirect
![Page 14: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/14.jpg)
Instruction Cycle State Diagram
![Page 15: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/15.jpg)
Data Flow• Fetch Cycle• Indirect Cycle• Interrupt Cycle
![Page 16: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/16.jpg)
FETCH CYCLEDepends on CPU design.
![Page 17: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/17.jpg)
INDIRECT CYCLEIf indirect addressing, indirect cycle is performed.
![Page 18: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/18.jpg)
INTERRUPT CYCLEIs simple and predictable.Current Program Counter is saved to allow resumption after interrupt.
![Page 19: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/19.jpg)
PREFETCH It’s a technique used in microprocessors to speed up
the execution of a program by reducing wait states.
Prefetching occurs when a processor requests an instruction from main memory before it is actually needed. Once the instruction comes back from memory, it is placed in a cache. When an instruction is actually needed, the instruction can be accessed much more quickly from the cache than if it had to make a request from memory.
Since programs are generally executed sequentially, performance is likely to be best when instructions are prefetched in program order.
![Page 20: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/20.jpg)
Instruction Pipeline
![Page 21: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/21.jpg)
What is an Instruction Pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase the instructions that can be executed in a unit of time.
![Page 22: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/22.jpg)
Pipelining
Fetch instruction Decode instruction Calculate operands (i.e. EAs) Fetch operands Execute instructions Write result
Overlap these operations
![Page 24: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/24.jpg)
What are branches?
A branch (or jump on some computer architectures, such as the PDP-8 and Intel x86) is a point in a computer program where the flow of control is altered.
The term branch is usually used when referring to a program written in machine code or assembly language.
In a high-level programming language, branches usually take the form of conditional statements, subroutine calls or GOTO statements.
![Page 25: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/25.jpg)
Six Stage Instruction Pipeline
![Page 26: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/26.jpg)
Alternative Pipeline Depiction
![Page 27: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/27.jpg)
Dealing with Branches
Multiple Streams Prefetch Branch Target Loop buffer Branch prediction Delayed branching
![Page 28: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/28.jpg)
Multiple Streams
Have two pipelines Prefetch each branch into a separate
pipeline Use appropriate pipeline
Leads to bus & register contention Multiple branches lead to further
pipelines being needed
![Page 29: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/29.jpg)
Prefetch Branch Target
Target of branch is prefetched in addition to instructions following branch
Keep target until branch is executed Used by IBM 360/91
![Page 30: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/30.jpg)
Loop Buffer
Very fast memory Maintained by fetch stage of pipeline Check buffer before fetching from
memory Very good for small loops or jumps c.f. cache Used by CRAY-1
![Page 31: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/31.jpg)
Loop Buffer Diagram
![Page 32: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/32.jpg)
Branch Prediction (1)
Predict never taken› Assume that jump will not happen› Always fetch next instruction › 68020 & VAX 11/780› VAX will not prefetch after branch if a page
fault would result (O/S v CPU design) Predict always taken
› Assume that jump will happen› Always fetch target instruction
![Page 33: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/33.jpg)
Branch Prediction (2)
Predict by Opcode› Some instructions are more likely to result
in a jump than thers› Can get up to 75% success
Taken/Not taken switch› Based on previous history› Good for loops
![Page 34: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/34.jpg)
Branch Prediction (3)
Delayed Branch› Do not take jump until you have to› Rearrange instructions
![Page 35: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/35.jpg)
Branch Prediction Flowchart
![Page 36: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/36.jpg)
Dealing With Branches
![Page 37: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/37.jpg)
Intel 80486 Pipelining
Fetch› From cache or external memory› Put in one of two 16-byte prefetch buffers› Fill buffer with new data as soon as old data consumed› Average 5 instructions fetched per load› Independent of other stages to keep buffers full
Decode stage 1› Opcode & address-mode info› At most first 3 bytes of instruction› Can direct D2 stage to get rest of instruction
Decode stage 2› Expand opcode into control signals› Computation of complex address modes
Execute› ALU operations, cache access, register update
Writeback› Update registers & flags› Results sent to cache & bus interface write buffers
![Page 38: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/38.jpg)
80486 Instruction Pipeline Examples
![Page 39: Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz](https://reader036.vdocuments.us/reader036/viewer/2022062314/56649da75503460f94a92cbe/html5/thumbnails/39.jpg)
Questions
1. What is a small amount of available storage on the CPU where it can be reached quickly?
2. What must the CPU do?3. Does a memory buffer register store data being
transferred to and from the immediate access store4. What is an instruction cycle?5. Is additional memory access required if indirect cycles
are used?6. What is prefetching?7. What is a pipeline?8. What is a branch?9. Can unconditional branches be ignored?10. What is loop buffer used for?