A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
BOM P/N :
PCB NO :
COMPAL CONFIDENTIAL
MODEL NAME :
Goliad MLK 12" UMA
REV : 0.3 (X01) @ : Nopop Component
Goliad MLK 12 UMA
2013-12-23
CONN@ : Connector Component
Broadwell U Processor
LA-A971P
4319RJ31LXX
GPIO MAP: 3.3b
EMC@ : EMI, ESD and RF Component
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
CXDP@ : XDP Component@EMC@ : EMI, ESD and RF Nopop Component
VPRO@ : Vpro ComponentLayout Dell logo
COPYRIGHT 2013ALL RIGHT RESERVEDREV: X01PWB: 89XM3DATE: 1351-05
NVPRO@ : Non-Vpro Component
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Cover Sheet
1 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Cover Sheet
1 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Cover Sheet
1 48Wednesday, March 19, 2014
Compal Electronics, Inc.
Part Number Description
DAA00083000 PCB 14A LA-A971P REV0 MB WITH DOCKING 2
MB PCB
Part Number Description
DAA00083000 PCB 14A LA-A971P REV0 MB WITH DOCKING 2
MB PCB
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCI Express BUS
PCIE1
HD Audio I/F
Universal Jack
Automatic Power
Switch (APS)
CPU XDP Port
Power On/Off
SW & LED
DC/DC Interface
Memory BUS (DDR3L)
BANK 0, 1, 2, 3
DDR3L-DIMM X2Goliad MLK 12 UMA Block Diagram
KB/TP CONN
BCM5882
USHSmart Card
RFID
Dig. MIC
INT.Speaker
ALC3235HDA Codec
Intel Clarkville
I218LM
TDA8034HN
eDP CONN
SP
I
INTEL
BROADWELL ULT
SATA1
BC BUS
Fingerprint
CONNFP_USB
SMSC KBC
MEC5085
WLAN/BT/
1333/1600MHz
W25Q32BVSSIQ
64M 4K sector
32M 4K sector
W25Q64CVSSIQ
SD4.0O2 Micro OZ777FJ2LN
Card reader
Discrete TPMECE5048
SMSC SIO
USH board
AT97SC3205
PAGE 29 PAGE 29
PAGE 36PAGE 36
PAGE 35
PAGE 37
PAGE 27
PAGE 7
PAGE 21
PAGE 21
WIGIG
PAGE 23
PAGE 28
PCIE3 PCIE4
Dual Lane eDP1.3
DDI2
FAN CONN
USB2.0[6]
PAGE 9
PAGE 9
PAGE 39
PAGE 38
PAGE 30
PAGE 6~17
PAGE 18 19
PAGE 23
Trough eDP Cable
Camera
PAGE 27
LPC
PAGE 24
mDP CONN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Transformer
RJ45
PAGE 28
PAGE 28
PAGE 21
USH CONNPAGE 27
USB2.0[2]
PCIE5_L0
WIGIG_DP
DDI1
Reverse Type
LID switch
LCD Touch
PAGE 23
WWAN/LTE
PAGE 30
USB2.0[7]
Trough eDP Cable
PCIE6_L1
WIGIG_DP
Parade
PS8338IDT
VMM3320
PAGE 22
DOCKING
CONN
PAGE 34
DP
DP
DP
SATA1
DAI
DOCK_USB3.0[3]
DOCK_USB2.0[0]
DOCK_USB2.0[5]
LAN
HDMI CONNPAGE 24
PAGE 26
VGAParade
PS8339PAGE 25
DP
HDMI
USB
USB2.0[4]
PAGE 32USB3.0/2.0USB3.0[2]
USB2.0[1]
PCIE6_L0
USB2.0[5]
PAGE 20Near Field
Communications con
SIM+HALL/BFull Mini Card
mSATAPAGE 20
USB3.0/2.0+PSTPS2544
USB POWER SHAREPAGE 31
DOCK _USB2.0[0]
PI3USB3102
PAGE 31
USB3&2 Switch
SW_USB2.0[3]
SW_USB2.0[0]
USB3.0[1]
USB2.0[0]
NX3DV221
PAGE 31
USB20 SwitchDOCK _USB2.0[3]
SW_USB3.0[1]
DOCK_USB3.0[1]
PAGE 31USB3.0/2.0
USB2.0[0]_PS
USB2.0[3]
USB3.0[4]
DOCKED
DOCKED_LIO_EN
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Block diagram
2 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Block diagram
2 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Block diagram
2 48Wednesday, March 19, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PM TABLE
PCIE
PCIE 1
PCIE 2
PCIE 3
POWER STATES
PCIE 4
PCIE 5
LOM
+3.3V_M +3.3V_M
(M-OFF)
ON
ON
ON
ON
OFF
OFF
OFFOFF
+3.3V_SUS+5V_ALW +5V_RUN
+3.3V_ALW_PCH
+1.35V_MEM
S0
S3
S5 S4/AC doesn't exist
ON
powerplane
S5 S4/AC
State
OFFON
ON
ON
ON ON
OFF
OFF
OFF
OFFOFF
+3.3V_RTC_LDO
+1.05V_M
WLAN + BT
CAMERA
USH
2
3
1
4
USB PORT#
0
DESTINATION
6
5
7
BDWULT
+1.05V_M+3.3V_RUN
+0.675V_DDR_VTT
+VCC_CORE
+1.05V_RUN
WLAN - JNGFF1
JDOCK1
SATA
SATA 0
DESTINATION
JMINI3SATA 1
SATA 2
SATA 3
0
1
BIO
NAUSH
JUSB2 or DOCK2
JUSB3
OFF
OFF
OFF
LOW
LOW
OFF
OFF
S0 (Full ON) / M0
SLP S3#
SLPS5#
HIGH
Signal
State
SLPS4#
HIGH HIGH
ALWAYSPLANE
ON
MPLANE
ON
SUSPLANE
RUNPLANE
CLOCKS
ON ON ON
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
SLPA#
HIGH
HIGH
LOW HIGH HIGH
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S5 (SOFT OFF) / M-OFF
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
S4 (Suspend to DISK) / M-OFF HIGH
JUSB3-->Right
JUSB1-->Rear left
JUSB2-->Rear Right
USB3.0
USB3.0 1
USB3.0 2
USB3.0 4
+3.3V_ALW
MMI (CARD READER)
PCIE 6
JUSB1 or DOCK1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
SATA Cache - JNGFF2
HCA & SATA Cache - JNGFF2
USB3.0 3
Touch Screen
WWAN
WiGig - JNGFF1
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Port assignment
3 40Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Port assignment
3 40Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Port assignment
3 40Wednesday, March 19, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BATTERY +PWR_SRC
ADAPTERFDC654P
+BL_PWR_SRCEN_INVPWR
CHARGER
+3.3V_ALW
TPS51285+5V_ALW
ALWON
RU
N_
ON
+3.3V_RUN
(QV1)
(PU100)
+VCC_CORE
ISL95813(PU501)
+1.35V_MEM
SU
S_
ON
0.6
75
V_
DD
R_
VT
T_
ON
RT8207(PU200)
+0.675V_DDR_VTT
+3.3V_SUS
TPS22966
SU
S_
ON
+5V_RUN
RU
N_
ON
H_
VR
_E
N
+3.3V_M
A_
ON
(UZ8) (UZ9)TPS22966
(QZ1)LP2301ALT1G
+3.3V_CAM
TPS22966(UZ7)
RUN_ON
+1.05V_RUN
3.3
V_
CA
M_
EN
#
3.3
V_
WW
AN
_E
N
+3.3V_WWAN
TPS22966(UZ2)
TPS22966
+3.3V_LAN
(UL3)
SIO
_S
LP
_L
AN
#
APL3512(UV24)
EN
_L
CD
PW
R
+LCDVDD
USB_PWR_SHR_EN#
TPS2544
+5V_USB_CHG_PWR
USB_PWR_EN1#
(UI1)G547I2P81U
+USB_SIDE_PWR +USB_RIGHT_PWR
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
+1.05V_M(PU300)SY8208A_ON
3.3
V_
HD
D_
EN
+3.3V_HDD
SI3456(QZ6)
MPHYP_PWR_EN
+1.05V_MODPHY
(UI3)
+3.3V_WLAN
AU
X_
EN
_W
OW
L
(UI2)G547I2P81U
USB_PWR_EN2#
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Power rails
4 40Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Power rails
4 40Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Power rails
4 40Wednesday, March 19, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MEC 5085
MEM_SMBDATA
MEM_SMBCLK
KBC
AH1
AP2
+3.3V_ALW_PCH
2.2K
2.2K
200 DIMMA
202
DIMMB200
202
AN1
AK1
+3.3V_ALW2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
2.2K
B4
A3
1A
1A
A4
B5
2.2K
2.2K
LCD_SMBCLK
LCD_SMDATA1B
1B
1C
1C
B59
A56
+3.3V_ALW2.2K
2.2K
100 ohm
100 ohmBATTERYCONN
7
6PBAT_SMBCLK
PBAT_SMBDAT
3A
1E
1E
2B
2B
B501G
1GA47
B7
A7
+3.3V_ALW2.2K
2.2K
2D
2D
BAY_SMBDAT
BAY_SMBCLK
A49
B52
CARD_SMBCLK
CARD_SMBDAT
+3.3V_ALW2.2K
2.2K
LOM
CHARGER_SMBCLK
CHARGER_SMBDAT Charger
SML1_SMBDATA
BDW
SML1_SMBCLK
AU3AH3
A50
B53
3A
B6A5
+3.3V_ALW_PCH2.2K
2.2K
USH
+3.3V_SUS
USH_SMBCLK
USH_SMBDAT
+3.3V_ALW10K
10K
53
51XDP
M9
L9
9
8
31
28
2N7002
2N7002
2.2K
2.2K
SMBUS Address [0x9a]
+3.3V_ALW
B48
B49
+3.3V_ALW2.2K
2.2K
GPU_SMBDAT
GPU_SMBCLK
2A
2A
1K
SML0CLK
SML0DATA
+3.3V_ALW_PCH1K
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
+3.3V_RUN2.2K
2.2K
4
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
SMbus Block diagram
5 40Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
SMbus Block diagram
5 40Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
SMbus Block diagram
5 40Wednesday, March 19, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
High - Enable Internal VRs
Low - Enable External VRs
INTVRMEN - INTEGRATED SUS 1.05V VRM
ENABLE
CMOS setting
Shunt Clear CMOS
Keep CMOS
TPM setting
Shunt Clear ME RTC Registers
Keep ME RTC Registers
ME_CLR1
Open
CMOS_CLR1
Open
CMOS place near DIMM
CAD note:
Place the resistor within 500 mils of the PCH. Avoid
routing next to clock pins.
SATA Impedance Compensation
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
HDA for Codec
Reserve for EMI
SATA HDD
for DOCK
UMA SATA port
for SATA-CACHE (WWAN)
for PCIe Cache (WWAN)
PCB
G14U_En
G14D_En
G14 UMA
G14 DSC
G12 UMA
SATA2/PCIE6 L1SATA1
M2 3030 WIGIG
E-Dock
SATA0
M2 30422nd PCIe Lane for PCIe Cache
SATA3/PCIE6 L0
G12 EntryNA
E-Dock
E-Dock
NA
NA
mSATA
HDD
HDD
mSATA
mSATA
mSATA
NA NA
M2 3042SATA-Cache(no HCA)
M2 3042(HCA & SATA-Cache)
M2 30422nd PCIe Lane for PCIe Cache
M2 3030 WIGIG
NA
NA
NA
M2 3042(HCA & SATA-Cache)
contact to WWAN
contact to WWAN
SATA2/PCIE6_L1 contact to WWAN
SATA3/PCIE6 L0 contact to WLAN
contact to WLAN
ME_FWP PCH has internal 20K PD.
Service Mode Switch:
Add a switch to ME_FWP signal to unlock the ME region and
allow the entire region of the SPI flash to be updated using FPT.
FLASH DESCRIPTOR SECURITY OVERRIDE
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
PT, ST pop RC2 & SW1; MP pop RC301.
INTRUDER#
ME_FWP
PCH_AZ_BITCLK
PCH_AZ_BITCLK
PCH_AZ_CODEC_SDIN0PCH_AZ_RST#
PCH_AZ_RST#
PCH_AZ_SDOUT
PCH_AZ_SDOUT
PCH_AZ_SYNC
PCH_AZ_SYNC
PCH_INTVRMEN
PCH_INTVRMEN
PCH_JTAG_JTAGX
PCH_JTAG_TCK
PCH_JTAG_TCK
PCH_JTAG_TDIPCH_JTAG_TDOPCH_JTAG_TMS
PCH_JTAG_TRST#
PCH_RTCRST#
PCH_RTCX1PCH_RTCX1_R
SATA_ACT#SATA_COMP
SATA_COMP
SRTCRST#
PCH_RTCX2
SATA2_PCIE6_L1
MPCIE_RST#
HDD_DET#MPCIE_RST#
ME_FWP
PCH_JTAG_TDOPCH_JTAG_TMSPCH_JTAG_TDI
PM_TEST_RST
ME_FWPME_FWP_EC
+RTC_CELL
+RTC_CELL
+PCH_ASATA3PLL
+PCH_ASATA3PLL
+3.3V_RUN
+1.05V_M
+3.3V_ALW_PCH
+1.05V_M
PCH_AZ_CODEC_SDIN0<21>
PCH_AZ_CODEC_SYNC<21>
PCH_AZ_CODEC_BITCLK<21>
PCH_AZ_CODEC_RST#<21>
PCH_AZ_CODEC_SDOUT<21>
SATA_ACT# <39>
PCH_JTAG_TDI<9>PCH_JTAG_TDO<9>PCH_JTAG_TMS<9>
PCH_RTCRST#<9>
PCH_JTAG_TCK<9>PCH_JTAG_TRST#<9>
PCH_JTAG_JTAGX<9>
SATA_PTX_DRX_P1 <20>SATA_PTX_DRX_N1 <20>SATA_PRX_DTX_P1 <20>SATA_PRX_DTX_N1 <20>
SATA_PTX_DKRX_P0_C <34>SATA_PTX_DKRX_N0_C <34>SATA_PRX_DKTX_P0_C <34>SATA_PRX_DKTX_N0_C <34>
PCIE_PTX_SATARX_P6_L0 <30>PCIE_PTX_SATARX_N6_L0 <30>PCIE_PRX_SATATX_P6_L0 <30>PCIE_PRX_SATATX_N6_L0 <30>
PCIE_PTX_SATARX_P6_L1 <30>PCIE_PTX_SATARX_N6_L1 <30>PCIE_PRX_SATATX_P6_L1 <30>PCIE_PRX_SATATX_N6_L1 <30>
HDD_DET# <20>SATA2_PCIE6_L1 <12,35>mCARD_PCIE#_SATA <36,7>
DGPU_PWROK<10>
ME_FWP_EC<36>
MMICLK_REQ#<29,7>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (1/12)
6 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (1/12)
6 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (1/12)
6 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RPC18
10K_8P4R_5%
RPC18
10K_8P4R_5%
12345
678
RC9 1M_0402_5%RC9 1M_0402_5%1 2
CC100
1U_0402_6.3V6K
@CC100
1U_0402_6.3V6K
@
12
RC11 1K_0402_5%RC11 1K_0402_5%1 2
RC301 0_0402_5%@RC301 0_0402_5%@12
CC2
12P_0402_50V8J
CC2
12P_0402_50V8J
1 2
SW1
SS3-CMFTQR9_3P
SW1
SS3-CMFTQR9_3P
A1
B2
C3
G14
G25
CC1
12P_0402_50V8J
CC1
12P_0402_50V8J
1 2
RC10 20K_0402_5%RC10 20K_0402_5%1 2
RC21@ 51_0402_5%RC21@ 51_0402_5%12
RC
71
0M
_0
40
2_
5%
RC
71
0M
_0
40
2_
5%
12
CC4 1U_0402_6.3V6KCC4 1U_0402_6.3V6K1 2
BDW_ULT_DDR3L
JTAG
RTC
AUDIO SATA
5 OF 19
UC1E
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
JTAG
RTC
AUDIO SATA
5 OF 19
UC1E
BDW-ULT-DDR3L_BGA1168
RSVDL11
RSVDK10
PCH_TMSAD62 PCH_TDOAE61 PCH_TDIAD61 PCH_TCKAE62 PCH_TRSTAU62
HDA_DOCK_RST/I2S1_SFRMAV10 HDA_DOCK_EN/I2S1_TXD
AW10
HDA_SDI1/I2S1_RXDAU12
HDA_SDO/I2S0_TXDAU11
HDA_SDI0/I2S0_RXDAY10 HDA_RST/I2S_MCLKAU8 HDA_SYNC/I2S0_SFRM
AV11 HDA_BCLK/I2S0_SCLKAW8
RSVDAC4 RSVD
AL11
RSVDAV2
I2S1_SCLKAY8
SATALEDU3
JTAGXAE63
RTCX2AY5
SATA_RCOMPC12
SATA_IREFA12
SATA3GP/GPIO37AC1SATA2GP/GPIO36V6SATA1GP/GPIO35U1SATA0GP/GPIO34V1
SATA_TP3/PETP6_L0D17SATA_TN3/PETN6_L0C17SATA_RP3/PERP6_L0E5SATA_RN3/PERN6_L0F5
SATA_TP2/PETP6_L1C15SATA_TN2/PETN6_L1B14
SATA_RN2/PERN6_L1J6
SATA_RP2/PERP6_L1H6
SATA_TP1/PETP6_L2B17SATA_TN1/PETN6_L2A17
SATA_RN1/PERN6_L2J8
SATA_RP1/PERP6_L2H8
SATA_TP0/PETP6_L3A15SATA_TN0/PETN6_L3B15SATA_RP0/PERP6_L3H5SATA_RN0/PERN6_L3J5
RTCX1AW5
RTCRSTAU7 SRTCRSTAV6 INTVRMENAV7 INTRUDERAU6
RC18@ 1K_0402_1%RC18@ 1K_0402_1%12
RC20 33_0402_5%RC20 33_0402_5%1 2
CC3 1U_0402_6.3V6KCC3 1U_0402_6.3V6K1 2
CMOS1@
SHORT PADS~DCMOS1@
SHORT PADS~D
11
22
CC
5@
EM
C@
27
P_
04
02
_5
0V
8J
CC
5@
EM
C@
27
P_
04
02
_5
0V
8J
12
RC4@ 0_0402_5%RC4@ 0_0402_5%1 2
RC19 33_0402_5%RC19 33_0402_5%1 2
RC
1330K
_0402_5%
RC
1330K
_0402_5%
12
RC23 33_0402_5%EMC@
RC23 33_0402_5%EMC@1 2
YC132.768KHZ_12.5PF_9H03220008
YC132.768KHZ_12.5PF_9H03220008
12
RC8 20K_0402_5%RC8 20K_0402_5%1 2
RPC21
51_0804_8P4R_5%
RPC21
51_0804_8P4R_5%
18273645
RC22 33_0402_5%RC22 33_0402_5%1 2
RC173.01K_0402_1% RC173.01K_0402_1%1 2
RC300
10K_0402_5%
@RC300
10K_0402_5%
@
1 2
RC2
1K_0402_5%
RC2
1K_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
support SPI TPM
LPC_0 LPC_1 LPC_0 LPC_1
support LPC TPM
SIO
MEC
DOCK
DEBUGSIO
MEC
TPM
DOCK
DEBUG
CLKBUFF
WLAN (NGFF1)--->
10/100/1G LAN --->
MMI --->
PCIECLK for UMA
WGIG (NGFF1)--->
HCA/PCIe cache (NGFF2)--->
PCB
G14U_En
G14D_En
G14 UMA
G14 DSC
G12 UMA
PCIE3PCIE2
SD card
PCIE1 PCIE4
G12 Entry NA
NA
WIGIG
WIGIGSD card
SD card
SD card
SD card
SD card
NA
NA
NA
NA
NA
NA LOM
LOM
LOM
LOM
LOM
LOM
WLAN
WLAN
WLAN
WLAN
WLAN
WLAN
PCIE5
GPU
WIGIG
GPU
WIGIG
PCIE6
WIGIG
WIGIG
M2 3042(HCA & SATA-Cache)
M2 3042(HCA & SATA-Cache)
to SPI ROMfrom CPU
32Mb Flash ROM
64Mb Flash ROM
SOFTWARE TAA
Reserve for EMI
MP Depop RC70.
CLK_BIASREF
CLK_BIASREF
LPC_LAD0LPC_LAD1LPC_LAD2LPC_LAD3LPC_LFRAME#
MCP_TESTLOW1
MCP_TESTLOW1
MCP_TESTLOW2
MCP_TESTLOW2
MCP_TESTLOW3
MCP_TESTLOW3
MCP_TESTLOW4
MCP_TESTLOW4
MEM_SMBCLK
MEM_SMBCLK
MEM_SMBDATA
MEM_SMBDATA
PCH_CL_CLK1PCH_CL_DATA1PCH_CL_RST1#
PCH_SPI_CLKPCH_SPI_CS0#PCH_SPI_CS1#
PCH_SPI_DINPCH_SPI_DO
PCH_SPI_DO2PCH_SPI_DO3
PCI_CLK_LPC_0
SML0_SMBCLK
SML0_SMBDATA
SML1_SMBCLKSML1_SMBDATA
SPI_CLK32 SPI_CLK64
XTAL24_INXTAL24_OUT
PCI_CLK_LPC_0
XTAL24_OUT_R
PCI_CLK_LPC_1
PCI_CLK_LPC_1
LANCLK_REQ#
WLANCLK_REQ#
MMICLK_REQ#
WIGIGCLK_REQ#
PCH_SPI_CS2#
PCH_GPIO19
SML0_SMBCLK
SML0_SMBDATA
SML0_SMBCLKSML0_SMBDATA
SPI_PCH_DO
SPI_PCH_DIN
SPI_PCH_CLK
SPI_PCH_CS1#
SPI_PCH_DO2
SPI_PCH_CS0#
SPI_PCH_DO3PCH_SPI_DO3
PCH_SPI_DIN
PCH_SPI_DO2
PCH_SPI_CS0#
PCH_SPI_DO
PCH_SPI_CS1#
PCH_SPI_CLK
SPI_PCH_CS1#
SPI_PCH_CS0#
SPI_CLK64
SPI_CLK32SPI_PCH_DO3_32
SPI_PCH_DO2_64
SPI_PCH_DO2_32
SPI_PCH_CS1#_R
SPI_PCH_CS0#_R
SPI_DO64
SPI_DO32
SPI_DIN64
SPI_DIN32
SPI_PCH_DO3_64
SPI_PCH_DO2 SPI_PCH_DO2_64
SPI_PCH_DO2 SPI_PCH_DO2_32
SPI_PCH_DO2
SPI_PCH_DO3
SPI_PCH_DO3_32
SPI_PCH_DINSPI_PCH_DOSPI_PCH_CLKSPI_PCH_DO3
SPI_PCH_CLKSPI_PCH_DO
SPI_PCH_DO3
SPI_PCH_DINSPI_DO64SPI_CLK64SPI_PCH_DO3_64
SPI_DIN64
SPI_DIN32SPI_DO32SPI_CLK32
MEM_SMBCLKMEM_SMBDATA
SML1_SMBCLKSML1_SMBDATA
LANCLK_REQ#
DDR_XDP_WAN_SMBCLK
DDR_XDP_WAN_SMBDAT
CLK_PCI_MEC
CLK_PCI_SIO
CLK_PCI_LPDEBUG
CLK_PCI_DOCK
+PCH_VCCACLKPLL
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_M+3.3V_SPI
+3.3V_SPI
+3.3V_SPI
+3.3V_SPI
+3.3V_RUN
LPC_LAD0<20,35,36>LPC_LAD1<20,35,36>LPC_LAD2<20,35,36>LPC_LAD3<20,35,36>
LPC_LFRAME#<20,35,36>
DDR_XDP_WAN_SMBDAT <18,19,9>
DDR_XDP_WAN_SMBCLK <18,19,9>
SML1_SMBDATA <36>SML1_SMBCLK <36>PCH_GPIO73 <12>
CLK_PCI_MEC <36>
CLK_PCI_SIO <35>
PCH_CL_CLK1 <30>PCH_CL_DATA1 <30>
PCH_CL_RST1# <30>
CLK_PCI_LPDEBUG <20,36>
CLK_PCI_DOCK <34>
PCH_SMB_ALERT# <11>
CLK_PCIE_WLAN#<30>CLK_PCIE_WLAN<30>
CLK_PCIE_LAN#<28>CLK_PCIE_LAN<28>
CLK_PCIE_MMI#<29>CLK_PCIE_MMI<29>
CLK_PCIE_WIGIG#<30>CLK_PCIE_WIGIG<30>
CLK_PCIE_SATA#<30>CLK_PCIE_SATA<30>
PCH_SPI_CS2#<27>
MMICLK_REQ#<29,6>
LANCLK_REQ#<28>
WLANCLK_REQ#<12,30>
WIGIGCLK_REQ#<12,30>
SATACLK_REQ#<30>
PCH_SPI_CLK<27>
PCH_SPI_DO<27>PCH_SPI_DIN<27>
LAN_SMBDATA <28>
LAN_SMBCLK <28>
mCARD_PCIE#_SATA <36,6>PCH_GPIO16 <12>
CONTACTLESS_DET# <10,27>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (2/12)
7 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (2/12)
7 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (2/12)
7 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RC65@ 0_0402_5%RC65@ 0_0402_5%1 2
UC3
W25Q32FVSSIQ_SO8
VPRO@UC3
W25Q32FVSSIQ_SO8
VPRO@
/CS1
DO/IO12
/WP/IO23
GND4
DI/IO05CLK6/HOLD/IO37VCC8
RC224 0_0402_5%RC224 0_0402_5%12
RC
62
@E
MC
@
33
_0
40
2_
5%
RC
62
@E
MC
@
33
_0
40
2_
5%
12
RPC11
33_0804_8P4R_5%
RPC11
33_0804_8P4R_5%
1 82 73 64 5
RC
61
@E
MC
@
33
_0
40
2_
5%
RC
61
@E
MC
@
33
_0
40
2_
5%
12
CC
10
@E
MC
@
33
P_
04
02
_5
0V
8J
CC
10
@E
MC
@
33
P_
04
02
_5
0V
8J
12
RC227 0_0402_5%RC227 0_0402_5%12
CC1533P_0402_50V8J @EMC@
CC1533P_0402_50V8J @EMC@
12
RC70EMC@ 22_0402_5%RC70EMC@ 22_0402_5%1 2
RC29 1K_0402_5%RC29 1K_0402_5%1 2
UC2
W25Q64FVSSIQ_SO8
UC2
W25Q64FVSSIQ_SO8
/CS1
DO(IO1)2
/WP(IO2)3
GND4
DI(IO0)5CLK6/HOLD(IO3)7VCC8
CC1433P_0402_50V8J @EMC@
CC1433P_0402_50V8J @EMC@
12
YC224MHZ_12PF_X3G024000DC1H
YC224MHZ_12PF_X3G024000DC1H
1 23 4
RC226 0_0402_5%RC226 0_0402_5%12
BDW_ULT_DDR3L
LPCSMBUS
C-LINKSPI
7 OF 19
UC1G
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
LPCSMBUS
C-LINKSPI
7 OF 19
UC1G
BDW-ULT-DDR3L_BGA1168
CL_RSTAF4CL_DATAAD2CL_CLKAF2
SML1CLK/GPIO75AU3
SML1DATA/GPIO74AH3
SML1ALERT/PCHHOT/GPIO73AU4SML0DATAAK1SML0CLKAN1
SMBDATAAH1
SML0ALERT/GPIO60AL2
SMBCLKAP2SMBALERT/GPIO11AN2
SPI_IO3AF1 SPI_IO2
Y6 SPI_MISOAA4 SPI_MOSIAA2 SPI_CS2AC2 SPI_CS1
Y4
SPI_CLKAA3
SPI_CS0Y7
LFRAMEAV12 LAD3
AW11 LAD2AY12 LAD1
AW12 LAD0AU14
RC38 33_0402_5%RC38 33_0402_5%1 2
RC72EMC@ 22_0402_5%RC72EMC@ 22_0402_5%1 2
RC74EMC@ 22_0402_5%RC74EMC@ 22_0402_5%1 2
CC1333P_0402_50V8J @EMC@
CC1333P_0402_50V8J @EMC@
12
RPC6
10K_8P4R_5%
RPC6
10K_8P4R_5%
1234 5
678
RC230 0_0402_5%RC230 0_0402_5%12
RC31 1K_0402_5%RC31 1K_0402_5%1 2
RC34499_0402_1% RC34499_0402_1%12
RC
63
1M
_0
40
2_
5%
RC
63
1M
_0
40
2_
5%1
2
RC228 0_0402_5%RC228 0_0402_5%12
RC35 0_0402_5%@RC35 0_0402_5%@1 2
RC55 33_0402_5%VPRO@RC55 33_0402_5%VPRO@
1 2
RC693.01K_0402_1% RC693.01K_0402_1%1 2
RPC12
33_0804_8P4R_5%
VPRO@RPC12
33_0804_8P4R_5%
VPRO@
1 82 73 64 5
RC30 0_0402_5%@RC30 0_0402_5%@12
RC229 0_0402_5%RC229 0_0402_5%12
CC
9@
EM
C@
33
P_
04
02
_5
0V
8J
CC
9@
EM
C@
33
P_
04
02
_5
0V
8J
12
CC11
15P_0402_50V8J
CC11
15P_0402_50V8J
12
RC242 10K_0402_5%RC242 10K_0402_5%1 2
RPC14
2.2K_0804_8P4R_5%
RPC14
2.2K_0804_8P4R_5%
1234 5
678
RC231 0_0402_5%RC231 0_0402_5%12
CC1233P_0402_50V8J @EMC@
CC1233P_0402_50V8J @EMC@
12
CC8
15P_0402_50V8J
CC8
15P_0402_50V8J
12
RC240 10K_0402_5%RC240 10K_0402_5%1 2
RN42.2K_0402_5% RN42.2K_0402_5%12
RC68 10K_0402_5%RC68 10K_0402_5%1 2
RN32.2K_0402_5% RN32.2K_0402_5%12
RC66 10K_0402_5%RC66 10K_0402_5%1 2
CLOCK
SIGNALS
BDW_ULT_DDR3L
6 OF 19
UC1F
BDW-ULT-DDR3L_BGA1168
CLOCK
SIGNALS
BDW_ULT_DDR3L
6 OF 19
UC1F
BDW-ULT-DDR3L_BGA1168
CLKOUT_PCIE_N1B41
CLKOUT_PCIE_P1A41
PCIECLKRQ1/GPIO19Y5
PCIECLKRQ0/GPIO18U2 CLKOUT_PCIE_P0
C42
CLKOUT_ITPXDPB35
CLKOUT_LPC_0AN15
CLKOUT_LPC_1AP15
PCIECLKRQ4/GPIO22U5 CLKOUT_PCIE_P4
B39 CLKOUT_PCIE_N4A39
PCIECLKRQ3/GPIO21N1
CLKOUT_PCIE_N0C43
XTAL24_OUTB25XTAL24_INA25
PCIECLKRQ5/GPIO23T2 CLKOUT_PCIE_P5
A37 CLKOUT_PCIE_N5B37
CLKOUT_PCIE_P3C37 CLKOUT_PCIE_N3B38
PCIECLKRQ2/GPIO20AD1
CLKOUT_PCIE_N2C41
CLKOUT_PCIE_P2B42
DIFFCLK_BIASREFC26
RSVDK21
RSVDM21
TESTLOW_C35C35
TESTLOW_C34C34
TESTLOW_AK8AK8
TESTLOW_AL8AL8
CLKOUT_ITPXDP_PA35
RC50 0_0402_5%VPRO@RC50 0_0402_5%VPRO@
1 2
RC67EMC@ 22_0402_5%RC67EMC@ 22_0402_5%1 2
RC241 10K_0402_5%RC241 10K_0402_5%1 2
CC7
0.1U_0402_25V6
VPRO@CC7
0.1U_0402_25V6
VPRO@
1 2
JSPI1
E-T_6700K-Y20N-00LCONN@
JSPI1
E-T_6700K-Y20N-00LCONN@
11
2 22
33
4 44
55
6 66
77
8 88
99
10 1010
1111
12 1212
1313
14 1414
1515
16 1616
1717
18 1818
G121
G222
G323
G424
1919
20 2020
RC243 10K_0402_5%RC243 10K_0402_5%1 2
RC32 0_0402_5%@RC32 0_0402_5%@12
QC1BDMN66D0LDW-7_SOT363-6
QC1BDMN66D0LDW-7_SOT363-6
3 4
5
CC6
0.1U_0402_25V6
CC6
0.1U_0402_25V6
1 2
QC1ADMN66D0LDW-7_SOT363-6
QC1ADMN66D0LDW-7_SOT363-6
1
2
6
RC33499_0402_1% RC33499_0402_1%12
RC225 0_0402_5%RC225 0_0402_5%12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
DDR_A_BS0DDR_A_BS1DDR_A_BS2
DDR_A_CAS#
DDR_A_D0DDR_A_D1
DDR_A_D10DDR_A_D11DDR_A_D12DDR_A_D13DDR_A_D14DDR_A_D15DDR_A_D16DDR_A_D17DDR_A_D18DDR_A_D19
DDR_A_D2
DDR_A_D20DDR_A_D21DDR_A_D22DDR_A_D23DDR_A_D24DDR_A_D25DDR_A_D26DDR_A_D27DDR_A_D28DDR_A_D29
DDR_A_D3
DDR_A_D30DDR_A_D31DDR_A_D32DDR_A_D33DDR_A_D34DDR_A_D35DDR_A_D36DDR_A_D37DDR_A_D38DDR_A_D39
DDR_A_D4
DDR_A_D40DDR_A_D41DDR_A_D42DDR_A_D43DDR_A_D44DDR_A_D45DDR_A_D46DDR_A_D47DDR_A_D48DDR_A_D49
DDR_A_D5
DDR_A_D50DDR_A_D51DDR_A_D52DDR_A_D53DDR_A_D54DDR_A_D55DDR_A_D56DDR_A_D57DDR_A_D58DDR_A_D59
DDR_A_D6
DDR_A_D60DDR_A_D61DDR_A_D62DDR_A_D63
DDR_A_D7DDR_A_D8DDR_A_D9
DDR_A_DQS#0DDR_A_DQS#1DDR_A_DQS#2DDR_A_DQS#3DDR_A_DQS#4DDR_A_DQS#5DDR_A_DQS#6DDR_A_DQS#7
DDR_A_DQS0DDR_A_DQS1DDR_A_DQS2DDR_A_DQS3DDR_A_DQS4DDR_A_DQS5DDR_A_DQS6DDR_A_DQS7
DDR_A_MA0DDR_A_MA1
DDR_A_MA10DDR_A_MA11DDR_A_MA12DDR_A_MA13DDR_A_MA14DDR_A_MA15
DDR_A_MA2DDR_A_MA3DDR_A_MA4DDR_A_MA5DDR_A_MA6DDR_A_MA7DDR_A_MA8DDR_A_MA9
DDR_A_RAS#DDR_A_WE#
DDR_B_BS0DDR_B_BS1DDR_B_BS2
DDR_B_CAS#
DDR_B_D0DDR_B_D1
DDR_B_D10DDR_B_D11DDR_B_D12DDR_B_D13DDR_B_D14DDR_B_D15DDR_B_D16DDR_B_D17DDR_B_D18DDR_B_D19
DDR_B_D2
DDR_B_D20DDR_B_D21DDR_B_D22DDR_B_D23DDR_B_D24DDR_B_D25DDR_B_D26DDR_B_D27DDR_B_D28DDR_B_D29
DDR_B_D3
DDR_B_D30DDR_B_D31DDR_B_D32DDR_B_D33DDR_B_D34DDR_B_D35DDR_B_D36DDR_B_D37DDR_B_D38DDR_B_D39
DDR_B_D4
DDR_B_D40DDR_B_D41DDR_B_D42DDR_B_D43DDR_B_D44DDR_B_D45DDR_B_D46DDR_B_D47DDR_B_D48DDR_B_D49
DDR_B_D5
DDR_B_D50DDR_B_D51DDR_B_D52DDR_B_D53DDR_B_D54DDR_B_D55DDR_B_D56DDR_B_D57DDR_B_D58DDR_B_D59
DDR_B_D6
DDR_B_D60DDR_B_D61DDR_B_D62DDR_B_D63
DDR_B_D7DDR_B_D8DDR_B_D9
DDR_B_DQS#0DDR_B_DQS#1DDR_B_DQS#2DDR_B_DQS#3DDR_B_DQS#4DDR_B_DQS#5DDR_B_DQS#6DDR_B_DQS#7
DDR_B_DQS0DDR_B_DQS1DDR_B_DQS2DDR_B_DQS3DDR_B_DQS4DDR_B_DQS5DDR_B_DQS6DDR_B_DQS7
DDR_B_MA0DDR_B_MA1
DDR_B_MA10DDR_B_MA11DDR_B_MA12DDR_B_MA13DDR_B_MA14DDR_B_MA15
DDR_B_MA2DDR_B_MA3DDR_B_MA4DDR_B_MA5DDR_B_MA6DDR_B_MA7DDR_B_MA8DDR_B_MA9
DDR_B_RAS#DDR_B_WE#
DDR_CKE0_DIMMADDR_CKE1_DIMMA DDR_CKE2_DIMMB
DDR_CKE3_DIMMB
DDR_CS0_DIMMA#DDR_CS1_DIMMA# DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_CLK_DDR#0
M_CLK_DDR#1M_CLK_DDR#2
M_CLK_DDR#3
M_CLK_DDR0
M_CLK_DDR1M_CLK_DDR2
M_CLK_DDR3
+SM_VREF_CA+SM_VREF_DQ0+SM_VREF_DQ1
DDR_A_D[0..63]<18>
DDR_A_DQS#[0..7] <18>
DDR_A_DQS[0..7] <18>
DDR_A_MA[0..15] <18>
M_CLK_DDR0 <18>M_CLK_DDR#0 <18>
M_CLK_DDR1 <18>M_CLK_DDR#1 <18>
DDR_CKE0_DIMMA <18>DDR_CKE1_DIMMA <18>
DDR_CS0_DIMMA# <18>DDR_CS1_DIMMA# <18>
DDR_A_BS0 <18>DDR_A_BS1 <18>DDR_A_BS2 <18>
DDR_A_RAS# <18>DDR_A_WE# <18>
DDR_A_CAS# <18>
DDR_B_D[0..63]<19>
M_CLK_DDR#2 <19>M_CLK_DDR2 <19>M_CLK_DDR#3 <19>M_CLK_DDR3 <19>
DDR_CKE2_DIMMB <19>DDR_CKE3_DIMMB <19>
DDR_CS3_DIMMB# <19>DDR_CS2_DIMMB# <19>
DDR_B_BS2 <19>DDR_B_BS1 <19>DDR_B_BS0 <19>
DDR_B_CAS# <19>DDR_B_WE# <19>
DDR_B_RAS# <19>
DDR_B_MA[0..15] <19>
DDR_B_DQS#[0..7] <19>
DDR_B_DQS[0..7] <19>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (3/12)
8 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (3/12)
8 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (3/12)
8 48Wednesday, March 19, 2014
Compal Electronics, Inc.
BDW_ULT_DDR3L
DDR CHANNEL A
3 OF 19
UC1C
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
DDR CHANNEL A
3 OF 19
UC1C
BDW-ULT-DDR3L_BGA1168
SM_VREF_DQ0AR51
SM_VREF_DQ1AP51
SM_VREF_CAAP49
SA_DQSP7AL49
SA_DQSP5AW53
SA_DQSP6AL42
SA_DQSP2AN58
SA_DQSP3AN55
SA_DQSP4AW57
SA_DQSP0AJ62
SA_DQSP1AN61
SA_DQSN6AL43
SA_DQSN7AL48
SA_DQSN4AV57
SA_DQSN5AV53
SA_DQSN3AM55
SA_DQSN1AN62
SA_DQSN2AM58
SA_DQSN0AJ61
SA_MA15AU42
SA_MA13AR35
SA_MA14AV42
SA_MA10AP35
SA_MA12AU41SA_MA11AW41
SA_MA8AY39
SA_MA9AU40
SA_MA6AV40
SA_MA7AW39
SA_MA5AR36SA_MA4AU39SA_MA3AP36SA_MA2AR38
SA_MA0AU36
SA_MA1AY37
SA_BA2AY41SA_BA1AV35SA_BA0AU35
SA_WEAW34
SA_CASAU34
SA_RASAY34
SA_ODT0AP32
SA_CS#0AP33
SA_CS#1AR32
SA_CKE3AY43
SA_CKE0AU43
SA_CKE1AW43
SA_CKE2AY42
SA_DQ15AP60
SA_DQ63AK51 SA_DQ62AM51 SA_DQ61AK48 SA_DQ60AM48 SA_DQ59AK49 SA_DQ58AM49 SA_DQ57AK46 SA_DQ56AM46 SA_DQ55AM42 SA_DQ54AM40 SA_DQ53AK43 SA_DQ52AK45 SA_DQ51AM45 SA_DQ50AM43 SA_DQ49AK42 SA_DQ48AK40 SA_DQ47AU52 SA_DQ46AV52 SA_DQ45AU54 SA_DQ44AV54 SA_DQ43
AW52 SA_DQ42AY52 SA_DQ41
AW54 SA_DQ40AY54 SA_DQ39AU56 SA_DQ38AV56 SA_DQ37AU58 SA_DQ36AV58 SA_DQ35
AW56 SA_DQ34AY56 SA_DQ33
AW58 SA_DQ32AY58 SA_DQ31AN54 SA_DQ30AR54 SA_DQ29AK55
SA_DQ26AM54
SA_DQ27AK54
SA_DQ24AP55 SA_DQ23AN57 SA_DQ22AR57 SA_DQ21AK58 SA_DQ20AL58 SA_DQ19AK57 SA_DQ18AM57 SA_DQ17AR58 SA_DQ16AP58
SA_DQ14AP61 SA_DQ13AM60 SA_DQ12AM61 SA_DQ11AP62 SA_DQ10AP63 SA_DQ9AM62 SA_DQ8AM63 SA_DQ7AK60 SA_DQ6AK61 SA_DQ5AH60
SA_DQ3AK62 SA_DQ2AK63 SA_DQ1AH62 SA_DQ0AH63
SA_CLK#0AU37
SA_CLK0AV37
SA_CLK#1AW36
SA_CLK1AY36
SA_DQ28AL55
SA_DQ25AR55
SA_DQ4AH61
BDW_ULT_DDR3L
DDR CHANNEL B
4 OF 19
UC1D
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
DDR CHANNEL B
4 OF 19
UC1D
BDW-ULT-DDR3L_BGA1168
SB_DQ14AV25
SB_DQSN5AV18
SB_DQSN7AN18
SB_DQSP4AV22
SB_DQSP5AW18
SB_DQSP6AM21
SB_DQSP3AM25
SB_DQSP7AM18
SB_DQSP2AM28
SB_DQSP0AV30
SB_DQSP1AW26
SB_DQSN6AN21
SB_DQSN2AN28
SB_DQSN3AN25
SB_DQSN4AW22
SB_DQSN1AV26SB_DQSN0AW30
SB_MA14AR46
SB_MA15AP46
SB_MA13AK33
SB_MA9AU46
SB_MA10AK36
SB_MA11AV47
SB_MA8AY47
SB_MA12AU47
SB_MA4AR45
SB_MA5AP45
SB_MA6AW46
SB_MA3AR42
SB_MA7AY46
SB_MA2AP42
SB_MA0AP40
SB_MA1AR40
SB_BA2AU49
SB_WEAK35
SB_CASAM33
SB_BA0AL35
SB_BA1AM36
SB_RASAM35
SB_CS#1AK32
SB_ODT0AL32
SB_CS#0AM32
SB_CKE1AU50
SB_CKE2AW49
SB_CKE3AV50
SB_CKE0AY49
SB_CK#1AK38
SB_CK1AL38
SB_CK0AN38SB_CK#0AM38
SB_DQ61AM20
SB_DQ63AP18 SB_DQ62AR18
SB_DQ57AR20 SB_DQ56AN20
SB_DQ58AK18
SB_DQ59AL18
SB_DQ60AK20
SB_DQ51AM22
SB_DQ52AN22
SB_DQ53AP21
SB_DQ54AK21
SB_DQ55AK22
SB_DQ46AV17
SB_DQ47AU17
SB_DQ48AR21
SB_DQ49AR22
SB_DQ50AL21
SB_DQ45AU19
SB_DQ41AW19
SB_DQ42AY17
SB_DQ43AW17
SB_DQ44AV19
SB_DQ40AY19
SB_DQ36AV23
SB_DQ37AU23
SB_DQ38AV21
SB_DQ39AU21
SB_DQ35AW21
SB_DQ31AL25
SB_DQ32AY23
SB_DQ33AW23
SB_DQ30AK25
SB_DQ34AY21
SB_DQ26AR25 SB_DQ25AR26
SB_DQ27AP25
SB_DQ28AK26
SB_DQ29AM26
SB_DQ20AR29
SB_DQ21AN29
SB_DQ22AR28
SB_DQ23AP28
SB_DQ24AN26
SB_DQ15AU25
SB_DQ16AM29
SB_DQ17AK29
SB_DQ18AL28
SB_DQ19AK28
SB_DQ10AY25
SB_DQ11AW25
SB_DQ13AU27
SB_DQ5AU31
SB_DQ7AU29
SB_DQ8AY27
SB_DQ9AW27
SB_DQ0AY31
SB_DQ1AW31
SB_DQ2AY29
SB_DQ3AW29
SB_DQ4AV31
SB_DQ12AV27
SB_DQ6AV29
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HIGH = ENABLED (DEFAULT)
LOW = DISABLED
DSWODVREN - ON DIE DSW VR ENABLE
RC5 need to close to JCPU1
Place near JXDP1
Place near JXDP1.47
Place near JXDP1.48
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
CAD Note:
Avoid stub in the PWRGD path
while placing resistors RC123
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
DDR3 COMPENSATION SIGNALS
reference Shark Bay ULT Validation Customer Debug Port
Implementation Requirement Rev 1.0
EMI request add
20130726 same as Goliad
Fix Intel 7260 can not detect issue.
It will cause “floating” situation before 3V_RUN coming of AND gate
AC_PRESENT
SIO_PWRBTN#
CFG0CFG1
CFG10CFG11
CFG12CFG13
CFG14CFG15
CFG16CFG17
CFG18CFG19
CFG2CFG3
CFG3CFG3_R
CFG4CFG5
CFG6CFG7
CFG8CFG9
CLKRUN#
CPU_XDP_PRDY#
CPU_XDP_PRDY#
CPU_XDP_PREQ#
CPU_XDP_PREQ#
CPU_XDP_PREQ#
CPU_XDP_TCLK
CPU_XDP_TCLK
CPU_XDP_TCLKCPU_XDP_TCLK
CPU_XDP_TCLK
CPU_XDP_TDI
CPU_XDP_TDI
CPU_XDP_TDI
CPU_XDP_TDO
CPU_XDP_TDO
CPU_XDP_TDO
CPU_XDP_TMS
CPU_XDP_TMS
CPU_XDP_TMS
CPU_XDP_TRST#
CPU_XDP_TRST#
CPU_XDP_TRST#
CPU_XDP_TRST#
DSWODVREN
DSWODVREN
H_CATERR#
H_CATERR#
H_CPUPWRGD
H_CPUPWRGD
H_PROCHOT#
H_PROCHOT#_R
H_VCCST_PWRGD_XDP
ME_RESET#
ME_RESET#
ME_SUS_PWR_ACK
ME_SUS_PWR_ACK
PCH_BATLOW#
PCH_DPWROK
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_PCIE_WAKE#
PCH_PLTRST#
PCH_PLTRST#
PCH_PLTRST#_EC
PCH_RSMRST#_Q PCH_RTCRST#
PECI_EC
PM_APWROK_R
PM_APWROK_R
RUNPWROK
RUNPWROK
RUNPWROK
RUNPWROK
SIO_PWRBTN#
SIO_SLP_A#
SIO_SLP_A#
SIO_SLP_A#
SIO_SLP_LAN#SIO_SLP_S0#
SIO_SLP_S0#
SIO_SLP_S3#
SIO_SLP_S3#
SIO_SLP_S4#
SIO_SLP_S4#
SIO_SLP_S5#
SIO_SLP_S5#
SIO_SLP_SUS#SIO_SLP_WLAN#
SM_RCOMP0
SM_RCOMP0
SM_RCOMP1
SM_RCOMP1
SM_RCOMP2
SM_RCOMP2
SUSACK#
SUSACK#
SUS_STAT#/LPCPD#
SUS_STAT#/LPCPD#
SYS_PWROK
SYS_PWROK
SYS_PWROK
SYS_RESET#
SYS_RESET#
SYS_RESET#
PCH_JTAG_TDI
TDI_XDP_R
TDI_XDP_R
TDO_XDP
TDO_XDP
TDO_XDP
TDO_XDP
PCH_JTAG_TMS
PCH_JTAG_TMS
TRST#_XDP
TRST#_XDP
XDP_DBRESET#
XDP_DBRESET#
XDP_DBRESET#
XDP_DBRESET#
XDP_OBS0_R
XDP_OBS0_R
XDP_OBS1_R
XDP_OBS1_RXDP_OBS2_RXDP_OBS3_RXDP_OBS4_RXDP_OBS5_RXDP_OBS6_RXDP_OBS7_R
XDP_RST#_R
H_PROCHOT#
PCH_PLTRST#
SUSCLK_R
H_CPUPWRGD
PCH_PCIE_WAKE#
PM_APWROK PM_APWROK_L
PCH_PLTRST#_EC
PCH_RSMRST#_Q
PM_LANPHY_ENABLE
+3.3V_RUN+3.3V_RUN
+3.3V_ALW_PCH+RTC_CELL
+3.3V_RUN
+1.05V_VCCST
+1.05V_RUN
+3.3V_RUN
+1.05V_RUN+1.05V_RUN
+1.05V_RUN
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
+1.05V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
+3.3V_ALW2
+PCH_VCCDSW3_3
PCH_PLTRST#_EC <20,27,30,35,36>
SIO_PWRBTN#<36>AC_PRESENT<36,9>
SIO_SLP_WLAN#<35>
PCH_DPWROK <36>PCH_PCIE_WAKE# <35,36>
CLKRUN# <10,35,36>
SIO_SLP_S5# <36>
SIO_SLP_S4# <36>SIO_SLP_S3# <36>SIO_SLP_A# <36>SIO_SLP_SUS# <36>SIO_SLP_LAN# <28,36>
PECI_EC<36>
H_PROCHOT#<36,45,46>
DDR_PG_CTRL<18>
CFG18 <13>
CFG17 <13>CFG16 <13>
CFG3<13>
CFG1<13>CFG0<13>
CFG4<13>
CFG2<13>
CFG7<13>CFG6<13>
CFG5<13>
CFG9 <13>
CFG10 <13>CFG11 <13>
CFG8 <13>
CFG13 <13>
CFG14 <13>CFG15 <13>
CFG12 <13>
CFG19 <13>
H_VCCST_PWRGD<15>
DDR3_DRAMRST#_CPU<18>
PCH_RTCRST#<6>
PCH_JTAG_JTAGX<6>
PCH_JTAG_TRST#<6>
RUNPWROK<35,36>
PCH_JTAG_TDI<6>
PCH_JTAG_TDO<6>
POWER_SW#_MB<36,39>
PLTRST_LAN#<28>
PLTRST_USH#<27>PLTRST_MMI#<29>
SUSCLK <30>
PCH_RSMRST#_Q<37>ME_SUS_PWR_ACK<36>
RESET_OUT#<15,36>
SUSACK#<36>
SYS_PWROK<36>
CPU_PWR_DEBUG#<15>
DDR_XDP_WAN_SMBDAT<18,19,7>DDR_XDP_WAN_SMBCLK<18,19,7>
PCH_JTAG_TCK<6>
PCH_JTAG_TMS<6>
PLTRST_VMM2320#<22>
PCH_BATLOW#<9>
AC_PRESENT <36,9>
PCH_BATLOW# <9>
PM_APWROK<36>
1.05V_M_PWRGD<43>
PM_LANPHY_ENABLE <12,28>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (4/12)
9 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (4/12)
9 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (4/12)
9 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RC130200_0402_1% RC130200_0402_1% 12
UC5TC7SH08FU_SSOP5~D
UC5TC7SH08FU_SSOP5~D
B1
A2
G3
O4
P5
CC
18
@0.1
U_0402_25V
6C
C18
@0.1
U_0402_25V
6
12
T13 @PAD~D T13 @PAD~D
RC95@ 8.2K_0402_5%RC95@ 8.2K_0402_5%1 2
RC92 10K_0402_5%@RC92 10K_0402_5%@1 2
T8 @PAD~DT8 @PAD~D
JAPS1
CONN@ACES_50506-01841-P01
JAPS1
CONN@ACES_50506-01841-P01
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
GND19
GND20
RC79 10K_0402_5%RC79 10K_0402_5%1 2
RC119 @0_0402_5% RC119 @0_0402_5%12
RC1120_0402_5% CXDP@RC1120_0402_5% CXDP@12
RC87@ 0_0402_5%RC87@ 0_0402_5%1 2
RC1221K_0402_5%
RC1221K_0402_5%
12
RC129@
51_0402_5%RC129@
51_0402_5%12
T14 @PAD~D T14 @PAD~D
RC27 0_0402_5%@RC27 0_0402_5%@1 2
DDR3L
BDW_ULT_DDR3L
MISC
THERMAL
PWR
JTAG
2 OF 19
UC1B
BDW-ULT-DDR3L_BGA1168
DDR3L
BDW_ULT_DDR3L
MISC
THERMAL
PWR
JTAG
2 OF 19
UC1B
BDW-ULT-DDR3L_BGA1168
BPM#4K59
BPM#5H63
BPM#6K60
SM_RCOMP0AU60
BPM#7J61
BPM#3H62
BPM#1H60
BPM#2H61
BPM#0J60
PROC_TDOF62PROC_TDIF63
PROC_TMSE61
PECIN62 CATERRK61
PROCPWRGDC61
PROCHOTK63
PROC_TRSTE59
PROC_TCKE60
PRDYJ62
PREQK62
SM_PG_CNTL1AV61 SM_DRAMRSTAV15 SM_RCOMP2AU61 SM_RCOMP1AV60
PROC_DETECTD61
JXDP1
CONN@SAMTE_BSH-030-01-L-D-A
JXDP1
CONN@SAMTE_BSH-030-01-L-D-A
GND01
GND12
OBSFN_A03
OBSFN_C04
OBSFN_A15
OBSFN_C16
GND27
GND38
OBSDATA_A09
OBSDATA_C010
OBSDATA_A111
OBSDATA_C112
GND413
GND514
OBSDATA_A215
OBSDATA_C216
OBSDATA_A317
OBSDATA_C318
GND619
GND720
OBSFN_B021
OBSFN_D022
OBSFN_B123
OBSFN_D124
GND825
GND926
OBSDATA_B027
OBSDATA_D028
OBSDATA_B129
OBSDATA_D130
GND1031
GND1132
OBSDATA_B233
OBSDATA_D234
OBSDATA_B335
OBSDATA_D336
GND1237
GND1338
PWRGOOD/HOOK039
ITPCLK/HOOK440
HOOK141
ITPCLK#/HOOK542
VCC_OBS_AB43
VCC_OBS_CD44
HOOK245
RESET#/HOOK646
HOOK347
DBR#/HOOK748
GND1449
GND1550
SDA51
TD052
SCL53
TRST#54
TCK155
TDI56
TCK057
TMS58
GND1659
GND1760
CC
22
@0.1
U_0402_25V
6C
C22
@0.1
U_0402_25V
6
12
RC
78
33
0K
_0
40
2_
5%
RC
78
33
0K
_0
40
2_
5%
12
RC118 @0_0402_5% RC118 @0_0402_5%12
T15 @PAD~D T15 @PAD~D
RC91 47K_0402_5%RC91 47K_0402_5%1 2
CC
83
100P
_0402_50V
8J
@E
MC
@C
C8
3100P
_0402_50V
8J
@E
MC
@
1
2
CC2022P_0402_50V8J
@EMC@CC2022P_0402_50V8J
@EMC@1
2
T11 @PAD~D T11 @PAD~D RC126@
51_0402_5%RC126@
51_0402_5%12
RC113 1K_0402_5%CXDP@RC113 1K_0402_5%CXDP@
1 2
RC136 0_0402_5%@ RC136 0_0402_5%@1 2
RC132100_0402_1% RC132100_0402_1% 12
RC98 0_0402_5%CXDP@RC98 0_0402_5%CXDP@
1 2
UC7
74CBTLV3126BQ_DHVQFN14_2P5X3
CXDP@UC7
74CBTLV3126BQ_DHVQFN14_2P5X3
CXDP@
1OE1
1A2
1B3
2OE4
2A5
2B6
GND7
3B8
3A9
3OE10
4B11
4A12
4OE13
VCC14
GND PAD15
RC12751_0402_5%
RC12751_0402_5%
12
UC6TC7SH08FU_SSOP5~D
UC6TC7SH08FU_SSOP5~D
B1
A2
G3
O4
P5
RC114@ 49.9_0402_1%RC114@ 49.9_0402_1%1 2
RC99 0_0402_5%CXDP@RC99 0_0402_5%CXDP@
1 2
RC77@ 0_0402_5%RC77@ 0_0402_5%1 2
RC103@ 1K_0402_5%RC103@ 1K_0402_5%1 2
RC26 0_0402_5%@RC26 0_0402_5%@1 2
T12 @PAD~D T12 @PAD~D
RC89@ 0_0402_5%RC89@ 0_0402_5%1 2
RC116 62_0402_5%RC116 62_0402_5%1 2
CC
21
0.1
U_0402_25V
6 CX
DP
@C
C21
0.1
U_0402_25V
6 CX
DP
@
12
RC106 1K_0402_5%CXDP@RC106 1K_0402_5%CXDP@
12
RC115 @0_0402_5% RC115 @0_0402_5%12
CC17
0.1U_0402_25V6
CXDP@CC17
0.1U_0402_25V6
CXDP@12
RC124@
51_0402_5%RC124@
51_0402_5%12
RC82@ 10K_0402_5%RC82@ 10K_0402_5%1 2
RC304
100K_0402_5%
@RC304
100K_0402_5%
@
12
RC102 1K_0402_5%CXDP@RC102 1K_0402_5%CXDP@
1 2
RC88@ 0_0402_5%RC88@ 0_0402_5%1 2
RC121 56_0402_5%RC121 56_0402_5%1 2
T9 @PAD~DT9 @PAD~D
RC117@51_0402_5% RC117@51_0402_5%12
RC12851_0402_5%
RC12851_0402_5%
12
RC81 10K_0402_5%RC81 10K_0402_5%1 2
RC125@
51_0402_5%RC125@
51_0402_5%12
RC
120
CX
DP
@
1K
_0402_5%
RC
120
CX
DP
@
1K
_0402_5%
12
BDW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
8 OF 19
UC1H
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
8 OF 19
UC1H
BDW-ULT-DDR3L_BGA1168
SLP_A AL5
SLP_SUS AP4
SLP_LAN AJ7
SLP_S3 AT4
SLP_S5/GPIO63 AP5
SLP_S4 AJ6
SUSCLK/GPIO62AE6
CLKRUN/GPIO32 V5
SUS_STAT/GPIO61 AG4
WAKEAJ5
DSWVRMENAW7
DPWROKAV5
SLP_WLAN/GPIO29AM5 SLP_S0AF3
SUSWARN/SUSPWRDNACK/GPIO30AV4
PWRBTNAL7
BATLOW/GPIO72AN4 ACPRESENT/GPIO31AJ8
RSMRSTAW6
PCH_PWROKAY7
SUSACKAK2
PLTRSTAG7 APWROKAB5
SYS_PWROKAG2 SYS_RESETAC3
RC219@ 0_0402_5%RC219@ 0_0402_5%1 2
RPC1
10K_8P4R_5%
RPC1
10K_8P4R_5%
1234 5
678
RC131121_0402_1% RC131121_0402_1% 12
RC80@ 8.2K_0402_5%RC80@ 8.2K_0402_5%12
RC
123
10K
_0402_5%
RC
123
10K
_0402_5%
12
CC
19
@0.1
U_0402_25V
6C
C19
@0.1
U_0402_25V
6
12
RC1090_0402_5% CXDP@RC1090_0402_5% CXDP@12
T10 @PAD~D T10 @PAD~D
UC4@74AHC1G09GW_TSSOP5
UC4@74AHC1G09GW_TSSOP5
B1
A2
G3
O4
P5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
PCH_GPIO53
PCH_GPIO53
DPB_HPDDPC_HPD
EDP_BIA_PWM
EDP_COMP
EDP_COMP
EDP_CPU_AUXEDP_CPU_AUX#
EDP_CPU_HPD
EDP_CPU_LANE_N0
EDP_CPU_LANE_N1EDP_CPU_LANE_P0
EDP_CPU_LANE_P1
ENVDD_PCH
ENVDD_PCHPANEL_BKLEN
HDD_FALL_INTDGPU_PWROK
CPU_DPC_CTRLCLKCPU_DPC_CTRLDAT
EDP_CPU_HPD
DPB_HPD
CPU_DPB_AUXCPU_DPC_AUXCPU_DPC_AUX#
CPU_DPB_AUX#
CPU_DPB_CTRLDATCPU_DPB_CTRLCLK
CPU_DPB_AUX
CPU_DPB_AUX#
CPU_DPB_CTRLCLKCPU_DPB_CTRLDAT
CPU_DPC_AUX
CPU_DPC_AUX#
CPU_DPC_CTRLCLKCPU_DPC_CTRLDAT
+VCCIOA_OUT
+3.3V_RUN
+3.3V_RUN
DDI1_LANE_N3<25>
DDI1_LANE_N2<25>
DDI1_LANE_N1<25>
DDI1_LANE_N0<25>
DDI1_LANE_P1<25>
DDI1_LANE_P0<25>
DDI1_LANE_P3<25>
DDI1_LANE_P2<25>
DPB_HPD <25>DPC_HPD <24>
PANEL_BKLEN<23>ENVDD_PCH<23,36>
CONTACTLESS_DET#<27,7>
EDP_CPU_LANE_P0 <23>EDP_CPU_LANE_N0 <23>
EDP_CPU_LANE_P1 <23>EDP_CPU_LANE_N1 <23>
EDP_CPU_AUX <23>EDP_CPU_AUX# <23>
EDP_CPU_HPD <23>
EDP_BIA_PWM<23>
PCH_GPIO52<12>
DDI2_LANE_N3<24>
DDI2_LANE_N0<24>
DDI2_LANE_N1<24>
DDI2_LANE_N2<24>
DDI2_LANE_P3<24>
DDI2_LANE_P0<24>
DDI2_LANE_P1<24>
DDI2_LANE_P2<24>
TOUCHPAD_INTR#<12>
DGPU_PWROK<6>
PCH_GPIO80<12>
CPU_DPC_CTRLDAT <24>CPU_DPC_CTRLCLK <24>
CPU_DPB_AUX <25>
CPU_DPB_AUX# <25>CPU_DPC_AUX# <24>
CPU_DPC_AUX <24>
CPU_DPB_CTRLDAT <25>CPU_DPB_CTRLCLK <25>
HDD_FALL_INT<12>
USH_DET# <12,27>
SIO_RCIN# <12,36>
IRQ_SERIRQ <12,35,36>
CLKRUN# <35,36,9>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (5/12)
10 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (5/12)
10 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (5/12)
10 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RPC2
2.2K_0804_8P4R_5%
RPC2
2.2K_0804_8P4R_5%
1234 5
678
RC141100K_0402_5% RC141100K_0402_5% 12
BDW_ULT_DDR3L
EDPDDI
1 OF 19
UC1A
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
EDPDDI
1 OF 19
UC1A
BDW-ULT-DDR3L_BGA1168
DDI1_TXN0C54
DDI1_TXP0C55
DDI1_TXN1B58
DDI1_TXP1C58
DDI1_TXN2B55
DDI1_TXP2A55
DDI1_TXN3A57
EDP_TXP0B46EDP_TXN0C45
EDP_TXN1A47
EDP_TXP1B47
EDP_TXN2C47
EDP_TXP2C46
EDP_TXN3A49
EDP_TXP3B49
EDP_AUXPB45EDP_AUXNA45
DDI1_TXP3B57
DDI2_TXP1B54
DDI2_TXP0C50 DDI2_TXN0C51
DDI2_TXN1C53
DDI2_TXN2C49
DDI2_TXP2B50
DDI2_TXN3A53
DDI2_TXP3B53
EDP_RCOMPD20
EDP_DISP_UTILA43
RPC20
100K_0804_8P4R_5%
RPC20
100K_0804_8P4R_5%
1234 5
678
RC142100K_0402_5% RC142100K_0402_5% 12
RC13324.9_0402_1% RC13324.9_0402_1%12
T16@ PAD~DT16@ PAD~DRC140@ 1K_0402_5%RC140@ 1K_0402_5%
12
BDW_ULT_DDR3L
eDP SIDEBAND
PCIE
DISPLAY
9 OF 19
UC1I
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
eDP SIDEBAND
PCIE
DISPLAY
9 OF 19
UC1I
BDW-ULT-DDR3L_BGA1168
DDPC_AUXNB6
DDPC_AUXPA6DDPB_AUXPB5
EDP_BKLENA9
GPIO53L4 GPIO51R5 GPIO54L3 GPIO52L1 GPIO55U7
PMEAD4 PIRQD/GPIO80
N2 PIRQC/GPIO79N4
DDPB_CTRLCLKB9
DDPB_CTRLDATAC9
DDPC_CTRLCLKD9
DDPC_CTRLDATAD11
DDPB_HPDC8
EDP_HPDD6DDPC_HPDA8
DDPB_AUXNC5
EDP_VDDENC6
EDP_BKLCTLB8
PIRQA/GPIO77U6
PIRQB/GPIO78P4
RC139@ 100K_0402_5%RC139@ 100K_0402_5%1 2
RPC15
10K_8P4R_5%
RPC15
10K_8P4R_5%
12345
678
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAD NOTE:
Route single-end 50-ohms and max 500-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15
mils.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
10/100/1G LAN --->
WLAN (Mini Card 2)--->
-----> Ext Port 1 Charge
-----> Ext Port 3
-----> WLAN/BT
-----> Ext USB3 Port 3
-----> Ext USB3 Port 1 Charge
MMI -->
-----> USH
-----> Camera
-----> Ext Port 2
-----> Touch
-----> WWAN
PCIE for UMA
WIGIG --->
-----> USB Port0 (JUSB1)-----> USB Port1 (JUSB3)-----> USB Port3 (JUSB2)
PCB
G14U_En
G14D_En
G14 UMA
G14 DSC
G12 UMA WWAN
USB2 7
G12 Entry
WWAN
WWAN
NA
NA
NA
PCB
G14U_En
G14D_En
G14 UMA
G14 DSC
G12 UMA
PCIE3PCIE2
SD card
PCIE1 PCIE4
G12 Entry NA
NA
WIGIG
WIGIGSD card
SD card
SD card
SD card
SD card
NA
NA
NA
NA
NA
NA LOM
LOM
LOM
LOM
LOM
LOM
WLAN
WLAN
WLAN
WLAN
WLAN
WLAN
PCIE5
GPU
WIGIG
GPU
WIGIG
PCIE6
WIGIG
WIGIG
M2 3042(HCA & SATA-Cache)
M2 3042(HCA & SATA-Cache)
PCH_PCIE_RCOMP
PCIE_PRX_GLANTX_N3PCIE_PRX_GLANTX_P3
PCIE_PRX_WLANTX_N4PCIE_PRX_WLANTX_P4
PCIE_PTX_GLANRX_N3PCIE_PTX_GLANRX_P3
PCIE_PTX_WLANRX_N4PCIE_PTX_WLANRX_P4
USBP0+USBP0-
USBP1+USBP1-
USBP2+USBP2-
USBRBIAS
USBRBIAS
USB_OC0#
USB_OC3#
USB_OC1#
PCIE_PRX_MMITX_N1PCIE_PRX_MMITX_P1
PCIE_PTX_MMIRX_N1PCIE_PTX_MMIRX_P1
USBP6+USBP6-
USBP5+USBP5-
USBP3+USBP3-
USBP4+USBP4-
USBP7-USBP7+
PCIE_PRX_WIGIGTX_N5PCIE_PRX_WIGIGTX_P5
PCIE_PTX_WIGIGRX_N5PCIE_PTX_WIGIGRX_P5
USB_OC0#+PCH_AUSB3PLL
+3.3V_ALW_PCH
USBP0- <31>USBP0+ <31>
USB3RN1 <31>
USB3RN2 <32>USB3RP2 <32>
USB3TN2 <32>USB3TP2 <32>
USB3RP1 <31>
USB3TN1 <31>USB3TP1 <31>
PCIE_PTX_GLANRX_N3<28>PCIE_PTX_GLANRX_P3<28>
PCIE_PRX_GLANTX_P3<28>PCIE_PRX_GLANTX_N3<28>
PCIE_PRX_WLANTX_P4<30>PCIE_PRX_WLANTX_N4<30>
PCIE_PTX_WLANRX_N4<30>PCIE_PTX_WLANRX_P4<30>
USBP2+ <30>USBP2- <30>
USBP1+ <32>USBP1- <32>
USB_OC0# <31>
USB_OC2# <12,31>USB_OC1# <12,32>
PCIE_PRX_MMITX_N1<29>
PCIE_PTX_MMIRX_N1<29>
PCIE_PRX_MMITX_P1<29>
PCIE_PTX_MMIRX_P1<29>
USBP6+ <27>USBP6- <27>
USBP5- <23>USBP5+ <23>
USBP3+ <31>USBP3- <31>
USB3RN4<31>USB3RP4<31>
USB3TN4<31>USB3TP4<31>
USBP4+ <23>USBP4- <23>
USBP7+ <30>USBP7- <30>
PCIE_PTX_WIGIGRX_N5<30>PCIE_PTX_WIGIGRX_P5<30>
PCIE_PRX_WIGIGTX_P5<30>PCIE_PRX_WIGIGTX_N5<30>
USB_OC3# <12>
PCH_GPIO44<12>
PCH_SMB_ALERT#<7>KB_DET#<12,37>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (6/12)
11 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (6/12)
11 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (6/12)
11 48Wednesday, March 19, 2014
Compal Electronics, Inc.
BDW_ULT_DDR3L
PCIE USB
11 OF 19
UC1K
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
PCIE USB
11 OF 19
UC1K
BDW-ULT-DDR3L_BGA1168
RSVDAM10RSVDAN10
USB2P1AT7
USB2P0AM8
PERN3G11
PETN5_L0C23
USBRBIAS AJ10
USBRBIASAJ11
PETN5_L1B23
PETP5_L1A23
USB2N7AR13
USB2P7AP13
USB2N6AP11
USB2P5AN13USB2N5AM13
USB2P6AN11
USB2P4AL15USB2N4AM15
USB2P3AT10USB2N3AR10
USB2P2AP8USB2N2AR8
USB2N1AR7
USB2N0AN8
PETP4A29
PERP4G13
PERN5_L3E6
PERP5_L3F6
PETN5_L2B21
PERP5_L2G10 PERN5_L2H10
OC0/GPIO40 AL3
OC1/GPIO41 AT1
OC2/GPIO42 AH2
OC3/GPIO43 AV3
PETN3C29
PERP3F11
PERN5_L1F8
PETN5_L3B22
PETP5_L3A21
PERP5_L1E8
PETN4B29
PETP5_L0C22
PERP5_L0E10 PERN5_L0F10
PERN4F13
PETP3B30
PCIE_IREFB27 PCIE_RCOMPA27 RSVDE13
PETP5_L2C21
PERP1/USB3RP3F17 PERN1/USB3RN3G17
RSVDE15
PETP1/USB3TP3C31 PETN1/USB3TN3C30
PERN2/USB3RN4F15
PETP2/USB3TP4A31 PETN2/USB3TN4B31
PERP2/USB3RP4G15
USB3RN1G20
USB3RP1H20
USB3TN1C33
USB3TP1B34
USB3RN2E18
USB3RP2F18
USB3TN2B33
USB3TP2A33
RC
15
22
2.6
_0
40
2_
1%
RC
15
22
2.6
_0
40
2_
1%
12
RC149 3.01K_0402_1%RC149 3.01K_0402_1%1 2RPC19
10K_8P4R_5%
RPC19
10K_8P4R_5%
1234 5
678
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
No Reboot on TCO Timer expiration
HIGH
LOW(DEFAULT)
TLS CONFIDENTIALITYTOP-BLOCK SWAP OVERRIDE
HIGH
LOW(DEFAULT)
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
ENABLE
DISABLE
ENABLE
DISABLE
PCH_NFC_RST for Goliad
HIGH
LOW(DEFAULT)
ENABLE
DISABLE
HIGH
LOW
DIMM Detect
1 DIMM
2 DIMM
3.3V_CAM_EN#
PCH_GPIO85
3.3V_TP_EN
BBS_BIT
CAM_MIC_CBL_DET#
CPPE#CPUSB#
PCH_GPIO87
LAN_WAKE#
FFS_INT2
H_THERMTRIP#_R
PCH_GPIO5PCH_GPIO4
PCH_GPIO7PCH_GPIO6
IRQ_SERIRQ
KB_DET#
LCD_CBL_DET#
PCH_GPIO57MEDIACARD_RST#
MPHYP_PWR_EN
MPHYP_PWR_EN
NFC_IRQ
PCH_GPIO10
HOST_ALERT1_R_N
HOST_ALERT1_R_N
PCH_GPIO44
PCH_GPIO66
PCH_GPIO66
PCH_GPIO9
PCH_OPI_COMP
SIO_EXT_SCI#
SIO_EXT_SCI#
SIO_EXT_SMI#
SIO_EXT_WAKE# SIO_RCIN#
SLATE_MODE
SPKR
SPKR
TOUCH_PANEL_INTR#
USH_DET#
PCH_OPI_COMP
LAN_WAKE#
PCH_GPIO59
PCH_GPIO76
PCH_GPIO69
3.3V_CAM_EN#
NFC_IRQ
PCH_GPIO59
SIO_EXT_SMI#
MEDIACARD_IRQ#MEDIACARD_RST#
SLATE_MODE
PCH_GPIO9
MPHYP_PWR_EN
PCH_GPIO7PCH_GPIO6
CPPE#
FFS_INT2
H_THERMTRIP#
TOUCH_PANEL_INTR#
LCD_CBL_DET#CPUSB#3.3V_TS_EN
PCH_GPIO49
PCH_GPIO67
PCH_GPIO68
PCH_GPIO67PCH_GPIO68
GC6_EVENT#_Q
TPM_PIRQ#
PCH_GPIO4PCH_GPIO5
PCH_GPIO76
PCH_GPIO85
3.3V_TP_ENGPU_GC6_FB_EN
CAM_MIC_CBL_DET#
PCH_GPIO87GC6_EVENT#_QPCH_GPIO69
GPU_GC6_FB_EN
PCH_GPIO57
DIMM_DET
DIMM_DET
PCH_GPIO14
TPM_PIRQ#
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
+3.3V_ALW_PCH
+1.05V_VCCST
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
SIO_EXT_WAKE#<12,36>PM_LANPHY_ENABLE<28,9>
SIO_RCIN# <10,36>IRQ_SERIRQ <10,35,36>
LCD_CBL_DET# <23>
SPKR<21>
KB_DET#<11,37>
3.3V_CAM_EN#<23>
MEDIACARD_IRQ#<29>
USH_DET# <10,27>CAM_MIC_CBL_DET# <23>
H_THERMTRIP# <36>
SIO_EXT_SCI#<36>
LAN_WAKE#<28,36>
HDD_DEVSLP<20>
SIO_EXT_SMI#<36>
MPHYP_PWR_EN<38>
3.3V_TS_EN <23>
TOUCH_PANEL_INTR#<23>
mSATA_DEVSLP<30>
PCH_GPIO80<10>
HDD_FALL_INT<10>
PCH_GPIO16<7>
PCH_GPIO46<12>
3.3V_HDD_EN <38>
WLANCLK_REQ#<30,7>
PCH_GPIO52<10>
WIGIGCLK_REQ#<30,7>TOUCHPAD_INTR#<10>
SATA2_PCIE6_L1<35,6>
USB_OC2# <11,31>PCH_GPIO46 <12>
PCH_GPIO44<11>
PCH_GPIO73 <7>
USB_OC3# <11>SIO_EXT_WAKE# <12,36>USB_OC1# <11,32>
TPM_PIRQ#<27>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (7/12)
12 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (7/12)
12 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (7/12)
12 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RC161@ 0_0402_5% RC161@ 0_0402_5% 12
RC
18
0@
1K
_0
40
2_
5%
RC
18
0@
1K
_0
40
2_
5%
12
RPC17
10K_8P4R_5%
RPC17
10K_8P4R_5%
12345
678
RC171@ 10K_0402_5%RC171@ 10K_0402_5%12
RC
17
6@
1K
_0
40
2_
5%
RC
17
6@
1K
_0
40
2_
5%
12
RPC4
10K_8P4R_5%
RPC4
10K_8P4R_5%
12345
678
RC174 100K_0402_5%RC174 100K_0402_5%12
RPC16
10K_8P4R_5%
RPC16
10K_8P4R_5%
12345
678
RPC3
10K_8P4R_5%
RPC3
10K_8P4R_5%
12345
678
T22@ PAD~DT22@ PAD~D
RC247 10K_0402_5%RC247 10K_0402_5%1 2
RC175 100K_0402_5%RC175 100K_0402_5%12
RPC5
10K_8P4R_5%
RPC5
10K_8P4R_5%
1234 5
678
BDW_ULT_DDR3L
SERIAL IO
GPIO
MISC
CPU/
10 OF 19
UC1J
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
SERIAL IO
GPIO
MISC
CPU/
10 OF 19
UC1J
BDW-ULT-DDR3L_BGA1168
RSVDAB21RSVDAF20
SERIRQT4
LAN_PHY_PWR_CTRL/GPIO12AM7
GPIO58AL4
GPIO44AK4
BMBUSY/GPIO76P1
GPIO8AU2
GPIO15AD6
GPIO17T3 GPIO16Y1
GPIO59AT5
GPIO48U4 GPIO47
AB6
GPIO49Y3
GPIO50P3
HSIOPC/GPIO71Y2
GPIO13AT3
GPIO25AM4 GPIO14AH4
GPIO46AG3
GPIO10AM2 GPIO9AM3
DEVSLP0/GPIO33P2
SDIO_POWER_EN/GPIO70C4
DEVSLP1/GPIO38L2
SPKR/GPIO81V2 DEVSLP2/GPIO39N5
THRMTRIPD60
RCIN/GPIO82V4
GSPI0_CS/GPIO83 R6
GSPI0_MISO/GPIO85N6GSPI0_CLK/GPIO84L6
GSPI0_MOSI/GPIO86L8
GSPI1_CS/GPIO87 R7
GSPI1_CLK/GPIO88L5
GSPI_MOSI/GPIO90K2GSPI1_MISO/GPIO89N7
UART0_RXD/GPIO91J1
UART0_RTS/GPIO93 J2UART0_TXD/GPIO92K3
UART0_CTS/GPIO94 G1
UART1_TXD/GPIO1G2UART1_RXD/GPIO0K4
I2C0_SCL/GPIO5F3
I2C1_SDA/GPIO6G4
I2C1_SCL/GPIO7F1
SDIO_CMD/GPIO65F4SDIO_CLK/GPIO64E3
SDIO_D0/GPIO66D3
SDIO_D3/GPIO69E2SDIO_D2/GPIO68C3SDIO_D1/GPIO67E4
GPIO28AD7
GPIO57AP1 GPIO56AG6
GPIO45AG5
GPIO24AD5
GPIO27AN5
GPIO26AN3
UART1_RST/GPIO2 J3
I2C0_SDA/GPIO4F2UART1_CTS/GPIO3 J4
PCH_OPI_RCOMPAW15
RC
17
91
K_
04
02
_5
%R
C1
79
1K
_0
40
2_
5%
12
RC16310K_0402_5% RC16310K_0402_5%12
RC245 100K_0402_5%RC245 100K_0402_5%12
RC
302
@10K
_0402_5%
RC
302
@10K
_0402_5%
12
RC251K_0402_5% RC251K_0402_5%12
RPC8
10K_8P4R_5%
RPC8
10K_8P4R_5%
1234 5
678
RC158100K_0402_5% RC158100K_0402_5%12
RC156 100K_0402_5%RC156 100K_0402_5%12
T27@ PAD~DT27@ PAD~D
RC153 10K_0402_5%RC153 10K_0402_5%12
RPC10
10K_8P4R_5%
RPC10
10K_8P4R_5%
1234 5
678
RC16410K_0402_5% RC16410K_0402_5%12
RC
303
10K
_0402_5%
RC
303
10K
_0402_5%
12
RC17849.9_0402_1% RC17849.9_0402_1%1 2
RC155 100K_0402_5%RC155 100K_0402_5%12
RPC9
10K_8P4R_5%
RPC9
10K_8P4R_5%
12345
678
T21@ PAD~DT21@ PAD~D
RC160100K_0402_5% RC160100K_0402_5%12
RPC7
10K_8P4R_5%
RPC7
10K_8P4R_5%
1234 5
678
T109@ PAD~DT109@ PAD~D
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG4
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
Display Port Presence Strap
1: Enable(Default): Noa will be disable in
locked units and enable in un-locked
unitsCFG8
ALLOW THE USE OF NOA ON LOCKED UNITS
0: Enable Noa will be available pegardless of
the locking of the unit
EAR-STALL/NOT STALL RESET SEQUENCE AFTER PCU PLL IS LOCKE
CFG01:(Default) Normal Operation; No stall
0:Lane Reversed
PCH/PCH LESS MODE SELECTION
CFG11:(Default) Normal Operation
0:Lane Reversed
1: VRS support SVID protocol are present
CFG9
NO SVID PROTOCOL CAPABLE VR CONNECTED
0:No VR support SVID is present
The chip will not generate(OR Respond to)
SVID activity
1: POWER FEATURES ACTIVATED DURING
RESETCFG10
SAFE MODE BOOT
0: POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
CFG STRAPS for CPU
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
CFG0
CFG0
CFG1
CFG1
CFG10
CFG10 CFG4
CFG4
CFG8
CFG8CFG9
CFG9
CFG_RCOMP
CFG_RCOMP
PROC_OPI_RCOMP
PROC_OPI_RCOMP
TDI_IREF
TDI_IREF
CFG0<9>
CFG2<9>
CFG4<9>CFG5<9>CFG6<9>CFG7<9>
CFG1<9>
CFG3<9>
CFG8<9>CFG9<9>CFG10<9>CFG11<9>CFG12<9>CFG13<9>CFG14<9>CFG15<9>
CFG16<9>
CFG19<9>
CFG18<9>CFG17<9>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (8/12)
13 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (8/12)
13 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (8/12)
13 48Wednesday, March 19, 2014
Compal Electronics, Inc.
T34 @PAD~D T34 @PAD~D
RC
18
4@
1K
_0
40
2_
1%
RC
18
4@
1K
_0
40
2_
1%
12
RC
19
0@
1K
_0
40
2_
1%
RC
19
0@
1K
_0
40
2_
1%
12
RC
18
3@1
K_
04
02
_1
%R
C1
83
@1K
_0
40
2_
1%
12
RC
18
8@
1K
_0
40
2_
1%
RC
18
8@
1K
_0
40
2_
1%
12
T33 @PAD~D T33 @PAD~D
T30 @PAD~D T30 @PAD~D
RESERVED
BDW_ULT_DDR3L
19 OF 19
UC1S
BDW-ULT-DDR3L_BGA1168
RESERVED
BDW_ULT_DDR3L
19 OF 19
UC1S
BDW-ULT-DDR3L_BGA1168
CFG4AA60
CFG5Y62
CFG17AA61 CFG18U63
CFG7Y60
CFG11U60
RSVD_TPAU63
RSVD_TPC63
RSVD_TPC62
RSVD_TPL60
RSVD_TPB51RSVD_TPA51
CFG10V60 CFG9V61 CFG8V62
RSVDN60
RSVDY22RSVDW23
RSVDD58RSVDAV62
RSVD_TPAV63
VSSN21VSSP22
CFG19U62
RSVDR20RSVDP20
RSVDJ20
CFG3AA63 CFG2AC63 CFG1AC62
CFG16AA62
CFG15T60 CFG14T61
CFG_RCOMPV63
RSVDA5
RSVDE1
RSVDD1
TD_IREFB12 RSVDH18
PROC_OPI_RCOMPAY15
CFG12T63
CFG13T62
CFG0AC60
CFG6Y61
RSVDB43
T28 @PAD~D T28 @PAD~D
RC186 8.2K_0402_1%RC186 8.2K_0402_1%1 2
RC18749.9_0402_1% RC18749.9_0402_1%1 2
T35 @PAD~D T35 @PAD~D
RC
18
9@1
K_
04
02
_1
%R
C1
89
@1K
_0
40
2_
1%
12
RC185 49.9_0402_1%RC185 49.9_0402_1%12
T31 @PAD~D T31 @PAD~D
T29 @PAD~D T29 @PAD~D
RC
191
1K
_0402_5%
RC
191
1K
_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1
2
4
3
1.B2-PKG-C1-PCB-C2-PKG-B3-PCB-A3-PKG-A4
2.A62-PKG-A61-PCB-B61-PKG-B62-PCB-B63-PKG-A60
3.AY60-PKG-AW61-PCB-AY61-PKG-AW62-PCB-AY62-PKG-AW63
4.AW1-PKG-AW3-PCB-AY3-PKG-AW2-PCB-AY2-PKG-AV1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Package Daisy Chain:
DC_TEST_A3_B3
DC_TEST_A3_B3DC_TEST_A4
DC_TEST_A60
DC_TEST_A61_B61
DC_TEST_A61_B61DC_TEST_A62DC_TEST_AV1DC_TEST_AW1
DC_TEST_AW63
DC_TEST_AY2_AW2
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY3_AW3
DC_TEST_AY60DC_TEST_AY61_AW61
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
DC_TEST_AY62_AW62
DC_TEST_B62_B63
DC_TEST_C1_C2
TP_DC_TEST_B2
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (9/12)
14 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (9/12)
14 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (9/12)
14 48Wednesday, March 19, 2014
Compal Electronics, Inc.
BDW_ULT_DDR3L
18 OF 19
UC1R
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
18 OF 19
UC1R
BDW-ULT-DDR3L_BGA1168
RSVDAY14RSVDAW14
RSVDAT2
RSVDAU44
RSVDAV44
RSVDD15
RSVDF22
RSVDH22
RSVDJ21
RSVDT23
RSVDN23
RSVDR23
RSVDAU15RSVDAU10
RSVDAM11RSVDAL1
RSVDU10
RSVDAP7
RC194@0_0402_5% RC194@0_0402_5%12
RC195@0_0402_5% RC195@0_0402_5%12
RC192@0_0402_5% RC192@0_0402_5%12
RC193@0_0402_5% RC193@0_0402_5%12
BDW_ULT_DDR3L
17 OF 19
UC1Q
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
17 OF 19
UC1Q
BDW-ULT-DDR3L_BGA1168
DAISY_CHAIN_NCTF_AY2AY2
DAISY_CHAIN_NCTF_AY60AY60
DAISY_CHAIN_NCTF_AY61AY61
DAISY_CHAIN_NCTF_B2B2
DAISY_CHAIN_NCTF_A3A3
DAISY_CHAIN_NCTF_A4A4
DAISY_CHAIN_NCTF_A61A61DAISY_CHAIN_NCTF_A60A60
DAISY_CHAIN_NCTF_AW1AW1DAISY_CHAIN_NCTF_AV1AV1DAISY_CHAIN_NCTF_A62A62
DAISY_CHAIN_NCTF_AW2AW2
DAISY_CHAIN_NCTF_AW3AW3
DAISY_CHAIN_NCTF_AW61AW61
DAISY_CHAIN_NCTF_AW63AW63DAISY_CHAIN_NCTF_AW62AW62DAISY_CHAIN_NCTF_C1
C1
DAISY_CHAIN_NCTF_B62B62
DAISY_CHAIN_NCTF_B3B3
DAISY_CHAIN_NCTF_AY3AY3
DAISY_CHAIN_NCTF_AY62AY62
DAISY_CHAIN_NCTF_B61B61
DAISY_CHAIN_NCTF_B63B63
DAISY_CHAIN_NCTF_C2C2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAD Note: Place the PU resistors close to CPU
RC208close to CPU 300 - 1500mils
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 -
1500mils
CAD Note: RC209 SHOULD BE PLACED CLOSE TO CPU
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
RESISTOR STUFFING OPTIONS ARE
PROVIDED FOR TESTING PURPOSES
VDDQ DECOUPLING
VCC_SENSE
SVID ALERT
SVID DATA
ESD Request
CPU_PWR_DEBUG#
H_CPU_SVIDALRT#
H_CPU_SVIDALRT#
H_VCCST_PWRGD
H_VCCST_PWRGD
H_VR_EN
H_VR_EN
H_VR_READY
H_VR_READY
VCCSENSE
VCCSENSE
VIDSCLKVIDSOUT
VIDSOUT
H_VCCST_PWRGD
+1.35V_MEM
+VCC_CORE
+1.05V_RUN +VCCIO_OUT
+VCCIO_OUT+VCCIOA_OUT
+1.05V_VCCST
+1.05V_VCCST
+VCC_CORE
+1.05V_RUN
+1.05V_RUN +1.05V_VCCST
+1.05V_VCCST
+VCC_CORE
+1.35V_MEM
+VCC_CORE
+1.05V_VCCST
+1.05V_VCCST
+3.3V_ALW
+1.05V_RUN
+VCC_CORE
+VCC_CORE
+1.35V_MEM
+1.05V_RUN +3.3V_RUN
VCCSENSE<45>
VIDSCLK<45>
VIDALERT_N<45>
VIDSOUT<45>
CPU_PWR_DEBUG#<9>
H_VR_EN<45>H_VCCST_PWRGD<9>
H_VR_READY<45>
RESET_OUT#<36,9>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (10/12)
15 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (10/12)
15 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (10/12)
15 48Wednesday, March 19, 2014
Compal Electronics, Inc.
CC85 22U_0603_6.3V6M@EMC@ CC85 22U_0603_6.3V6M@EMC@1 2
CC
34
10
U_
06
03
_6
.3V
6M
CC
34
10
U_
06
03
_6
.3V
6M
12
BDW_ULT_DDR3L
HSW ULT POWER
12 OF 19
UC1L
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
HSW ULT POWER
12 OF 19
UC1L
BDW-ULT-DDR3L_BGA1168
VCCIO_OUTA59
VCCIOA_OUTE20
RSVDAD23
RSVDAB23
RSVDAC58
VCCF59
VDDQAY44 VDDQAY40 VDDQAY35
RSVDAA59
RSVDU59
RSVDV59
RSVDAG58 RSVDAC59 RSVDAE60
RSVDAD59
VCCSTAC22
VDDQAY50
RSVDN58
VCC_SENSEE63
RSVDAA23
RSVDAE59
VCCST_PWRGDB59
VR_READYC59 VR_ENF60
VDDQAR48 VDDQAP43 VDDQAN33 VDDQAJ37 VDDQAJ33 VDDQAJ31 VDDQAH26
RSVDJ58 RSVDL59
VCCC24
VCCC28
VCCC32
VCCAG57
VCCW57VCCU57
VCCM23
VCCM57
VCCP57
VCCL22VCCK57
VCCH23
VCCJ23
VCCG55
VCCG57
VCCG49
VCCG51
VCCG53
VCCG45
VCCG47
VCCG43
VCCG39
VCCG41
VCCG37VCCG35VCCG33
VCCG29
VCCG31
VCCG27VCCG25VCCG23
VCCF52
VCCF56
VCCF48VCCF44VCCF40
VCCF28
VCCF32
VCCF36
VCCF24VCCE57
VCCE51
VCCE53
VCCE55
VCCE47
VCCE49
VCCE41
VCCE43
VCCE45
VCCE37
VCCE39
VCCE31
VCCE33
VCCE35
VCCE27
VCCE29
VCCC56
VCCE23
VCCE25
VCCC48
VCCC52
VCCC36
VCCC40
VCCC44
VCCK23
VCCAD57 VCCAB57
VCCSTAE23 VCCSTAE22
VIDSOUTL63 VIDSCLKN63 VIDALERTL62
VSSP62
RSVD_TPP60
RSVD_TPP61
RSVD_TPN59
RSVD_TPN61
RSVDT59
RSVDAD60
VSSD63
PWR_DEBUGH59
T74@ PAD~DT74@ PAD~D
CC
27
2.2
U_
04
02
_6
.3V
6M
CC
27
2.2
U_
04
02
_6
.3V
6M
12
RC
20
81
10
_0
40
2_
1%
RC
20
81
10
_0
40
2_
1%
12
CC
36
22
U_
06
03
_6
.3V
6M
CC
36
22
U_
06
03
_6
.3V
6M
12
PJP23
PAD-OPEN1x1m
@ PJP23
PAD-OPEN1x1m
@1 2
UC8
74AUP1G07GW_TSSOP5
UC8
74AUP1G07GW_TSSOP5
NC1
A2
GND3 Y
4
VCC5
CC
30
@1
0U
_0
60
3_
6.3
V6
MC
C3
0@
10
U_
06
03
_6
.3V
6M
12
CC79 22U_0603_6.3V6M@EMC@ CC79 22U_0603_6.3V6M@EMC@1 2
RC
19
9@1
0K
_0
40
2_
5%
RC
19
9@1
0K
_0
40
2_
5%
12
CC
29
10
U_
06
03
_6
.3V
6M
CC
29
10
U_
06
03
_6
.3V
6M
12
RC196 0_0603_5%@ RC196 0_0603_5%@12
CC35@ 0.1U_0402_25V6CC35@ 0.1U_0402_25V61 2
CC
32
10
U_
06
03
_6
.3V
6M
CC
32
10
U_
06
03
_6
.3V
6M
12
T75@ PAD~DT75@ PAD~D
RC
20
21
K_
04
02
_5
%R
C2
02
1K
_0
40
2_
5%
12
RC2011.5K_0402_5% RC2011.5K_0402_5%12
CC
37
@
1U
_0
40
2_
6.3
V6
KC
C3
7
@
1U
_0
40
2_
6.3
V6
K
12
CC
28
2.2
U_
04
02
_6
.3V
6M
CC
28
2.2
U_
04
02
_6
.3V
6M
12
RC20743_0402_5% RC20743_0402_5%12
CC
26
@2
.2U
_0
40
2_
6.3
V6
MC
C2
6@
2.2
U_
04
02
_6
.3V
6M
12CC84 22U_0603_6.3V6M@EMC@ CC84 22U_0603_6.3V6M@EMC@
1 2
T77@ PAD~DT77@ PAD~D
CC23 22U_0603_6.3V6M@EMC@ CC23 22U_0603_6.3V6M@EMC@1 2
RC
20
91
00
_0
40
2_
1%
RC
20
91
00
_0
40
2_
1%
12
CC24100P_0402_50V8J
@EMC@
CC24100P_0402_50V8J
@EMC@
1
2
RC
19
8@
10
K_
04
02
_5
%R
C1
98
@1
0K
_0
40
2_
5%
12
RC
20
47
5_
04
02
_1
%R
C2
04
75
_0
40
2_
1%
12
CC
31
10
U_
06
03
_6
.3V
6M
CC
31
10
U_
06
03
_6
.3V
6M
12
T76@ PAD~DT76@ PAD~D
CC
33
@1
0U
_0
60
3_
6.3
V6
MC
C3
3@
10
U_
06
03
_6
.3V
6M
12
RC197
150_0402_5%
RC197
150_0402_5%
12
CC
25
@2
.2U
_0
40
2_
6.3
V6
MC
C2
5@
2.2
U_
04
02
_6
.3V
6M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CC70 close to Pin J17
CC71 close to Pin R21
CC64 place near V8
CC63 place near AC9
CC57 place near AH14
CC72 place near AG16
CC69 place near U8
CC48,CC49, CC50 place near AG10
CC61 CC62 place near AE9
CC59 and CC60 place near
J11; CC58 place near AE8
CC54 place near Y8
CC80 place near AH10
CC68 place near AA21
CC56 place near B11
CC47 place near B18
CC40 place near K9;
CC44 place near L10
CC43 place near M9
CC78 place near J18
CC82 place near A20
CC65 place near AG19
CC73 place near AH11
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
VCCHSIO
S0 Iccmax = 1.838A
VCCUSB3PLL
S0 Iccmax = 41mA
VCCSATA3PLL
S0 Iccmax = 42mA
VCCAPLL
S0 Iccmax = 57mA
VCCDSW3_3
S0 Iccmax = 114mA
VCCCLK
S0 Iccmax = 200mA
VCCACLKPLL
S0 Iccmax = 31mA
VCCSUS3_3
S0 Iccmax = 63mA
2013/06/10 refer 6L_WP chnage to +3.3V_M, 6/14 change back
2013/06/10 refer 6L_WP chnage to float,6/14 change back
Reminder below power rail need isolation for layout refer
attach file for more detail that from Intel review feedback.
intel DG Rev 1.2 , page 500
47.3 Boot Strap Capacitor
CC97 place near AH10
+DCPRRTC
+PCH_VCCDSW
+PCH_VCCDSW
+P
CH
_V
CC
DS
W_
R
+1.05V_MODPHY +1.05V_MODPHY_PCH
+1.05V_MODPHY_PCH
+PCH_AUSB3PLL+1.05V_MODPHY
+PCH_AUSB3PLL
+PCH_ASATA3PLL+1.05V_MODPHY
+PCH_ASATA3PLL
+V1.05S_APLLOPI+1.05V_RUN
+V1.05S_APLLOPI
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
+PCH_VCC1P05
+PCH_VCCACLKPLL
+1.05V_RUN
+PCH_RTC_VCCSUS3_3 +3.3V_ALW_PCH
+3.3V_ALW
+PCH_RTC_VCCSUS3_3
+3.3V_M
+1.05V_M
+1.05V_M
+1.5V_RUN
+3.3V_RUN
+1.05V_RUN
+1.05V_RUN+1.05V_M
+3.3V_RUN
+3.3V_ALW_PCH
+1.05V_RUN
+PCH_VCCDSW3_3+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_ALW_PCH
+1.05V_RUN
+PCH_VCC1P05+1.05V_RUN
+PCH_VCCACLKPLL+1.05V_RUN
+RTC_CELL
+3.3V_RUN
+PCH_VCCDSW+PCH_VCCDSW3_3
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (11/12)
16 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (11/12)
16 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
CPU (11/12)
16 48Wednesday, March 19, 2014
Compal Electronics, Inc.
LC5
2.2UH_LQM2MPN2R2NG0L_30%
LC5
2.2UH_LQM2MPN2R2NG0L_30%1 2
CC
49
0.1
U_0402_10V
7K
CC
49
0.1
U_0402_10V
7K
12
CC
77
100U
_1206_6.3
V6M
CC
77
100U
_1206_6.3
V6M
12
CC
50
1U
_0402_6.3
V6K
CC
50
1U
_0402_6.3
V6K
12
+
CC
42
33
0U
_D
3_
2.5
VY
_R
6M
@E
MC
@+
CC
42
33
0U
_D
3_
2.5
VY
_R
6M
@E
MC
@
1
2
CC
80
@1U
_0402_6.3
V6K
CC
80
@1U
_0402_6.3
V6K
12
RC212 @0_0402_5% RC212 @0_0402_5%12
CC
44
1U
_0402_6.3
V6K
CC
44
1U
_0402_6.3
V6K
12
RC211 5.11_0402_1%RC211 5.11_0402_1%12
CC
70
1U
_0402_6.3
V6K
CC
70
1U
_0402_6.3
V6K
12
RC216 0_0402_5%@ RC216 0_0402_5%@1 2
CC
63
22U
_0603_6.3
V6M
CC
63
22U
_0603_6.3
V6M
12
CC
51
22U
_0603_6.3
V6M
CC
51
22U
_0603_6.3
V6M
12
RC217@ 0_0402_5%RC217@ 0_0402_5%1 2
CC
78
1U
_0402_6.3
V6K
CC
78
1U
_0402_6.3
V6K
12
+
CC
39
@330U
_D
3_2.5
VY
_R
6M
+
CC
39
@330U
_D
3_2.5
VY
_R
6M
12
CC
59
1U
_0402_6.3
V6K
CC
59
1U
_0402_6.3
V6K
12
CC
73
1U
_0402_6.3
V6K
CC
73
1U
_0402_6.3
V6K
12
CC
48
@
0.1
U_0402_10V
7K
CC
48
@
0.1
U_0402_10V
7K
12
LC2
2.2UH_LQM2MPN2R2NG0L_30%
LC2
2.2UH_LQM2MPN2R2NG0L_30%1 2
PJP51@
PAD-OPEN1x1m
PJP51@
PAD-OPEN1x1m
1 2
USB2
THERMAL SENSOR
HSIO
BDW_ULT_DDR3L
USB3
OPI
RTC
GPIO/LPC
VRM
HDA
SERIAL IO
SUS OSCILLATOR
SPI
LPT LP POWER
CORE
13 OF 19
UC1M
BDW-ULT-DDR3L_BGA1168
USB2
THERMAL SENSOR
HSIO
BDW_ULT_DDR3L
USB3
OPI
RTC
GPIO/LPC
VRM
HDA
SERIAL IO
SUS OSCILLATOR
SPI
LPT LP POWER
CORE
13 OF 19
UC1M
BDW-ULT-DDR3L_BGA1168
VCCHDAAH14
VCCTS1_5J15
DCPSUS1AD8DCPSUS1AD10
DCPSUSBYPAG20DCPSUSBYPAG19
DCPSUS4AB8
VCCASWAE9
VCCASWAF9
VCCASWAG8
VCCSUS3_3AH11
VCCRTCAG10
DCPRTCAE7
VCCSPIY8
VCCASWAG14
VCCASWAG13
VCC3_3K16VCC3_3K14
VCCSDIOT9VCCSDIOU8
DCPSUS3J13
VCCAPLLW21
VCCHSIOK9
VCCHSIOL10
VCCHSIOM9
VCCAPLLAA21 RSVD
Y20
VCCSATA3PLLB11 VCCUSB3PLLB18
VCC1_05N8
VCC1_05P9
VCC1_05J11
VCC1_05H11
VCC1_05H15
VCC1_05AE8
VCC1_05AF22
VCCSUS3_3AE21 VCCSUS3_3AE20 RSVD
V21 RSVDM20 RSVDK18 VCCCLKT21 VCCCLKR21 VCCCLKJ17 VCCACLKPLLA20
VCC3_3W9 VCC3_3V8 VCCDSW3_3
AH10
VCCSUS3_3AC9
RSVDAC20
VCCSUS3_3AA9
DCPSUS2AH13
VCC1_05AG16
VCC1_05AG17
VCCCLKJ18
VCCCLKK19
CC
57
0.1
U_0402_10V
7K
CC
57
0.1
U_0402_10V
7K
12
CC
58
1U
_0402_6.3
V6K
CC
58
1U
_0402_6.3
V6K
12
CC
64
22U
_0603_6.3
V6M
CC
64
22U
_0603_6.3
V6M
12
CC
71
1U
_0402_6.3
V6K
CC
71
1U
_0402_6.3
V6K
12
CC
67
100U
_1206_6.3
V6M
CC
67
100U
_1206_6.3
V6M
12
LC4
2.2UH_LQM2MPN2R2NG0L_30%
LC4
2.2UH_LQM2MPN2R2NG0L_30%1 2
CC
82
1U
_0402_6.3
V6K
CC
82
1U
_0402_6.3
V6K
12
LC1
2.2UH_LQM2MPN2R2NG0L_30%
LC1
2.2UH_LQM2MPN2R2NG0L_30%1 2
LC3
2.2UH_LQM2MPN2R2NG0L_30%
LC3
2.2UH_LQM2MPN2R2NG0L_30%1 2
CC
56
22U
_0603_6.3
V6M
CC
56
22U
_0603_6.3
V6M
12
CC
47
22U
_0603_6.3
V6M
CC
47
22U
_0603_6.3
V6M
12
CC97 0.47U_0402_10V6K@CC97 0.47U_0402_10V6K@
1 2
CC
53
@1U
_0402_6.3
V6K
CC
53
@1U
_0402_6.3
V6K
12
CC
66
0.1
U_0402_10V
7K
CC
66
0.1
U_0402_10V
7K
12
CC
43
@1U
_0402_6.3
V6K
CC
43
@1U
_0402_6.3
V6K
12
CC
60
10U
_0603_6.3
V6M
CC
60
10U
_0603_6.3
V6M
12C
C6
22
2U
_0
60
3_
6.3
V6
M@
CC
62
22
U_
06
03
_6
.3V
6M
@
1
2
CC
54
@0.1
U_0402_10V
7K
CC
54
@0.1
U_0402_10V
7K
12
CC
55
22U
_0603_6.3
V6M
CC
55
22U
_0603_6.3
V6M
12
CC
81
100U
_1206_6.3
V6M
CC
81
100U
_1206_6.3
V6M
12
+
CC
41
33
0U
_D
3_
2.5
VY
_R
6M
@E
MC
@+
CC
41
33
0U
_D
3_
2.5
VY
_R
6M
@E
MC
@
1
2
CC
68
1U
_0402_6.3
V6K
CC
68
1U
_0402_6.3
V6K
12
CC
61
1U
_0402_6.3
V6K
CC
61
1U
_0402_6.3
V6K
12
CC
40
1U
_0402_6.3
V6K
CC
40
1U
_0402_6.3
V6K
12
CC
69
1U
_0402_6.3
V6K
CC
69
1U
_0402_6.3
V6K
12
CC
65
1U
_0402_6.3
V6K
CC
65
1U
_0402_6.3
V6K
12
CC
72
1U
_0402_6.3
V6K
CC
72
1U
_0402_6.3
V6K
12
CC52 0.1U_0402_10V7KCC52 0.1U_0402_10V7K1 2
RC213@0_0402_5% RC213@0_0402_5%12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAD Note: RC218 SHOULD BE PLACED CLOSE TO CPU
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
VSSSENSE
VSSSENSE <45>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (12/12)
17 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (12/12)
17 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
CPU (12/12)
17 48Wednesday, March 19, 2014
Compal Electronics, Inc.
BDW_ULT_DDR3L
15 OF 19
UC1O
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
15 OF 19
UC1O
BDW-ULT-DDR3L_BGA1168
VSSAV16
VSSAV24
VSSAV33 VSSAV28
VSSAV20
VSSAR11
VSSAU33
VSSAU55
VSSD26
VSSD27
VSSD25VSSD23
VSSAV55
VSSAP38
VSSAP29
VSSAP31
VSSAP39
VSSAP52
VSSAP54
VSSAP57
VSSAR15
VSSAR17
VSSAR23
VSSAR31
VSSAR33
VSSAR39
VSSAR43
VSSAR49
VSSAR5
VSSAR52
VSSAT13
VSSAT35
VSSAT37
VSSAT40
VSSAT42
VSSAT43
VSSAT46
VSSAT49
VSSAT61
VSSAT62
VSSAT63
VSSAU1
VSSAU18
VSSAU22
VSSAU30
VSSAU51
VSSAU53
VSSAU57
VSSAU59
VSSAV14
VSSAV36
VSSAV39
VSSAV41
VSSAV43
VSSAV46
VSSAV49
VSSAV51
VSSAW24
VSSAW33
VSSAW35
VSSAW37
VSSAW4
VSSAW42
VSSAW44
VSSAW47
VSSAW50
VSSAW51
VSSAW59
VSSAY11
VSSAY16
VSSAY18
VSSAY22
VSSAY24
VSSAY26
VSSAY30
VSSAY33
VSSAY4
VSSAY51
VSSAY53
VSSAY57
VSSAY59
VSSAY6
VSSB20
VSSB24
VSSB26
VSSB28
VSSB32
VSSB36
VSSB4
VSSB40
VSSB44
VSSB48
VSSB52
VSSB56
VSSB60
VSSC18
VSSC20
VSSC25
VSSC27
VSSC38
VSSC39
VSSC57
VSSD12
VSSD14
VSSD18
VSSD2
VSSD21
VSSD29
VSSD30
VSSD31
VSSAV34
VSSAV59
VSSAV8
VSSAW16
VSSAW40
VSSAW60
VSSC11
VSSC14
VSSAU28 VSSAU26 VSSAU24
VSSAU20
VSSAU16
VSSAP48
VSSAP26
VSSAP22
VSSAP23
VSSAP3
RC218 100_0402_1%RC218 100_0402_1%1 2
BDW_ULT_DDR3L
16 OF 19
UC1P
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
16 OF 19
UC1P
BDW-ULT-DDR3L_BGA1168
VSSD59
VSSY63VSSY59VSSY10
VSSV10VSSU9
VSSU22
VSSU61
VSSU20VSST58VSST1
VSSR22
VSSR8
VSSR10VSSP63VSSP59VSSN3VSSN10VSSM22
VSSL61VSSL58VSSL20VSSL18VSSL17VSSL15VSSL13VSSK12VSSK1VSSJ63VSSJ59VSSJ22
VSSH17
VSSF38
VSSF50
VSSAH16
VSSF42
VSSF34
VSSE17
VSSG22
VSSG6
VSSD39 VSSD38 VSSD37 VSSD35 VSSD34
VSSD43
VSSD45
VSSD46
VSSD47
VSSD5
VSSD50
VSSD51
VSSD53
VSSD54
VSSD55
VSSD57
VSSD62
VSSD8
VSSE11
VSSF46
VSSF54
VSSF58
VSSF61
VSSG18
VSSG3
VSSG5
VSSG8
VSSH13
VSSD42 VSSD41
VSSH57
VSSL7
VSSD33
VSSJ10
VSSV58
VSSAH46
VSSV23
VSS_SENSEE62
VSSW22VSSW20VSSV7VSSV3
VSSD49
VSSF30 VSSF26 VSSF20
BDW_ULT_DDR3L
14 OF 19
UC1N
BDW-ULT-DDR3L_BGA1168
BDW_ULT_DDR3L
14 OF 19
UC1N
BDW-ULT-DDR3L_BGA1168
VSSAH44
VSSAH49
VSSAH51
VSSAH38
VSSAP10
VSSAN49
VSSAN40
VSSAN23
VSSAM1
VSSAL51
VSSA28
VSSA11
VSSA14
VSSA18
VSSA24
VSSA32
VSSA36
VSSA40
VSSA44
VSSA48
VSSA52
VSSA56
VSSAA1
VSSAA58
VSSAB10
VSSAB20
VSSAB22
VSSAB7
VSSAC61
VSSAD21
VSSAD3
VSSAD63
VSSAE10
VSSAE5
VSSAE58
VSSAF11
VSSAF12
VSSAF14
VSSAF17
VSSAG1
VSSAG11
VSSAG23
VSSAG60
VSSAG62
VSSAG63
VSSAH19
VSSAH24
VSSAH28
VSSAH30
VSSAH32
VSSAH40
VSSAH42
VSSAH53
VSSAH55
VSSAH57
VSSAJ13
VSSAJ14
VSSAJ23
VSSAJ25
VSSAJ27
VSSAJ29
VSSAJ43
VSSAJ45
VSSAJ50
VSSAJ52
VSSAJ56
VSSAJ58
VSSAJ60
VSSAJ63
VSSAK23
VSSAK3
VSSAK52
VSSAL10
VSSAL13
VSSAL17
VSSAL20
VSSAL22
VSSAL23
VSSAL26
VSSAL29
VSSAL31
VSSAL33
VSSAL36
VSSAL39
VSSAL40
VSSAL45
VSSAL46
VSSAL52
VSSAL54
VSSAL57
VSSAL60
VSSAL61
VSSAM17
VSSAM23
VSSAM31
VSSAM52
VSSAN17
VSSAN31
VSSAN32
VSSAN35
VSSAN36
VSSAN39
VSSAN42
VSSAN43
VSSAN45
VSSAN46
VSSAN48
VSSAN51
VSSAN52
VSSAN60
VSSAN63
VSSAN7
VSSAP17
VSSAP20
VSSAF18
VSSAF15
VSSAJ54
VSSAJ47
VSSAJ35
VSSAJ41VSSAJ39
VSSAH36 VSSAH34
VSSAH22 VSSAH20
VSSAH17
VSSAG61
VSSAG21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H=4mmReverse Type
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socketLayout Note:
Place near JDIMM1
Layout Note:
Place near
JDIMM1.203,204
DDR3L SODIMM ODT GENERATION
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY20130730 SP07000LT00 CIS Link OK
DDR3_DRAMRST#
DDR_A_BS0DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_D0DDR_A_D1
DDR_A_D10 DDR_A_D11
DDR_A_D12DDR_A_D13
DDR_A_D14 DDR_A_D15
DDR_A_D16DDR_A_D17
DDR_A_D18DDR_A_D19
DDR_A_D2
DDR_A_D20DDR_A_D21
DDR_A_D22DDR_A_D23
DDR_A_D24DDR_A_D25
DDR_A_D26DDR_A_D27
DDR_A_D28DDR_A_D29
DDR_A_D3
DDR_A_D30DDR_A_D31
DDR_A_D32DDR_A_D33
DDR_A_D34DDR_A_D35
DDR_A_D36 DDR_A_D37
DDR_A_D38DDR_A_D39
DDR_A_D4
DDR_A_D40DDR_A_D41
DDR_A_D42DDR_A_D43
DDR_A_D44 DDR_A_D45
DDR_A_D46DDR_A_D47
DDR_A_D48DDR_A_D49
DDR_A_D5
DDR_A_D50DDR_A_D51
DDR_A_D52DDR_A_D53
DDR_A_D54DDR_A_D55
DDR_A_D56DDR_A_D57
DDR_A_D58DDR_A_D59
DDR_A_D6
DDR_A_D60DDR_A_D61
DDR_A_D62DDR_A_D63
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0DDR_A_MA1
DDR_A_MA10
DDR_A_MA11DDR_A_MA12
DDR_A_MA13
DDR_A_MA14DDR_A_MA15
DDR_A_MA2DDR_A_MA3
DDR_A_MA4DDR_A_MA5DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_RAS#
DDR_A_WE#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_CLK_DDR#0 M_CLK_DDR#1M_CLK_DDR0 M_CLK_DDR1
M_ODT0
M_ODT1
0.675V_DDR_VTT_ON
0.675V_DDR_VTT_ON
M_ODT0
M_ODT1
+0.675V_DDR_VTT
+1.35V_MEM
+1.35V_MEM
+1.35V_MEM
+1.35V_MEM+1.35V_MEM
+3.3V_RUN
+0.675V_DDR_VTT
+DIMM1_VREF_DQ
+0.675V_DDR_VTT
+5V_ALW
+1.35V_MEM
+1.35V_MEM
+SM_VREF_CA_DIMM
+SM_VREF_DQ0
+1.35V_MEM
+DIMM1_VREF_DQ
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
DDR_A_DQS#[0..7]<8>
DDR3_DRAMRST#_CPU <9>DDR3_DRAMRST#<19>
DDR_CKE0_DIMMA<8>
DDR_A_BS2<8>
DDR_CS1_DIMMA#<8>
DDR_A_WE#<8>DDR_A_CAS#<8>
DDR_A_BS0<8>DDR_A_BS1 <8>
DDR_A_RAS# <8>
M_CLK_DDR1 <8>M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
M_CLK_DDR0<8>
DDR_CKE1_DIMMA <8>
DDR_CS0_DIMMA# <8>
DDR_XDP_WAN_SMBCLK <19,7,9>DDR_XDP_WAN_SMBDAT <19,7,9>
DDR_PG_CTRL<9>
M_ODT2 <19>
M_ODT3 <19>
0.675V_DDR_VTT_ON <42>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DDR3L
18 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DDR3L
18 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DDR3L
18 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RD13 66.5_0402_1%RD13 66.5_0402_1%1 2
RD15@ 0_0402_5%RD15@ 0_0402_5%1 2
CD
27
0.1
U_0402_25V
6C
D27
0.1
U_0402_25V
6
12
CD
13
@10U
_0603_6.3
V6M
CD
13
@10U
_0603_6.3
V6M
12
RD
61.8
K_0402_1%
RD
61.8
K_0402_1%
12
CD
24
0.1
U_0402_25V
6C
D24
0.1
U_0402_25V
6
12
RD11 66.5_0402_1%RD11 66.5_0402_1%1 2
CD
26
0.1
U_0402_25V
6C
D26
0.1
U_0402_25V
6
12
CD
22
0.1
U_0402_25V
6C
D22
0.1
U_0402_25V
6
12
JDIMM1 CONN@
LCN_DAN06-K4406-0103
JDIMM1 CONN@
LCN_DAN06-K4406-0103
VREF_DQ1
VSS3
DQ05
DQ17
VSS9
DM011
VSS13
DQ215
DQ317
VSS19
DQ821
DQ923
VSS25
DQS1#27
DQS129
VSS31
DQ1033
DQ1135
VSS37
DQ1639
VSS2
DQ44
DQ56
VSS8
DQS0#10
DQS012
VSS14
DQ616
DQ718
VSS20
DQ1222
DQ1324
VSS26
DM128
RESET#30
VSS32
DQ1434
DQ1536
VSS38
DQ2040
DQ1741
VSS43
DQS2#45
DQS247
VSS49
DQ1851
DQ1953
VSS55
DQ2457
DQ2559
VSS61
DM363
VSS65
DQ2667
DQ2769
VSS71
CKE073
VDD75
NC77
BA279
VDD81
A12/BC#83
A985
VDD87
A889
A591
VDD93
A395
A197
VDD99
CK0101
CK0#103
VDD105
A10/AP107
BA0109
VDD111
WE#113
CAS#115
VDD117
A13119
S1#121
VDD123
TEST125
VSS127
DQ32129
DQ33131
VSS133
DQS4#135
DQS4137
VSS139
DQ34141
DQ35143
VSS145
DQ40147
DQ41149
VSS151
DM5153
VSS155
DQ42157
DQ43159
VSS161
DQ48163
DQ49165
VSS167
DQS6#169
DQS6171
VSS173
DQ50175
DQ51177
VSS179
DQ56181
DQ57183
VSS185
DM7187
VSS189
DQ58191
DQ59193
VSS195
SA0197
VDDSPD199
DQ2142
VSS44
DM246
VSS48
DQ2250
DQ2352
VSS54
DQ2856
DQ2958
VSS60
DQS3#62
DQS364
VSS66
DQ3068
DQ3170
VSS72
CKE174
VDD76
A1578
A1480
VDD82
A1184
A786
VDD88
A690
A492
VDD94
A296
A098
VDD100
CK1102
CK1#104
VDD106
BA1108
RAS#110
VDD112
S0#114
ODT0116
VDD118
ODT1120
NC122
VDD124
VREF_CA126
VSS128
DQ36130
DQ37132
VSS134
DM4136
VSS138
DQ38140
DQ39142
VSS144
DQ44146
DQ45148
VSS150
DQS5#152
DQS5154
VSS156
DQ46158
DQ47160
VSS162
DQ52164
DQ53166
VSS168
DM6170
VSS172
DQ54174
DQ55176
VSS178
DQ60180
DQ61182
VSS184
DQS7#186
DQS7188
VSS190
DQ62192
DQ63194
VSS196
EVENT#198
SDA200
SA1201
VTT203
GND1205
SCL202
VTT204
GND2206
BOSS1207
BOSS2208
CD
71U
_0402_6.3
V6K
CD
71U
_0402_6.3
V6K
12
RD
92
20
K_
04
02
_5
%R
D9
22
0K
_0
40
2_
5%
12
CD
21U
_0402_6.3
V6K
CD
21U
_0402_6.3
V6K
12
CD
52.2
U_0402_6.3
V6M
CD
52.2
U_0402_6.3
V6M
12
CD
29
10U
_0603_6.3
V6M
CD
29
10U
_0603_6.3
V6M
12
+
CD
20
330U
_D
3_2.5
VY
_R
6M
+
CD
20
330U
_D
3_2.5
VY
_R
6M
12
CD
6@
0.1
U_0402_25V
6C
D6
@0.1
U_0402_25V
6
12
RD
2470_0402_5%
RD
2470_0402_5%
12
CD
14
10U
_0603_6.3
V6M
CD
14
10U
_0603_6.3
V6M
12
RD3@ 0_0402_5%RD3@ 0_0402_5%1 2
CD
91U
_0402_6.3
V6K
CD
91U
_0402_6.3
V6K
12
CD
31
@2.2
U_0402_6.3
V6M
CD
31
@2.2
U_0402_6.3
V6M
12
CD
15
10U
_0603_6.3
V6M
CD
15
10U
_0603_6.3
V6M
12
RD
14
@2M
_0402_5%
RD
14
@2M
_0402_5%
12
CD
31U
_0402_6.3
V6K
CD
31U
_0402_6.3
V6K
12
CD
41U
_0402_6.3
V6K
CD
41U
_0402_6.3
V6K
12
RD
724.9
_0402_1%
RD
724.9
_0402_1%
12
CD
18
10U
_0603_6.3
V6M
CD
18
10U
_0603_6.3
V6M
12
CD
17
10U
_0603_6.3
V6M
CD
17
10U
_0603_6.3
V6M
12
CD
23
2.2
U_0402_6.3
V6M
CD
23
2.2
U_0402_6.3
V6M
12
G
D S
QD1
L2N7002WT1G_SC-70-3
G
D S
QD1
L2N7002WT1G_SC-70-3
2
1 3
UD1
74AUP1G07GW_TSSOP5
UD1
74AUP1G07GW_TSSOP5
NC1
A2
GND3 Y
4
VCC5
CD
10.1
U_0402_25V
6C
D1
0.1
U_0402_25V
6
12
CD
11
1U
_0402_6.3
V6K
CD
11
1U
_0402_6.3
V6K
12
CD
12
10U
_0603_6.3
V6M
CD
12
10U
_0603_6.3
V6M
12
RD5 2_0402_1%RD5 2_0402_1%1 2
CD
19
10U
_0603_6.3
V6M
CD
19
10U
_0603_6.3
V6M
12
CD
21
0.0
22U
_0402_16V
7K
CD
21
0.0
22U
_0402_16V
7K
12
CD
10
1U
_0402_6.3
V6K
CD
10
1U
_0402_6.3
V6K
12
CD
25
0.1
U_0402_25V
6C
D25
0.1
U_0402_25V
6
12
CD
16
@10U
_0603_6.3
V6M
CD
16
@10U
_0603_6.3
V6M
12
RD16@ 0_0402_5%RD16@ 0_0402_5%1 2
CD
32
0.1
U_0402_25V
6C
D32
0.1
U_0402_25V
6
12
CD
81U
_0402_6.3
V6K
CD
81U
_0402_6.3
V6K
12
RD
41.8
K_0402_1%
RD
41.8
K_0402_1%
12
CD
28
10U
_0603_6.3
V6M
CD
28
10U
_0603_6.3
V6M
12
CD30@ 0.1U_0402_25V6CD30@ 0.1U_0402_25V61 2
RD10 66.5_0402_1%RD10 66.5_0402_1%1 2
RD12 66.5_0402_1%RD12 66.5_0402_1%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H=4mmReverse Type
CAD NOTE
PLACE THE CAP NEAR TO DIMM RESET PIN
Note:
Check voltage tolerance of
VREF_DQ at the DIMM socket
Layout Note:
Place near JDIMM2
Layout Note:
Place near
JDIMM2.203,204
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
20130730 SP07000LT00 CIS Link OK
DDR3_DRAMRST#
DDR_B_BS0DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_D0DDR_B_D1
DDR_B_D10DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16DDR_B_D17
DDR_B_D18DDR_B_D19
DDR_B_D2
DDR_B_D20DDR_B_D21
DDR_B_D22DDR_B_D23
DDR_B_D24DDR_B_D25
DDR_B_D26DDR_B_D27
DDR_B_D28DDR_B_D29
DDR_B_D3
DDR_B_D30DDR_B_D31
DDR_B_D32DDR_B_D33
DDR_B_D34DDR_B_D35
DDR_B_D36 DDR_B_D37
DDR_B_D38DDR_B_D39
DDR_B_D4
DDR_B_D40DDR_B_D41
DDR_B_D42DDR_B_D43
DDR_B_D44DDR_B_D45
DDR_B_D46DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D5
DDR_B_D50
DDR_B_D51DDR_B_D52
DDR_B_D53DDR_B_D54
DDR_B_D55
DDR_B_D56DDR_B_D57
DDR_B_D58DDR_B_D59
DDR_B_D6
DDR_B_D60DDR_B_D61
DDR_B_D62DDR_B_D63
DDR_B_D7
DDR_B_D8 DDR_B_D9
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0DDR_B_MA1
DDR_B_MA10
DDR_B_MA11DDR_B_MA12
DDR_B_MA13
DDR_B_MA14DDR_B_MA15
DDR_B_MA2DDR_B_MA3
DDR_B_MA4DDR_B_MA5DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_RAS#
DDR_B_WE#
DDR_CKE2_DIMMB DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_CLK_DDR#2 M_CLK_DDR#3M_CLK_DDR2 M_CLK_DDR3
M_ODT2
+1.35V_MEM
+1.35V_MEM +1.35V_MEM
+1.35V_MEM
+0.675V_DDR_VTT
+DIMM2_VREF_DQ
+3.3V_RUN
+3.3V_RUN
+0.675V_DDR_VTT +0.675V_DDR_VTT
+1.35V_MEM
+SM_VREF_CA+SM_VREF_CA_DIMM
+SM_VREF_DQ1
+1.35V_MEM
+DIMM2_VREF_DQ
+SM_VREF_CA_DIMM
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..15]<8>
DDR_B_DQS#[0..7]<8>
DDR3_DRAMRST# <18>
DDR_B_CAS#<8>DDR_B_WE#<8>
DDR_CKE2_DIMMB<8>
DDR_B_BS0<8>
DDR_B_BS2<8>
DDR_CS3_DIMMB#<8>
M_CLK_DDR2<8>M_CLK_DDR#2<8>
DDR_CKE3_DIMMB <8>
DDR_B_RAS# <8>
DDR_B_BS1 <8>
M_ODT2 <18>DDR_CS2_DIMMB# <8>
M_CLK_DDR3 <8>M_CLK_DDR#3 <8>
M_ODT3 <18>
DDR_XDP_WAN_SMBCLK <18,7,9>DDR_XDP_WAN_SMBDAT <18,7,9>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DDR3L
19 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DDR3L
19 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DDR3L
19 48Wednesday, March 19, 2014
Compal Electronics, Inc.
CD
431U
_0402_6.3V6K
CD
431U
_0402_6.3V6K
12
CD
640.1U
_0402_25V6
CD
640.1U
_0402_25V6
12
CD
4910U
_0603_6.3V6M
CD
4910U
_0603_6.3V6M
12
CD
391U
_0402_6.3V6K
CD
391U
_0402_6.3V6K
12
RD23 2_0402_1%RD23 2_0402_1%1 2
CD
63@
2.2U_0402_6.3V
6MC
D63
@2.2U
_0402_6.3V6M
12
CD
421U
_0402_6.3V6K
CD
421U
_0402_6.3V6K
12
RD
221.8K
_0402_1%R
D22
1.8K_0402_1%
12
CD
600.1U
_0402_25V6
CD
600.1U
_0402_25V6
12
CD
35@
0.1U_0402_25V
6C
D35
@0.1U
_0402_25V6
12
RD27@ 0_0402_5%RD27@ 0_0402_5%12
CD
411U
_0402_6.3V6K
CD
411U
_0402_6.3V6K
12
CD
360.022U
_0402_16V7K
CD
360.022U
_0402_16V7K
12
CD
332.2U
_0402_6.3V6M
CD
332.2U
_0402_6.3V6M
12
RD
2124.9_0402_1%
RD
2124.9_0402_1%
12
CD
340.1U
_0402_25V6
CD
340.1U
_0402_25V6
12
CD
401U
_0402_6.3V6K
CD
401U
_0402_6.3V6K
12
CD
562.2U
_0402_6.3V6M
CD
562.2U
_0402_6.3V6M
12
JDIMM2 CONN@
LCN_DAN06-K4406-0103
JDIMM2 CONN@
LCN_DAN06-K4406-0103
VREF_DQ1
VSS3
DQ05
DQ17
VSS9
DM011
VSS13
DQ215
DQ317
VSS19
DQ821
DQ923
VSS25
DQS1#27
DQS129
VSS31
DQ1033
DQ1135
VSS37
DQ1639
VSS2
DQ44
DQ56
VSS8
DQS0#10
DQS012
VSS14
DQ616
DQ718
VSS20
DQ1222
DQ1324
VSS26
DM128
RESET#30
VSS32
DQ1434
DQ1536
VSS38
DQ2040
DQ1741
VSS43
DQS2#45
DQS247
VSS49
DQ1851
DQ1953
VSS55
DQ2457
DQ2559
VSS61
DM363
VSS65
DQ2667
DQ2769
VSS71
CKE073
VDD75
NC77
BA279
VDD81
A12/BC#83
A985
VDD87
A889
A591
VDD93
A395
A197
VDD99
CK0101
CK0#103
VDD105
A10/AP107
BA0109
VDD111
WE#113
CAS#115
VDD117
A13119
S1#121
VDD123
TEST125
VSS127
DQ32129
DQ33131
VSS133
DQS4#135
DQS4137
VSS139
DQ34141
DQ35143
VSS145
DQ40147
DQ41149
VSS151
DM5153
VSS155
DQ42157
DQ43159
VSS161
DQ48163
DQ49165
VSS167
DQS6#169
DQS6171
VSS173
DQ50175
DQ51177
VSS179
DQ56181
DQ57183
VSS185
DM7187
VSS189
DQ58191
DQ59193
VSS195
SA0197
VDDSPD199
DQ2142
VSS44
DM246
VSS48
DQ2250
DQ2352
VSS54
DQ2856
DQ2958
VSS60
DQS3#62
DQS364
VSS66
DQ3068
DQ3170
VSS72
CKE174
VDD76
A1578
A1480
VDD82
A1184
A786
VDD88
A690
A492
VDD94
A296
A098
VDD100
CK1102
CK1#104
VDD106
BA1108
RAS#110
VDD112
S0#114
ODT0116
VDD118
ODT1120
NC122
VDD124
VREF_CA126
VSS128
DQ36130
DQ37132
VSS134
DM4136
VSS138
DQ38140
DQ39142
VSS144
DQ44146
DQ45148
VSS150
DQS5#152
DQS5154
VSS156
DQ46158
DQ47160
VSS162
DQ52164
DQ53166
VSS168
DM6170
VSS172
DQ54174
DQ55176
VSS178
DQ60180
DQ61182
VSS184
DQS7#186
DQS7188
VSS190
DQ62192
DQ63194
VSS196
EVENT#198
SDA200
SA1201
VTT203
GND1205
SCL202
VTT204
GND2206
BOSS1207
BOSS2208
CD
550.1U
_0402_25V6
CD
550.1U
_0402_25V6
12
CD
540.022U
_0402_16V7K
CD
540.022U
_0402_16V7K
12
CD
5210U
_0603_6.3V6M
CD
5210U
_0603_6.3V6M
12
+
CD
53330U
_D3_2.5V
Y_R
6M
+
CD
53330U
_D3_2.5V
Y_R
6M
12
RD
2524.9_0402_1%
RD
2524.9_0402_1%
12
RD
201.8K
_0402_1%R
D20
1.8K_0402_1%
12
CD
4510U
_0603_6.3V6M
CD
4510U
_0603_6.3V6M
12
RD
181.8K
_0402_1%R
D18
1.8K_0402_1%
12
CD
441U
_0402_6.3V6K
CD
441U
_0402_6.3V6K
12
CD
570.1U
_0402_25V6
CD
570.1U
_0402_25V6
12
RD19 2_0402_1%RD19 2_0402_1%1 2
CD
47@
10U_0603_6.3V
6MC
D47
@10U
_0603_6.3V6M
12
CD
381U
_0402_6.3V6K
CD
381U
_0402_6.3V6K
12
CD
580.1U
_0402_25V6
CD
580.1U
_0402_25V6
12
CD
4810U
_0603_6.3V6M
CD
4810U
_0603_6.3V6M
12
CD
590.1U
_0402_25V6
CD
590.1U
_0402_25V6
12
RD
241.8K
_0402_1%R
D24
1.8K_0402_1%
12
CD
371U
_0402_6.3V6K
CD
371U
_0402_6.3V6K
12
CD
6110U
_0603_6.3V6M
CD
6110U
_0603_6.3V6M
12
RD
28@0_0402_5%
RD
28@0_0402_5%
12
CD
46@
10U_0603_6.3V
6MC
D46
@10U
_0603_6.3V6M
12
CD
5010U
_0603_6.3V6M
CD
5010U
_0603_6.3V6M
12
CD
5110U
_0603_6.3V6M
CD
5110U
_0603_6.3V6M
12
CD
6210U
_0603_6.3V6M
CD
6210U
_0603_6.3V6M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Place near JMINI3
Mini mSATA H=4HDD_DEVSLP
HDD_DET#
HDD_DEVSLP
LPC_LFRAME#LPC_LAD3LPC_LAD2LPC_LAD1LPC_LAD0
PCH_PLTRST#_EC
SATA_PTX_DRX_N1_CSATA_PTX_DRX_P1_C
SATA_PRX_DTX_N1_CSATA_PRX_DTX_P1_C
+3.3V_HDD
+3.3V_HDD
+3.3V_HDD +3.3V_HDD
HDD_DET#<6>
HDD_DEVSLP <12>
LPC_LFRAME# <35,36,7>LPC_LAD3 <35,36,7>LPC_LAD2 <35,36,7>LPC_LAD1 <35,36,7>LPC_LAD0 <35,36,7>
CLK_PCI_LPDEBUG<36,7>
PCH_PLTRST#_EC<27,30,35,36,9>
SATA_PRX_DTX_N1<6>SATA_PRX_DTX_P1<6>
SATA_PTX_DRX_N1<6>SATA_PTX_DRX_P1<6>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
HDD CONN
20 56Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
HDD CONN
20 56Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
HDD CONN
20 56Wednesday, March 19, 2014
Compal Electronics, Inc.
CN4 .01U_0402_16V7KCN4 .01U_0402_16V7K12
CN6 .01U_0402_16V7KCN6 .01U_0402_16V7K12
RN1 10K_0402_5%@ RN1 10K_0402_5%@1 2
JMINI3
LCN_DAN08-52406-0500
CONN@JMINI3
LCN_DAN08-52406-0500
CONN@
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
4545
4747
4949
5151
GND153
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4242
4444
4646
4848
5050
5252
GND254
CN
10.1
U_0402_25V
6C
N1
0.1
U_0402_25V
6
1
2
CN5 .01U_0402_16V7KCN5 .01U_0402_16V7K12
CN
20.1
U_0402_25V
6
@CN
20.1
U_0402_25V
6
@1
2
CN3 .01U_0402_16V7KCN3 .01U_0402_16V7K12
2
2
1
1
B B
A A
Add for solve
pop noise and
detect issue
40 mils trace keep 20 mil spacing
Close to UA1
Place CA29 close to Codec
SLEEVE/RING2 please keep 40 mils trace width
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
Internal Speakers Header
Close to UA1 pin6
Place closely to Pin 13.
Realtek feedback
Prevent the Noise from Combo Jack
while system entry into S3 / S4 /S5
place close to pin27
place close to pin40
place close to pin38
place close to pin2
BCLK: Audio serial data bus bit clock input/output
LRCK: Audio serial data bus word clock input/output
CA11 close to pin9CA10 close to pin3
Place closely to Pin 14 for DOCK only
Place RA32 close to codec
Digital Mic (Goliad MLK no single Mic)
place at AGND and DGND plane
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.)
HP-Out-Left
Global Headset
HP-Out-Right Nokia-MIC
iPhone-MIC
Verb table configures as 1 JD mode with
internal 47K pull high to save external rBOM.
place close to pin41 place close to pin46
GMLK no single MIC
Place RA9 close to UA1
20130806 CIS Link OK
Normal
Open
Combo Jack
EMI De-pop
CIS Link OK
place close to pin12
Place CA12 & CA13
close to Audio Jack
+VDDA_AVDD1
+1.5V_RUN_AUDIO
+VDDA_PVDD
+VREFOUT
AUD_HP_OUT_LAUD_HP_OUT_R
AUD_NB_MUTE#
AUD_OUT_LAUD_OUT_R
AUD_PC_BEEP
AUD_SENSE_A
AUD_SENSE_A
DMIC_CLK
DMIC_CLK
DMIC_CLK_L
INT_SPKR_L+INT_SPKR_L-INT_SPKR_R+
INT_SPK_L+
INT_SPK_L+
INT_SPK_L-
INT_SPK_L-
INT_SPK_R+
INT_SPK_R+INT_SPK_R-
INT_SPK_R-
AUD_NB_MUTE#
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_BITCLK
PCH_AZ_CODEC_RST#
PCH_AZ_CODEC_SDOUT
PCH_AZ_SDIN0_R
RING2
RING2SLEEVE
SLEEVE
SLEEVE
MIC1_L
MIC1_R
MIC1_L
MIC1_R
+MIC1_VREF_OUT
AUD_HP_OUT_R
AUD_HP_OUT_L
INT_SPKR_R+INT_SPKR_R-
AUD_SENSE_B
AUD_SENSE_B
I2S_BCLK
I2S_DO
I2S_MCLK
+5V_RUN_PVDD
AUD_HP_OUT_R AUD_HP_OUT_R1
AUD_HP_OUT_L1
SLEEVE_R
AUD_HP_OUT_L
AUD_HP_NB_SENSE
RING2 RING2_R
SLEEVE
+3.3V_RUN_AUDIO
+3.3V_RUN_AUDIO
+3.3V_RUN_AUDIO
+VREFOUT
+5V_RUN_AUDIO +1.5V_RUN
+VREFOUT
+RTC_CELL
+5V_RUN
+3.3V_RUN +3.3V_RUN_AUDIO
+5V_RUN_AUDIO
+3.3V_RUN_AUDIO +3.3V_RUN_AUDIO
+3.3V_RUN_AUDIO
+5V_RUN_AUDIO
+3.3V_RUN_AUDIO
+3.3V_RUN_AUDIO
PCH_AZ_CODEC_SDIN0<6>
AUD_NB_MUTE#<35>
PCH_AZ_CODEC_BITCLK<6>
PCH_AZ_CODEC_RST#<6>
PCH_AZ_CODEC_SYNC<6>
PCH_AZ_CODEC_SDOUT<6>
AUD_HP_NB_SENSE <35>
DMIC_CLK <23>
DMIC0 <23>
BEEP <36>
SPKR <12>
DOCK_MIC_DET <35>DOCK_HP_DET<35>
DAI_BCLK#<34>
DAI_LRCK#<34>
DAI_DO#<34>
DAI_12MHZ#<34>
DAI_DI<34>
EN_I2S_NB_CODEC#<35>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Codec _ALC3235
21 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Codec _ALC3235
21 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Codec _ALC3235
21 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RA18 10K_0402_5%RA18 10K_0402_5%1 2
CA29 1U_0603_10V6KCA29 1U_0603_10V6K12
CA
17
0.1
U_0402_25V
6C
A17
0.1
U_0402_25V
6
12
QA
2B
DM
N66D
0LD
W-7
_S
OT
363-6
QA
2B
DM
N66D
0LD
W-7
_S
OT
363-6
34
5
CA
19
@E
MC
@
1000P
_0402_50V
7K
CA
19
@E
MC
@
1000P
_0402_50V
7K
12
LA6 BLM15PX330SN1D_2PEMC@ LA6 BLM15PX330SN1D_2PEMC@ 1 2
DA
5R
B7
51
S4
0T
1G
_S
OD
52
3-2
DA
5R
B7
51
S4
0T
1G
_S
OD
52
3-2
21
RA
17
EM
C@3
3_0402_5%
RA
17
EM
C@3
3_0402_5%
12
DA
7L
03
ES
DL
5V
0C
C3
-2_
SO
T2
3-3
@E
MC
@D
A7
L0
3E
SD
L5
V0
CC
3-2
_S
OT
23
-3@
EM
C@
2 31
CA25 10U_0603_6.3V6MCA25 10U_0603_6.3V6M1 2
RA210
0K
_0
40
2_
5%
RA210
0K
_0
40
2_
5%
12
RA
44
100K
_0402_5%
RA
44
100K
_0402_5%
12
PJP6@
PAD-OPEN1x2m
PJP6@
PAD-OPEN1x2m
1 2
CA43
4.7U_0603_6.3V6K
CA43
4.7U_0603_6.3V6K
1 2
CA
53
4.7
U_
06
03
_6
.3V
6K
CA
53
4.7
U_
06
03
_6
.3V
6K
12
RA32 33_0402_5%RA32 33_0402_5%1 2
RA
27
20
0K
_0
40
2_
5%
RA
27
20
0K
_0
40
2_
5%
12
RA360_0402_5%
@EMC@RA360_0402_5%
@EMC@
1 2
CA
47
0.1
U_0402_25V
6C
A47
0.1
U_0402_25V
6
12
RA
3@0_0603_5%
RA
3@0_0603_5%
12
LA7 BLM15PX330SN1D_2PEMC@ LA7 BLM15PX330SN1D_2PEMC@ 1 2
RA52.2K_0402_5% RA52.2K_0402_5%1 2
DA
6L
03
ES
DL
5V
0C
C3
-2_
SO
T2
3-3
@E
MC
@D
A6
L0
3E
SD
L5
V0
CC
3-2
_S
OT
23
-3@
EM
C@
2 31
CA35 2.2U_0402_6.3V6MCA35 2.2U_0402_6.3V6M12
RA
29
100K
_0402_5%
RA
29
100K
_0402_5%
12
CA33
15P_0402_50V8J
EMC@
CA33
15P_0402_50V8J
EMC@
12
CA
11
0.1
U_0402_25V
6C
A11
0.1
U_0402_25V
6
12
RA
24
4.7
K_
04
02
_5
%R
A2
44
.7K
_0
40
2_
5%
12
RA31EMC@ 22_0402_5%RA31EMC@ 22_0402_5%1 2
RA110K_0402_5%RA110K_0402_5%
12
CA
22
@E
MC
@
1000P
_0402_50V
7K
CA
22
@E
MC
@
1000P
_0402_50V
7K
12
RA
28
10
0K
_0
40
2_
5%
RA
28
10
0K
_0
40
2_
5%
12
CA
18
4.7
U_
06
03
_6
.3V
6K
CA
18
4.7
U_
06
03
_6
.3V
6K
1
2
RA30EMC@ 22_0402_5%RA30EMC@ 22_0402_5%1 2
UA1
ALC3235-CG_MQFN48_6X6
UA1
ALC3235-CG_MQFN48_6X6
I2S I/F Float1
GPIO0/DMIC-CLK2
DVDD_IO3
GPIO1/DMIC-DATA124
SDATA-OUT5
BCLK6
LDO3-CAP7
SDATA-IN8
DVDD9
SYNC10
RESET#11
PCBEEP12
HP/MIC1 JD(JD1)13
I2S_IN/I2S_OUT JD(JD2)14
I2S_MCLK15
I2S_SCLK16
I2S_DOUT17
I2S_LRCK18
MIC1-L(PORT-B-L)19
MIC1-R(PORT-B-R)20
LDO1-CAP21
TV Mode/LINE1-JD (JD3)22
LINE1-VREFO23
I2S_DIN24
VREF25
AVSS126
AVDD127
LINE1-L(PORT-C-L)/RING228
LINE1-R(PORT-C-R)/SLEEVE29
MIC1-VREFO30
MIC-CAP31
HPOUT-R(PORT-A-R)32HPOUT-L(PORT-A-L)33
CPVEE34
CBN35
CBP36
AVSS237
CPVDD38
LDO2-CAP39
AVDD240
PVDD141
SPK-OUT-L+42
SPK-OUT-L-43
SPK-OUT-R-44SPK-OUT-R+45
PVDD246
SPDIF-OUT/DMIC-DATA34/GPIO247
EAPD+PD48
GND49
PJP9@
PAD-OPEN1X2m
PJP9@
PAD-OPEN1X2m
1 2
RA12 1K_0402_5%RA12 1K_0402_5%1 2
RA
39
@0_0805_5%
RA
39
@0_0805_5%
12
CA
52
4.7
U_
06
03
_6
.3V
6K
CA
52
4.7
U_
06
03
_6
.3V
6K
12
CA
12
68
0P
_0
40
2_
50
V7
K@
EM
C@
CA
12
68
0P
_0
40
2_
50
V7
K@
EM
C@
1
2
CA
45
0.1
U_0402_25V
6C
A45
0.1
U_0402_25V
6
12
DA1
L0
3E
SD
L5
V0
CC
3-2
_S
OT
23
-3
EMC@DA1
L0
3E
SD
L5
V0
CC
3-2
_S
OT
23
-3
EMC@
231
LA8 BLM15PX330SN1D_2PEMC@ LA8 BLM15PX330SN1D_2PEMC@ 1 2
QA3BDMN66D0LDW-7_SOT363-6
QA3BDMN66D0LDW-7_SOT363-6
34
5
CA
80.1
U_0402_25V
6C
A8
0.1
U_0402_25V
6
12
CA44
4.7U_0603_6.3V6K
CA44
4.7U_0603_6.3V6K
1 2
CA
24
@E
MC
@
1000P
_0402_50V
7K
CA
24
@E
MC
@
1000P
_0402_50V
7K
12
CA
46
80
P_
04
02
_5
0V
7K
@E
MC
@C
A4
68
0P
_0
40
2_
50
V7
K@
EM
C@1
2
CA
13
68
0P
_0
40
2_
50
V7
K@
EM
C@
CA
13
68
0P
_0
40
2_
50
V7
K@
EM
C@
1
2
RA45 0_0402_5%@ RA45 0_0402_5%@1 2
PJP10@
PAD-OPEN1x1m
PJP10@
PAD-OPEN1x1m
1 2
CA
32
20
P_
04
02
_5
0V
7K
@E
MC
@C
A3
22
0P
_0
40
2_
50
V7
K@
EM
C@1
2
DA2
L0
3E
SD
L5
V0
CC
3-2
_S
OT
23
-3
EMC@DA2
L0
3E
SD
L5
V0
CC
3-2
_S
OT
23
-3
EMC@
231
RA14EMC@ 33_0402_5%RA14EMC@ 33_0402_5%1 2
RA370_0402_5%
@EMC@RA370_0402_5%
@EMC@
1 2
CA
51
4.7
U_
06
03
_6
.3V
6K
CA
51
4.7
U_
06
03
_6
.3V
6K
12
RA
26
100K
_0402_5%
RA
26
100K
_0402_5%
12
CA28 0.1U_0402_25V6CA28 0.1U_0402_25V612
CA
46
10U
_0603_6.3
V6M
CA
46
10U
_0603_6.3
V6M
12
CA
50
0.1
U_0402_25V
6C
A50
0.1
U_0402_25V
6
12
RA
25
4.7
K_
04
02
_5
%R
A2
54
.7K
_0
40
2_
5%
12
RA350_0402_5%
@EMC@RA350_0402_5%
@EMC@
1 2
LA11 BLM15PX330SN1D_2PEMC@ LA11 BLM15PX330SN1D_2PEMC@ 1 2
LA2BLM15BD601SN1D_2P
EMC@ LA2BLM15BD601SN1D_2P
EMC@ 1 2
CA
16
4.7
U_
06
03
_6
.3V
6K
CA
16
4.7
U_
06
03
_6
.3V
6K
1
2
LA9 BLM15PX330SN1D_2PEMC@ LA9 BLM15PX330SN1D_2PEMC@ 1 2
RA
21
100K
_0402_5%
RA
21
100K
_0402_5%
12
RA7 24.9_0402_1%RA7 24.9_0402_1%1 2
CA
41
0.1
U_0402_25V
6
@CA
41
0.1
U_0402_25V
6
@
12
RA38 100K_0402_5%RA38 100K_0402_5%1 2
CA
48
10U
_0603_6.3
V6M
CA
48
10U
_0603_6.3
V6M
12
LA10 BLM15PX330SN1D_2PEMC@ LA10 BLM15PX330SN1D_2PEMC@ 1 2
RA13 1K_0402_5%RA13 1K_0402_5%1 2
JSPK1
ACES_50279-0040N-001
CONN@
JSPK1
ACES_50279-0040N-001
CONN@
11
22
33
GND5
GND6
44
RA8 24.9_0402_1%RA8 24.9_0402_1%1 2
DA
4R
B7
51
S4
0T
1G
_S
OD
52
3-2
DA
4R
B7
51
S4
0T
1G
_S
OD
52
3-2
21
DA3
L0
3E
SD
L5
V0
CC
3-2
_S
OT
23
-3
EMC@DA3
L0
3E
SD
L5
V0
CC
3-2
_S
OT
23
-3
EMC@
231
CA
10
4.7
U_
06
03
_6
.3V
6K
CA
10
4.7
U_
06
03
_6
.3V
6K
12
LA3BLM15BD601SN1D_2P
EMC@ LA3BLM15BD601SN1D_2P
EMC@ 1 2
CA
16
80
P_
04
02
_5
0V
7K
@E
MC
@C
A1
68
0P
_0
40
2_
50
V7
K@
EM
C@1
2C
A31
1U
_0603_10V
6K
CA
31
1U
_0603_10V
6K
12
CA
26
@
1U
_0603_10V
4Z
CA
26
@
1U
_0603_10V
4Z
12
CA
910U
_0603_6.3
V6M
CA
910U
_0603_6.3
V6M
12
CA
30
EM
C@2
2P
_0402_50V
8J
CA
30
EM
C@2
2P
_0402_50V
8J
12
CA27 0.1U_0402_25V6CA27 0.1U_0402_25V612
RA
4@0_0603_5%
RA
4@0_0603_5%
12
QA
2A
DM
N66D
0LD
W-7
_S
OT
363-6
QA
2A
DM
N66D
0LD
W-7
_S
OT
363-6
1
2
6
LA5
BLM15PX600SN1D_2P
LA5
BLM15PX600SN1D_2P
1 2
CA
23
@E
MC
@
1000P
_0402_50V
7K
CA
23
@E
MC
@
1000P
_0402_50V
7K
12
RA62.2K_0402_5% RA62.2K_0402_5%1 2
JHP1
SINGA_2SJ3080-003111FCONN@
JHP1
SINGA_2SJ3080-003111FCONN@
1
3
42
5
6
7
RA9 33_0402_5%RA9 33_0402_5%1 2
CA49 1U_0603_10V6KCA49 1U_0603_10V6K12
QA3ADMN66D0LDW-7_SOT363-6
QA3ADMN66D0LDW-7_SOT363-6 1
2
6
G
D
S
QA
1L2N
7002W
T1G
_S
C-7
0-3
G
D
S
QA
1L2N
7002W
T1G
_S
C-7
0-3
2
13
CA
22
20
P_
04
02
_5
0V
7K
@E
MC
@C
A2
22
0P
_0
40
2_
50
V7
K@
EM
C@1
2
2
2
1
1
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
EEPROM
Goliad MLK should be use DOCKED to control TPS22966
Huston 14"/15" use jumper
0319 Change H3, E10, H11 net type
VMM_SPI_CS#
VMM_SPI_HOLD
VMM_GPIO9
BLUE_DOCK
GREEN_DOCK
RED_DOCK
SW_DPB_AUX
SW_DPC_AUX
VMM_SPI_CLK
VMM_SPI_CS#VMM_SPI_DIN
VMM_SPI_DO
VMM_SPI_HOLDVMM_SPI_WP#
+3.3V_RUN_VDDIOLP_CTL
+1.05V_VMM_VDD
+1.05V_VMM_VDDTX
CLK_27M_IN
CLK_27M_OUT
VMM2320_AUX#_CVMM2320_AUX_C
VMM2320_N0_C
VMM2320_N1_C
VMM2320_N2_C
VMM2320_N3_C
VMM2320_P0_C
VMM2320_P1_C
VMM2320_P2_C
VMM2320_P3_C
SW_DPC_AUX#
VMM_DPC_CTRLCLKVMM_DPC_CTRLDAT
I2C1_SCL_VMMI2C1_SDA_VMM
LP_CTL
SRCDET
SRCDET
SW_DPB_AUX
SW_DPB_AUX#
SW_DPB_AUX#
SW_DPC_AUXSW_DPC_AUX#
VMM2320_VGA_IREF
VMM2320_VGA_IREF
VMM2320_VGA_NC
VMM2320_VGA_DET
VMM2320_VGA_DET
VMM_DPB_CTRLCLK
VMM_DPB_CTRLCLK
VMM_DPB_CTRLDAT
VMM_DPB_CTRLDAT
VMM_DPC_CTRLCLKVMM_DPC_CTRLDAT
VMM_GPIO6
VMM_GPIO6
VMM_GPIO7
VMM_GPIO7
VMM_GPIO8VMM_GPIO9
VMM_SPI_CLKVMM_SPI_CS#
VMM_SPI_DINVMM_SPI_DO
VMM_SPI_WP#
+1.05V_VMM_UV10
+3.3V_VMM_UV10
DOCKED
DOCKED
VMM_GPIO8
VMM_SPI_WP#
VMM_GPIO5
VMM_GPIO4
VMM_GPIO4VMM_GPIO5
LP_CTL
I2C1_SCL_VMMI2C1_SDA_VMM
+1.05V_RUN +1.05V_RUN_VMM
+3.3V_RUN +3.3V_RUN_VMM
+3.3V_RUN_VDDA
+3.3V_RUN_VMM
+3.3V_RUN_VMM
+3.3V_RUN_VDDA +3.3V_RUN_VMM+1.05V_RUN_VMM
+3.3V_RUN_VMM
+1.05V_RUN_VMM
+3.3V_RUN_VMM
+1.05V_RUN_VMM
+5V_ALW
+1.05V_RUN
+3.3V_RUN
+3.3V_RUN_VDDIO
+3.3V_RUN_VMM
VMM2320_P3<26>
VMM2320_N0<26>VMM2320_P0<26>
VMM2320_N1<26>VMM2320_P1<26>
VMM2320_N2<26>VMM2320_P2<26>
VMM2320_N3<26>
VMM2320_AUX#<26>VMM2320_AUX<26>
VMM2320_HPD<26>
PLTRST_VMM2320#<9>
VMM_DPC_CTRLDAT <26>
SW_DPC_AUX# <26>SW_DPC_AUX <26>
VMM_DPC_CTRLCLK <26>
DPC_DOCK_HPD <34>
DPC_LANE_P0 <34>
DPC_LANE_P1 <34>DPC_LANE_N1 <34>DPC_LANE_P2 <34>DPC_LANE_N2 <34>DPC_LANE_P3 <34>DPC_LANE_N3 <34>
DPC_LANE_N0 <34>
DPC_CA_DET <26,34>
VMM_DPB_CTRLDAT <26>
DPB_LANE_N3 <34>DPB_LANE_P3 <34>DPB_LANE_N2 <34>DPB_LANE_P2 <34>
DPB_LANE_N0 <34>DPB_LANE_P1 <34>
DPB_LANE_P0 <34>
SW_DPB_AUX <26>SW_DPB_AUX# <26>
DPB_LANE_N1 <34>
DPB_CA_DET <26,34>
VMM_DPB_CTRLCLK <26>
DPB_DOCK_HPD <34>
RED_DOCK <34>
GREEN_DOCK <34>
BLUE_DOCK <34>
CLK_DDC2_DOCK <34>DAT_DDC2_DOCK <34>
HSYNC_DOCK <34>VSYNC_DOCK <34>
DOCKED<28,31,35>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DP 1.2 MST HUB
22 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DP 1.2 MST HUB
22 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
DP 1.2 MST HUB
22 48Wednesday, March 19, 2014
Compal Electronics, Inc.
UV13
TPS22966DPUR_SON14_2X3
UV13
TPS22966DPUR_SON14_2X3
VIN11
VIN12
ON13
VBIAS4
ON25
VIN26
VIN27
VOUT28VOUT29
CT210
GND11
CT112
VOUT113VOUT114
GPAD15
CV
11
31
8P
_0
40
2_
50
V8
JC
V1
13
18
P_
04
02
_5
0V
8J
12
CV
93
0.0
1U
_0402_16V
7K
CV
93
0.0
1U
_0402_16V
7K
12
CV116 470P_0402_50V7KCV116 470P_0402_50V7K1 2
LV23
BLM15PX181SN1D_2P
LV23
BLM15PX181SN1D_2P1 2
CV117 470P_0402_50V7KCV117 470P_0402_50V7K1 2
CV114
0.1U_0402_25V6
CV114
0.1U_0402_25V6
1 2RPV2
2.2K_0804_8P4R_5%
RPV2
2.2K_0804_8P4R_5%
1234 5
678
RV851M_0402_5% RV851M_0402_5%1 2
RV78150_0402_1% RV78150_0402_1%12
CV
94
10U
_0603_6.3
V6M
CV
94
10U
_0603_6.3
V6M
12
RV731M_0402_5% @ RV731M_0402_5% @12
CV
87
1U
_0603_10V
6K
CV
87
1U
_0603_10V
6K
12
CV1030.1U_0402_10V7K CV1030.1U_0402_10V7K 1 2
RV79@100K_0402_5% RV79@100K_0402_5%12
CV
86
0.0
1U
_0402_16V
7K
CV
86
0.0
1U
_0402_16V
7K
12
RV14 2.2K_0402_5%RV14 2.2K_0402_5%1 2
CV
95
0.1
U_0402_25V
6C
V95
0.1
U_0402_25V
6
12
CV
88
0.1
U_0402_25V
6C
V88
0.1
U_0402_25V
6
12
PJP25@
PAD-OPEN1x1m
PJP25@
PAD-OPEN1x1m
1 2
PJP24@
PAD-OPEN1x1m
PJP24@
PAD-OPEN1x1m
1 2
CV1060.1U_0402_10V7K CV1060.1U_0402_10V7K 1 2
RV517 @2.2K_0402_5% RV517 @2.2K_0402_5%12
CV
92
0.0
1U
_0402_16V
7K
CV
92
0.0
1U
_0402_16V
7K
12
CV
98
0.0
1U
_0402_16V
7K
CV
98
0.0
1U
_0402_16V
7K
12
RV751M_0402_5% RV751M_0402_5%12
CV
83
0.1
U_0402_25V
6C
V83
0.1
U_0402_25V
6
12
CV518 0.1U_0402_10V7KCV518 0.1U_0402_10V7K1 2
CV1100.1U_0402_10V7K CV1100.1U_0402_10V7K 1 2
PJP27@
PAD-OPEN1x1m
PJP27@
PAD-OPEN1x1m
1 2
RV5162.2K_0402_5% @ RV5162.2K_0402_5% @12
RV741M_0402_5% RV741M_0402_5%12
PJP28
@
PAD-OPEN1x1m
PJP28
@
PAD-OPEN1x1m
12
CV
118
0.1
U_0402_10V
7K
CV
118
0.1
U_0402_10V
7K
12
RV518 @2.2K_0402_5% RV518 @2.2K_0402_5%12
CV
85
0.0
1U
_0402_16V
7K
CV
85
0.0
1U
_0402_16V
7K
12
UV9
W25X10CVSNIG_SO8
UV9
W25X10CVSNIG_SO8
CS#1
DO(IO1)2
WP#(IO2)3
GND4
DI(IO0)5CLK6HOLD#(IO3)7VCC8
CV
90
10U
_0603_6.3
V6M
CV
90
10U
_0603_6.3
V6M
12
CV
97
0.0
1U
_0402_16V
7K
CV
97
0.0
1U
_0402_16V
7K
12
CV
100
0.1
U_0402_25V
6C
V100
0.1
U_0402_25V
6
12
CV
96
0.0
1U
_0402_16V
7K
CV
96
0.0
1U
_0402_16V
7K
12
CV
99
0.0
1U
_0402_16V
7K
CV
99
0.0
1U
_0402_16V
7K
12
RV8610K_0402_5% RV8610K_0402_5%12
CV1090.1U_0402_10V7K CV1090.1U_0402_10V7K 1 2
RV519 @2.2K_0402_5% RV519 @2.2K_0402_5%12
RV841M_0402_5% RV841M_0402_5%1 2
UV8A
VMM3320BJGR_BGA168
UV8A
VMM3320BJGR_BGA168
RxN3D2 RxP3D1 RxN2E2 RxP2E1
RxP1F1
RxN1F2
RxN0G2 RxP0G1
RxAUXPH1
RXAUXNH2
RxSRCDETC2
RxHPDJ1
Tx0N1A8
Tx0N3A10
Tx0N2A9
CAD0A14
Tx0N0A7
Tx0AUXNA11
Tx0P2B9
Tx0P3B10
Tx0DDCSDAA12
Tx0HPDA6
Tx0DDCSCLB12
Tx0AUXPB11
Tx0P0B7
Tx0P1B8
Tx1HPDK14Tx1DDCSDAL14Tx1DDCSCLK13Tx1AUXNJ14Tx1AUXPJ13CAD1M14Tx1N3H14Tx1P3H13Tx1N2G14Tx1P2G13Tx1N1F14Tx1P1F13Tx1N0E14Tx1P0E13
VGA_GPM7
VGA_RPM6
VGA_IREFM5
VGA_SDAM4
VGA_DETM3
RSTN_INA13
XINK1
XOUTL1
SSCLA2SSDAA1
VGA_SCLL4
NCL5
VGA_RNL6
RxDDCSDAM10
NCL12
NCL13
RxDDCSCLL10
VDDIOB5
NCB1
SPICLKB3
SPIDOA3
GPIO1D13
GPIO3C13
GPIO5B13
GPIO6C1
GPIO7M12
NCM13
VGA_BNL8
VGA_VSYNCL9
VGA_HSYNCM9
VGA_BPM8VGA_GNL7
NCM11
VDDIOB6
NCL11
SPICSA4
SPIDIB4
GPIO0D14
GPIO2C14
GPIO4B14
LP_CTLB2 NCL3
RX_STSK2
TX0_STSL2
TX1_STSM1
TX2_STSM2
LP_ENA5
RV81 2.2K_0402_5%RV81 2.2K_0402_5%1 2
CV
89
0.0
1U
_0402_16V
7K
CV
89
0.0
1U
_0402_16V
7K
12
CV
101
10U
_0603_6.3
V6M
CV
101
10U
_0603_6.3
V6M
12
RV821M_0402_5% RV821M_0402_5%1 2
YV227MHZ_12PF_X1E000021042600
YV227MHZ_12PF_X1E000021042600
IN1
GND2
OUT3
GND4
CV1110.1U_0402_10V7K CV1110.1U_0402_10V7K 1 2
CV
82
10U
_0603_6.3
V6M
CV
82
10U
_0603_6.3
V6M
12
RPV1
2.2K_0804_8P4R_5%
RPV1
2.2K_0804_8P4R_5%
1234 5
678
CV1040.1U_0402_10V7K CV1040.1U_0402_10V7K 1 2
RV76150_0402_1% RV76150_0402_1%12
1V
Dig
ita
l 1
V A
na
log
3
.3V
IO
3.3V Analog
UV8B
VMM3320BJGR_BGA168
1V
Dig
ita
l 1
V A
na
log
3
.3V
IO
3.3V Analog
UV8B
VMM3320BJGR_BGA168
VDDE6
VDDE7
VDDE8
VDDE9
VDDH7 VDDH6
VDDH8
VDDH9
VDDRXE3
VDDRXG3
VDDTX0C8
VDDTX0C9
VDDLPE5
NCE10
VDDRXA1F3
VDDTX0A1C7
VDDTX1G12
NCH11
NCH3
VDDRXD3
VDDTX1A2D12
VGA_AVDDJ10
VDDTX1A1E12
VDDTX0A2C6
VDDTX1F12
VDDLPJ3
VDDRX_33H5
VDDXT3VJ4 VDDIO
K12 VDDIOK11 VDDIOK4 VDDIOK3 VDDIO
C12 VDDHTX0_33C11 VDDHRX_33C4 VDDHRX_33C3
VDDSAJ2
VGA_AVDDK10 VGA_AVDDK9 VGA_AVDDK8
VSSD5
VSSD7
VSSD9
VSSD11
VSSE4
VSSE11
VSSF4
VSSF5
VSSF6
VSSF7
VSSD10
VSSD8
VSSD6
VSSF9
VSSF10
VSSF11
VSSG5
VSSG6
VSSG8
VSSG10
VSSH4
VSSJ11
VSSK5
VGA_AVSSJ6
VGA_AVSSJ7
VGA_AVSSJ8
VGA_AVSSJ9
VGA_AVDD33K6
VDDTX0_33C10
VDDTX1_33H12
VGA_AVDD33K7
VSSC5
VSSF8
VSSG7
VSSG4
VSSG9
VSSG11
VSSJ5
VSSJ12
VGA_AVSSH10
VSSD4
CV1070.1U_0402_10V7K CV1070.1U_0402_10V7K 1 2CV1080.1U_0402_10V7K CV1080.1U_0402_10V7K 1 2
T108@ PAD~DT108@ PAD~D
CV
115
22P
_0402_50V
8J
CV
115
22P
_0402_50V
8J
12
CV1020.1U_0402_10V7K CV1020.1U_0402_10V7K 1 2
LV22
BLM15PX181SN1D_2P
LV22
BLM15PX181SN1D_2P1 2
LV25
BLM15PX181SN1D_2P
LV25
BLM15PX181SN1D_2P1 2
CV
91
0.1
U_0402_25V
6C
V91
0.1
U_0402_25V
6
12
RV8810K_0402_5% RV8810K_0402_5%12
RV893.74K_0402_1% RV893.74K_0402_1%1 2
LV24
BLM15PX181SN1D_2P
LV24
BLM15PX181SN1D_2P1 2
RV77150_0402_1% RV77150_0402_1%12
RV872.2K_0402_5% RV872.2K_0402_5%12
RV832.2K_0402_5% RV832.2K_0402_5%1 2
CV1050.1U_0402_10V7K CV1050.1U_0402_10V7K 1 2
CV
84
0.1
U_0402_25V
6C
V84
0.1
U_0402_25V
6
12
RV
80
1M
_0402_5%
RV
80
1M
_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Close to JEDP1.11,12
change back to CCD_OFF at Goliad project
Close to JEDP1.33 Close to JEDP1.40 Close to JEDP1.1
LCDVDD POWERBacklight POWERWebCAM
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Close to JEDP1.24~27
2nd source SA00003AR00
For Touchscreen
ESD depop location
LED CONN
20130822
pin 15: LOOP_BACK
BIA_PWMBIA_PWM_EC
DISP_ON
EDP_BIA_PWM
EN_LCDPWR
PWR_SRC_ON
BIA_PWMDISP_ON
EDP_CPU_AUX#_CEDP_CPU_AUX_C
EDP_CPU_LANE_N0_C
EDP_CPU_LANE_N1_C
EDP_CPU_LANE_P0_C
EDP_CPU_LANE_P1_C
USBP5_D+USBP5_D-
USBP5_D+
USBP5_D-
USBP4_D+USBP4_D-
+PWR_SRC
+LCDVDD
+3.3V_CAM +3.3V_RUN
+3.3V_CAM +3.3V_TSP
+BL_PWR_SRC+3.3V_ALW
+LCDVDD
+3.3V_RUN+BL_PWR_SRC +3.3V_RUN+3.3V_RUN +3.3V_TSP
+3.3V_TSP
+5V_ALW
+LCDVDD
+BL_PWR_SRC
+3.3V_CAM+3.3V_RUN
EN_INVPWR<36>USBP5-<11>
USBP5+<11>
3.3V_CAM_EN#<12>
LCD_VCC_TEST_EN<35>
ENVDD_PCH<10,36>
PANEL_BKLEN <10>
PANEL_BKEN_EC <35>
EDP_BIA_PWM <10>
BIA_PWM_EC <36>
3.3V_TS_EN<12>
USBP4- <11>
USBP4+ <11>
BREATH_WHITE_LED#<39>
BATT_YELLOW_LED#<39>BATT_WHITE_LED#<39>
PANEL_HDD_LED#<39>
EDP_CPU_LANE_P0 <10>
EDP_CPU_LANE_P1 <10>
EDP_CPU_AUX# <10>
EDP_CPU_LANE_N1 <10>
EDP_CPU_LANE_N0 <10>
EDP_CPU_AUX <10>
LCD_TST <35>
EDP_CPU_HPD <10>
DMIC_CLK <21>
DMIC0 <21>
CAM_MIC_CBL_DET# <12>
LCD_CBL_DET# <12>
TOUCH_PANEL_INTR# <12>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
eDP CONN & Touch screen
23 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
eDP CONN & Touch screen
23 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
eDP CONN & Touch screen
23 48Wednesday, March 19, 2014
Compal Electronics, Inc.
DV4
AZC199-02SPR7G_SOT23-3@EMC@DV4
AZC199-02SPR7G_SOT23-3@EMC@
22
33
11
LV27
DLW21HN900HQ2L_4P
EMC@LV27
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
CV
12
0.1
U_
06
03
_5
0V
7K
CV
12
0.1
U_
06
03
_5
0V
7K
12
UV24
AP2821KTR-G1_SOT23-5
UV24
AP2821KTR-G1_SOT23-5
VIN5
VIN4
VOUT1
EN3
GND2
RV
41
00
K_
04
02
_5
%R
V4
10
0K
_0
40
2_
5%
12
CA
5@
EM
C@
10
0P
_0
40
2_
50
V8
JC
A5
@E
MC
@1
00
P_
04
02
_5
0V
8J
12
CV4 0.1U_0402_10V7KCV4 0.1U_0402_10V7K12
CV2 0.1U_0402_10V7KCV2 0.1U_0402_10V7K12
CZ
1
@
0.1
U_
04
02
_2
5V
6C
Z1
@
0.1
U_
04
02
_2
5V
6
12
CV
10
0.0
1U
_0
40
2_
16
V7
K
@CV
10
0.0
1U
_0
40
2_
16
V7
K
@12
DV3
BAT54CW_SOT323-3
DV3
BAT54CW_SOT323-3
12
3
CV1 0.1U_0402_10V7KCV1 0.1U_0402_10V7K12
RV
24
.7K
_0
40
2_
5%
RV
24
.7K
_0
40
2_
5%
12
CA
6@
EM
C@
10
0P
_0
40
2_
50
V8
JC
A6
@E
MC
@1
00
P_
04
02
_5
0V
8J
12
CV
70
.1U
_0
60
3_
50
V7
K
@CV
70
.1U
_0
60
3_
50
V7
K
@
12
S
G
D
QV1
AO6405_TSOP6
S
G
D
QV1
AO6405_TSOP63
6
24 5
1
G
D S
LP2301ALT1G_SOT23-3QV8
G
D S
LP2301ALT1G_SOT23-3QV8
1
2
3
CV3 0.1U_0402_10V7KCV3 0.1U_0402_10V7K12
LZ1
DLW21HN900HQ2L_4P
EMC@LZ1
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
RV
31
00
K_
04
02
_5
%R
V3
10
0K
_0
40
2_
5%1
2
G
D S
LP2301ALT1G_SOT23-3QZ1
G
D S
LP2301ALT1G_SOT23-3QZ1
1
2
3
G
D S
QV2L2N7002WT1G_SC-70-3
G
D S
QV2L2N7002WT1G_SC-70-3
1
2
3RV5 47K_0402_5%RV5 47K_0402_5%
1 2
JEDP1CONN@
ACES_50398-04041-001
JEDP1CONN@
ACES_50398-04041-001
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
G141
G242
G343
G444
G545
CA
7
@
0.1
U_
04
02
_2
5V
6C
A7
@
0.1
U_
04
02
_2
5V
6
12
CV
11
10
00
P_
04
02
_5
0V
7K
CV
11
10
00
P_
04
02
_5
0V
7K
12
CV9@
10U_0603_6.3V6M
CV9@
10U_0603_6.3V6M
12
LV1BLM15BB221SN1D_2P~D
EMC@ LV1BLM15BB221SN1D_2P~D
EMC@ 1 2
CV5 0.1U_0402_10V7KCV5 0.1U_0402_10V7K12
JLED1 CONN@
ACES_50277-0060N-001
JLED1 CONN@
ACES_50277-0060N-001
44
11
66
22 33
55
GND17GND28
CV6 0.1U_0402_10V7KCV6 0.1U_0402_10V7K12
DV2
BAT54CW_SOT323-3
DV2
BAT54CW_SOT323-3
12
3
RV
610K
_0402_5%
RV
610K
_0402_5%
12
DV1
BAT54CW_SOT323-3
DV1
BAT54CW_SOT323-3
12
3 G
D
S
QV
7L
2N
70
02
WT
1G
_S
C-7
0-3
G
D
S
QV
7L
2N
70
02
WT
1G
_S
C-7
0-3
2
13
CV
8
@
0.1
U_
04
02
_2
5V
6C
V8
@
0.1
U_
04
02
_2
5V
6
12
RV
14
.7K
_0
40
2_
5%
RV
14
.7K
_0
40
2_
5%
12
CZ
2
@
0.1
U_
04
02
_1
6V
4Z
CZ
2
@
0.1
U_
04
02
_1
6V
4Z
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
mDP connector
AUX/DDC SW for DDI2 to Mini DP
mDP_CA_DET
1
function
mDP
HDMI0
HDMI connector
20130730 DC232002PB0 CIS Link OK
20130730 DC060008GB0 CIS Link OK
mDP_AUX#_C
mDP_HPD
mDP_LANE_N1_C
mDP_LANE_P2_C
mDP_LANE_N2_C
mDP_LANE_P3_C
mDP_LANE_N3_C
mDP_CA_DET
DPB_MB_P14
mDP_LANE_P0_C
mDP_LANE_N0_C
mDP_LANE_P1_C
mDP_HPD
mDP_CA_DET
DPB_MB_P14
mDP_AUX_C
mDP_AUX#_C
mDP_AUX_C
mDP_HPD
mDP_LANE_N2_C
mDP_LANE_P2_C
mDP_LANE_N3_C
mDP_LANE_P3_C
mDP_LANE_N1_C
mDP_LANE_P1_C
mDP_LANE_N0_C
mDP_LANE_P0_C
mDP_AUX_C
mDP_AUX#_C
SW_mDP_AUX_C
SW_mDP_AUX#_C
mDP_CA_DET#
mDP_CA_DET
TMDS_CON_CLK
TMDS_CON_CLK#
TMDS_CON_N1
TMDS_CON_P1
HDMI_CLK_AUXHDMI_DAT_AUX#
HDMI_CEC
TMDS_CON_CLK
TMDS_CON_CLK#
TMDS_CON_N0
TMDS_CON_N1
TMDS_CON_N2
TMDS_CON_P0
TMDS_CON_P1
TMDS_CON_P2
HDMI_CLK_AUX
HDMI_DAT_AUX#
TMDS_CON_N0
TMDS_CON_P0
TMDS_CON_N2
TMDS_CON_P2
+VDISPLAY_VCC
+3.3V_RUN
+3.3V_RUN
+5V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+5V_RUN
+VHDMI_VCC
+VHDMI_VCC
DPC_HPD<10>
DDI2_LANE_P3<10>
DDI2_LANE_N3<10>
DDI2_LANE_P1<10>
DDI2_LANE_N1<10>
DDI2_LANE_P2<10>
DDI2_LANE_N2<10>
DDI2_LANE_P0<10>
DDI2_LANE_N0<10>
CPU_DPC_CTRLDAT <10>
CPU_DPC_CTRLCLK <10>
CPU_DPC_AUX#<10>
CPU_DPC_AUX<10>
HDMI_LANE_P3<25>
HDMI_LANE_N3<25>
HDMI_LANE_P1<25>
HDMI_LANE_N1<25>
HDMI_LANE_P2<25>
HDMI_LANE_N2<25>
HDMI_LANE_P0<25>
HDMI_LANE_N0<25>
HDMI_HPD<25>
HDMI_CLK_AUX<25>
HDMI_DAT_AUX#<25>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
HDMI CONN
24 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
HDMI CONN
24 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
HDMI CONN
24 48Wednesday, March 19, 2014
Compal Electronics, Inc.
LV10
DLW21HN900HQ2L_4P
EMC@LV10
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
CV
510
0.1
U_0402_16V
4Z
@CV
510
0.1
U_0402_16V
4Z
@ 1
2
CV
509
.01U
_0402_16V
7K
CV
509
.01U
_0402_16V
7K
1
2
G
DS
QV501L2N7002WT1G_SC-70-3
G
DS
QV501L2N7002WT1G_SC-70-3
1
2
3
G
D
S
QV502L2N7002WT1G_SC-70-3G
D
S
QV502L2N7002WT1G_SC-70-3
2
13
RV503 5.1M_0402_5%RV503 5.1M_0402_5%1 2
CV
30
@0
.1U
_0
40
2_
10
V7
KC
V3
0@
0.1
U_
04
02
_1
0V
7K
12
CV506 0.1U_0402_10V7KCV506 0.1U_0402_10V7K12
LV6
DLW21HN900HQ2L_4P
EMC@LV6
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
RV7 2.2K_0402_5%RV7 2.2K_0402_5%1 2
CV508 0.1U_0402_10V7KCV508 0.1U_0402_10V7K12
RV505 100K_0402_5%RV505 100K_0402_5%1 2
RV9 2.2K_0402_5%RV9 2.2K_0402_5%1 2
CV501 0.1U_0402_10V7KCV501 0.1U_0402_10V7K12
CV513
0.1U_0402_10V7K
CV513
0.1U_0402_10V7K12
CV503 0.1U_0402_10V7KCV503 0.1U_0402_10V7K12
LV3
DLW21HN900HQ2L_4P
EMC@LV3
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
CV
24
@
0.1
U_
04
02
_1
6V
4Z
CV
24
@
0.1
U_
04
02
_1
6V
4Z
12
CV5110.1U_0402_25V6CV5110.1U_0402_25V6
1 2
RV8@10K_0402_5% RV8@10K_0402_5%12
JHDMI1
LCN_AUF05-1922S10-0019
CONN@JHDMI1
LCN_AUF05-1922S10-0019
CONN@
D2+1 D2_shield2 D2-3 D1+4 D1_shield5 D1-6 D0+7 D0_shield8 D0-9 CK+
10 CK_shield11 CK-12 CEC13 Reserved14 SCL15 SDA16 DDC/CEC_GND17 +5V18 HP_DET19
GND20
GND21
GND22
GND23
RV504 1M_0402_5%RV504 1M_0402_5%12
RV502 100K_0402_5%RV502 100K_0402_5%1 2
JmDP1 CONN@
ACON_MAR2E-20K1800
JmDP1 CONN@
ACON_MAR2E-20K1800
GND19
AUX_CH_N18
LANE2_N17
AUX_CH_P16
LANE2_P15
GND14
GND13
LANE3_N12
LANE1_N11
LANE3_P10
LANE1_P9
GND8
GND7
CONFIG26
LANE0_N5
CONFIG14
LANE0_P3
HOT-PLUG2
GND1
DP_PWR20
GND424
GND323
GND222
GND121
UV501
AP2337SA-7_SOT23-3
UV501
AP2337SA-7_SOT23-3
IN1
GN
D2
OU
T3
RV
507
100K
_0402_5%
RV
507
100K
_0402_5%
12
CV507 0.1U_0402_10V7KCV507 0.1U_0402_10V7K12
UV
10
AP
23
30
W-7
_S
C5
9-3
UV
10
AP
23
30
W-7
_S
C5
9-3
IN1
GN
D2
OU
T3
CV504 0.1U_0402_10V7KCV504 0.1U_0402_10V7K12
RV501 100K_0402_5%RV501 100K_0402_5%1 2
UV502
PI3C3125LEX_TSSOP14~D
UV502
PI3C3125LEX_TSSOP14~D
B311
B16
BE14
A15
A29
GND7
A312
VCC14
B28
BE313
A02
B03
BE01
BE210
CV
27
10
U_
06
03
_6
.3V
6M
CV
27
10
U_
06
03
_6
.3V
6M
12
CV505 0.1U_0402_10V7KCV505 0.1U_0402_10V7K12
CV502 0.1U_0402_10V7KCV502 0.1U_0402_10V7K12
CV512
0.1U_0402_10V7K
CV512
0.1U_0402_10V7K
12
LV12
DLW21HN900HQ2L_4P
EMC@LV12
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
PCB
G14U_En
G14D_En
G14 UMA
G14 DSC
G12 UMA PS8339+PS8338
DP SWITCH
G12 Entry PS8339
MODE = L: Control Switching Mode, HDMI ID disable
= H: Automatic Switching Mode, HDMI ID disable
= M: Automatic Switching Mode, HDMI ID enable
TMDS_RT = L: Standard open drain driver
= H: Open drain driver with termination resistors
TMDS_DDCBUF = L: DDC pass through
= H: DDC active buffer
= M: DDC pass through with 40 kohm pull up resistor
DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
= M: auto test disable & input offset cancellation disable
PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
= H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2
TMDS_PRE = L: no pre-emphasis
= H: 1.5dB pre-emphasis
= M: 3.0dB pre-emphasis
DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
= H: automatic EQ disable & AUX interception enable
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
PS8339+PS8338
PS8339
PS8339+PS8338
PS8339
PS8339B_DP_CFG1
PS8339B_TMDS_RT
PS8339B_TMDS_PRE
PS8339B_MODE
PS8339B_INPUT_EQ
PS8339B_TMDS_DDCBUF
DDI1_LANE_P0_CDDI1_LANE_N0_C
DDI1_LANE_P1_CDDI1_LANE_N1_C
DDI1_LANE_P2_CDDI1_LANE_N2_C
DDI1_LANE_P3_CDDI1_LANE_N3_C
CPU_DPB_AUX_CCPU_DPB_AUX#_C
PS8339B_MODE
CPU_DPB_CTRLCLKCPU_DPB_CTRLDAT
PS8339B_TMDS_RTPS8339B_TMDS_PRE
PS8339B_DP_CFG1
PS8339B_OUT_CA_DET
PS8339B_TMDS_DDCBUF
PS8339B_INPUT_EQ
PS8339B_IN_CA_DET
PS8339B_DP_CFG0PS8339B_MODE_SW
PS8339B_IN_CA_DET
PS8339B_DP_CFG0
PS8339B_MODE_SW
PS8339B_OUT_CA_DET
PS8338_AUX#
PS8338_AUX
+3.3V_RUN
+3.3V_RUN
+3.3V_RUNDDI1_LANE_P3<10>
DDI1_LANE_N0<10>DDI1_LANE_P0<10>
DDI1_LANE_N1<10>DDI1_LANE_P1<10>
DDI1_LANE_N2<10>DDI1_LANE_P2<10>
DDI1_LANE_N3<10>
DPB_HPD<10>
CPU_DPB_AUX#<10>CPU_DPB_AUX<10> HDMI_LANE_P0 <24>
HDMI_LANE_N0 <24>
HDMI_LANE_P1 <24>HDMI_LANE_N1 <24>
HDMI_LANE_P2 <24>HDMI_LANE_N2 <24>
HDMI_LANE_P3 <24>HDMI_LANE_N3 <24>
PS8338_P2 <26>
PS8338_P3 <26>PS8338_N3 <26>
PS8338_N2 <26>
PS8338_P0 <26>
PS8338_P1 <26>PS8338_N1 <26>
PS8338_N0 <26>
HDMI_CLK_AUX <24>HDMI_DAT_AUX# <24>
PS8338_AUX <26>PS8338_AUX# <26>
HDMI_HPD <24>
PS8338_HPD <26>
CPU_DPB_CTRLDAT<10>CPU_DPB_CTRLCLK<10>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
DP SW
25 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
DP SW
25 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
DP SW
25 48Wednesday, March 19, 2014
Compal Electronics, Inc.
CV
66
0.1
U_
04
02
_2
5V
6C
V6
60
.1U
_0
40
2_
25
V6
12
CV
62
0.0
1U
_0402_16V
7K
CV
62
0.0
1U
_0402_16V
7K
1
2
RV555 100K_0402_5%@ RV555 100K_0402_5%@1 2
RV
52
4.7
K_
04
02
_5
%
@R
V5
24
.7K
_0
40
2_
5%
@
12
CV
60
2.2
U_
04
02
_6
.3V
6M
CV
60
2.2
U_
04
02
_6
.3V
6M
12
RV
63
4.7
K_
04
02
_5
%R
V6
34
.7K
_0
40
2_
5% 1
2
RV
51
4.7
K_
04
02
_5
%
@R
V5
14
.7K
_0
40
2_
5%
@
12
RV554 100K_0402_5%@ RV554 100K_0402_5%@1 2
CV75 0.1U_0402_25V6CV75 0.1U_0402_25V61 2
CV77 0.1U_0402_25V6CV77 0.1U_0402_25V61 2
RV
55
04
.7K
_0
40
2_
5%
@R
V5
50
4.7
K_
04
02
_5
%
@
12
RV
61
4.7
K_
04
02
_5
%
@R
V6
14
.7K
_0
40
2_
5%
@
12
RV
56
4.7
K_
04
02
_5
%@
RV
56
4.7
K_
04
02
_5
%@
12
RV
60
4.7
K_
04
02
_5
%
@R
V6
04
.7K
_0
40
2_
5%
@
12
CV
69
0.1
U_
04
02
_2
5V
6C
V6
90
.1U
_0
40
2_
25
V6
12
RV
66
4.7
K_
04
02
_5
%R
V6
64
.7K
_0
40
2_
5% 1
2
CV79 0.1U_0402_25V6CV79 0.1U_0402_25V61 2
RV
55
4.7
K_
04
02
_5
%R
V5
54
.7K
_0
40
2_
5% 1
2
RV
58
4.7
K_
04
02
_5
%
@R
V5
84
.7K
_0
40
2_
5%
@
12
RV
65
4.7
K_
04
02
_5
%
@R
V6
54
.7K
_0
40
2_
5%
@
12
RV
50
4.9
9K
_0
40
2_
1%
RV
50
4.9
9K
_0
40
2_
1%
12
UV7
PS8339BQFN56GTR2-A0_QFN56_7X7
UV7
PS8339BQFN56GTR2-A0_QFN56_7X7
SW/SDA_CTL45
DP_CFG129
IN_D0p3
IN_D0n4
IN_D1p6
IN_D1n7
VDD3341
IN_D2p9
IN_D2n10
TMDS_HPD17
IN_D3p12
IN_D3n13
VDD3314
MODE53
TMDS_CLKn15
TMDS_SDA47TMDS_SCL48
DP_CA_DET42
PD46
IN_CA_DET11
TMDS_RT23
CEXT1
IN_AUXn51 IN_AUXp52
PEQ8
DP_CFG0/SCL_CTL44
TMDS_CLKp16
VDD3356
DP_AUXp_SCL55
TMDS_DDCBUF2
TMDS_CH0p19
TMDS_CH0n18
TMDS_PRE20
TMDS_CH1p22
TMDS_CH1n21
DP_D0p40
DP_D0n39
VDD3328
DP_D1p37
DP_D1n36
DP_AUXn_SDA54
DP_D2p34
DP_D2n33
GND26
DP_D3p31
DP_D3n30
GND43
IN_DDC_SDA49 IN_DDC_SCL50
REXT27
I2C_CTL_EN38
GND35
TMDS_CH2n24TMDS_CH2p25
IN_HPD5
Thermal/GND57
DP_HPD32
RV
54
4.7
K_
04
02
_5
%
@R
V5
44
.7K
_0
40
2_
5%
@
12
RV
55
14
.7K
_0
40
2_
5%
@R
V5
51
4.7
K_
04
02
_5
%
@
12
CV71 0.1U_0402_25V6CV71 0.1U_0402_25V61 2
CV78 0.1U_0402_25V6CV78 0.1U_0402_25V61 2
RV
64
4.7
K_
04
02
_5
%
@R
V6
44
.7K
_0
40
2_
5%
@
12
RV67 1M_0402_5%RV67 1M_0402_5%1 2
CV80 0.1U_0402_25V6CV80 0.1U_0402_25V61 2
CV76 0.1U_0402_25V6CV76 0.1U_0402_25V61 2
CV
61
0.0
1U
_0402_16V
7K
CV
61
0.0
1U
_0402_16V
7K
1
2
RV
57
4.7
K_
04
02
_5
%R
V5
74
.7K
_0
40
2_
5% 1
2
RV68 100K_0402_5%@ RV68 100K_0402_5%@1 2
CV73 0.1U_0402_25V6CV73 0.1U_0402_25V61 2CV74 0.1U_0402_25V6CV74 0.1U_0402_25V61 2
RV
62
4.7
K_
04
02
_5
%
@R
V6
24
.7K
_0
40
2_
5%
@
12
CV72 0.1U_0402_25V6CV72 0.1U_0402_25V61 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
AUX/DDC SW for DPB to E-DOCK AUX/DDC SW for DPC to E-DOCK
Dock has high priority when both ports plugged
Port switching control or priority configuration. Internal pull down ~150KΩ, 3.3V I/O
For Control Switching Mode (CFG0 = L):
SW = L: Port1 is selected (default)
SW = H: Port2 is selected
For Automatic Switching Mode (CFG0 = H):
SW = L: Port1 has higher priority when both ports are plugged (default)
SW = H: Port2 has higher priority when both ports are plugged
PS8339+PS8338
PS8339
PS8339+PS8338
PS8339
PCB
G14U_En
G14D_En
G14 UMA
G14 DSC
G12 UMA PS8339+PS8338
DP SWITCH
G12 Entry PS8339
DPB_DOCK_AUX
DPB_CA_DET
DPB_CA_DET#
DPB_DOCK_AUX#
SW_DPB_AUX#_C
SW_DPB_AUX_C
DPC_CA_DET
DPC_CA_DET#
DPC_DOCK_AUX
DPC_DOCK_AUX#
SW_DPC_AUX#_C
SW_DPC_AUX_C
DPB_CA_DET
DPC_CA_DET
PS8338B_PEQPS8338_SW
OUT1_CA_DET
OUT2_CA_DET
PS8338B_P1PS8338B_P0
PS8338B_PC21PS8338B_PC20PS8338B_PC11PS8338B_PC10
PS8338_CFG0
VMM2320_AUX#
VMM2320_AUX
WIGIG_AUX
WIGIG_AUX#
OUT1_CA_DET
OUT2_CA_DET
PS8338B_PEQ
PS8338B_PC21
PS8338B_PC20
PS8338B_PC11
PS8338B_PC10
PS8338B_P0
PS8338_SW
PS8338_CFG0
PS8338_P0_CPS8338_N0_C
PS8338_P1_CPS8338_N1_C
PS8338_P2_CPS8338_N2_C
PS8338_P3_CPS8338_N3_C
PS8338B_P1
+3.3V_RUN_VMM
+3.3V_RUN_VMM
+3.3V_RUN_VMM
+3.3V_RUN_VMM
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
SW_DPB_AUX#<22>
SW_DPB_AUX<22>
VMM_DPB_CTRLDAT <22>DPB_DOCK_AUX#<34>
DPB_DOCK_AUX<34>
DPB_CA_DET<22,34>
VMM_DPB_CTRLCLK <22>
SW_DPC_AUX#<22>
SW_DPC_AUX<22>
VMM_DPC_CTRLDAT <22>
VMM_DPC_CTRLCLK <22>
DPC_DOCK_AUX#<34>
DPC_DOCK_AUX<34>
DPC_CA_DET<22,34>
WIGIG_AUX# <30>WIGIG_AUX <30>
WIGIG_HPD <30>
VMM2320_HPD <22>
WIGIG_LANE_P0 <30>
WIGIG_LANE_P1 <30>WIGIG_LANE_N1 <30>
WIGIG_LANE_N0 <30>
WIGIG_LANE_P2 <30>
WIGIG_LANE_P3 <30>WIGIG_LANE_N3 <30>
WIGIG_LANE_N2 <30>
VMM2320_AUX# <22>VMM2320_AUX <22>
PS8338_P3<25>
PS8338_N0<25>PS8338_P0<25>
PS8338_N3<25>
PS8338_N1<25>PS8338_P1<25>
PS8338_N2<25>PS8338_P2<25>
PS8338_AUX#<25>PS8338_AUX<25>
PS8338_HPD<25>VMM2320_P3 <22>VMM2320_N3 <22>
VMM2320_P2 <22>VMM2320_N2 <22>
VMM2320_P0 <22>
VMM2320_P1 <22>VMM2320_N1 <22>
VMM2320_N0 <22>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
DP SW
26 49Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
DP SW
26 49Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
DP SW
26 49Wednesday, March 19, 2014
Compal Electronics, Inc.
RV609 100K_0402_5%RV609 100K_0402_5%1 2
UV12
PI3C3125LEX_TSSOP14~D
UV12
PI3C3125LEX_TSSOP14~D
BE01
A02
B03
BE14
A15
B16
GND7
B28
A29
BE210B311
A312
BE313VCC14
RV
91
10
0K
_0
40
2_
5%
RV
91
10
0K
_0
40
2_
5%
12
UV11
PI3C3125LEX_TSSOP14~D
UV11
PI3C3125LEX_TSSOP14~D
BE01
A02
B03
BE14
A15
B16
GND7
B28
A29
BE210B311
A312
BE313VCC14
CV612 0.1U_0402_25V6CV612 0.1U_0402_25V61 2
RV
61
34
.7K
_0
40
2_
5%
@R
V6
13
4.7
K_
04
02
_5
%@
12
RV
61
44
.7K
_0
40
2_
5%
@R
V6
14
4.7
K_
04
02
_5
%@
12
G
D
S
QV10L2N7002WT1G_SC-70-3G
D
S
QV10L2N7002WT1G_SC-70-3
2
13
RV
62
04
.7K
_0
40
2_
5%
@R
V6
20
4.7
K_
04
02
_5
%@
12
RV605 100K_0402_5%RV605 100K_0402_5%1 2
CV
60
20
.1U
_0
40
2_
25
V6
CV
60
20
.1U
_0
40
2_
25
V6
12
RV607 1M_0402_5%
RV607 1M_0402_5%
1 2
CV119 0.1U_0402_10V7KCV119 0.1U_0402_10V7K12
RV
61
54
.7K
_0
40
2_
5%
@R
V6
15
4.7
K_
04
02
_5
%@
12
CV120 0.1U_0402_10V7KCV120 0.1U_0402_10V7K12
RV608 100K_0402_5%
RV608 100K_0402_5%
1 2
G
D
S
QV9L2N7002WT1G_SC-70-3G
D
S
QV9L2N7002WT1G_SC-70-3
2
13
CV610 0.1U_0402_25V6CV610 0.1U_0402_25V61 2
RV
61
94
.7K
_0
40
2_
5%
@R
V6
19
4.7
K_
04
02
_5
%@
12
CV
60
52
.2U
_0
40
2_
6.3
V6
MC
V6
05
2.2
U_
04
02
_6
.3V
6M
12
CV606 0.1U_0402_25V6CV606 0.1U_0402_25V61 2
CV609 0.1U_0402_25V6CV609 0.1U_0402_25V61 2
CV122 0.1U_0402_10V7KCV122 0.1U_0402_10V7K12
CV
60
00
.1U
_0
40
2_
25
V6
CV
60
00
.1U
_0
40
2_
25
V6
12
CV121
0.1U_0402_25V6
CV121
0.1U_0402_25V6
1 2
CV
60
10
.1U
_0
40
2_
25
V6
CV
60
10
.1U
_0
40
2_
25
V6
12
CV124
0.1U_0402_25V6
CV124
0.1U_0402_25V6
1 2
RV
61
14
.7K
_0
40
2_
5%
@R
V6
11
4.7
K_
04
02
_5
%@
12
RV
60
34
.7K
_0
40
2_
5%
@R
V6
03
4.7
K_
04
02
_5
%@
12
CV607 0.1U_0402_25V6CV607 0.1U_0402_25V61 2RV606 1M_0402_5%
RV606 1M_0402_5%
1 2
RV
60
04
.99
K_
04
02
_1
%R
V6
00
4.9
9K
_0
40
2_
1%
12
UV600
PS8338BQFN60GTR-A0_QFN60_5X9
UV600
PS8338BQFN60GTR-A0_QFN60_5X9
VDD335
IN_D0n7
IN_D2p12
IN_D2n13
IN_D3p15
IN_D3n16
IN_D1p9
IN_D1n10
IN_D0p6
VDD3321
VDD3330
VDD3351
VDD3357
GND19 GND11
PC2153 PC2054 PC1155 PC1056 CFG158 CFG059
OUT1_D0p50
OUT1_D0n49
OUT1_D1p47
OUT1_D1n46
OUT1_D2p45
OUT1_D2n44
OUT1_D3p42
OUT1_D3n41
IN_CA_DET4
IN_HPD3
I2C_CTL_EN2
Pl1/SCL_CTL1
IN_AUXp24
IN_AUXn25
OUT2_D0p40
OUT2_D0n39
OUT2_D1p37
OUT2_D1n36
OUT2_D2p35
OUT2_D2n34
OUT2_D3p32
OUT2_D3n31
OUT1_AUXp_SCL26
OUT1_AUXn_SDA27
OUT2_AUXp_SCL28
OUT2_AUXn_SDA29
OUT1_CA_DET43
OUT1_HPD48
OUT2_CA_DET33
OUT2_HPD38
PEQ8
CEXT17
GND52
IN_DDC_SCL22
IN_DDC_SDA23
Pl0/SDA_CTL60
PAD(GND)61
PD14
REXT20
SW18
CV
603
0.0
1U
_0402_16V
7K
CV
603
0.0
1U
_0402_16V
7K
12
RV601 4.7K_0402_5%
RV601 4.7K_0402_5%
1 2
RV509 1M_0402_5%RV509 1M_0402_5%1 2
RV
10
04
.7K
_0
40
2_
5%
@R
V1
00
4.7
K_
04
02
_5
%@
12
CV
604
0.0
1U
_0402_16V
7K
CV
604
0.0
1U
_0402_16V
7K
12
RV
61
84
.7K
_0
40
2_
5%
@R
V6
18
4.7
K_
04
02
_5
%@
12
RV
61
64
.7K
_0
40
2_
5%
@R
V6
16
4.7
K_
04
02
_5
%@
12
CV613 0.1U_0402_25V6CV613 0.1U_0402_25V61 2
CV123 0.1U_0402_10V7KCV123 0.1U_0402_10V7K12
RV602 4.7K_0402_5% RV602 4.7K_0402_5% 1 2
RV508 1M_0402_5%RV508 1M_0402_5%1 2
RV
90
10
0K
_0
40
2_
5%
RV
90
10
0K
_0
40
2_
5%
12
RV604 100K_0402_5%
RV604 100K_0402_5%
1 2
CV611 0.1U_0402_25V6CV611 0.1U_0402_25V61 2
RV
61
24
.7K
_0
40
2_
5%
@R
V6
12
4.7
K_
04
02
_5
%@
12
RV
61
74
.7K
_0
40
2_
5%
@R
V6
17
4.7
K_
04
02
_5
%@
12
CV608 0.1U_0402_25V6CV608 0.1U_0402_25V61 2
RV
61
04
.7K
_0
40
2_
5%
@R
V6
10
4.7
K_
04
02
_5
%@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USH CONN
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Close to JUSH1
USH_PWR_STATE#
USH_SMBCLK
USH_SMBDAT
SPI_DINTPMSPI_DOTPMSPI_CLKTPM
PCH_SPI_CS2#_R
SPI_CLKTPM
+3.3V_M_TPM
+3.3V_SUS
+3.3V_SUS+3.3V_RUN+5V_RUN
+3.3V_M_TPM+3.3V_M
+5V_RUN
+3.3V_SUS
+3.3V_RUN
PCH_PLTRST#_EC<20,30,35,36,9>
PCH_SPI_DIN<7>PCH_SPI_DO<7>
PCH_SPI_CLK<7>PCH_SPI_CS2#<7>
TPM_PIRQ#<12>
USH_DET#<10,12>
USBP6+<11>USBP6-<11>
BCM5882_ALERT#<35>
USH_PWR_STATE#<35>PLTRST_USH#<9>
USH_SMBDAT<36>USH_SMBCLK<36>
CONTACTLESS_DET#<10,7>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
USH & TPM
27 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
USH & TPM
27 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
USH & TPM
27 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RZ
35
33
_0
40
2_
5%
@E
MC
@R
Z35
33
_0
40
2_
5%
@E
MC
@
12
RZ17 0_0402_5%@ RZ17 0_0402_5%@ 1 2
CZ
4@
0.1
U_
04
02
_2
5V
6C
Z4
@0
.1U
_0
40
2_
25
V6
12
CZ
54
70
0P
_0
40
2_
25
V7
KC
Z5
47
00
P_
04
02
_2
5V
7K
12
CZ
10
@
0.1
U_
04
02
_2
5V
6C
Z1
0
@
0.1
U_
04
02
_2
5V
6
12
RZ10 1M_0402_5%RZ10 1M_0402_5%1 2
RZ9 2.2K_0402_5%RZ9 2.2K_0402_5%1 2
CZ
62
20
0P
_0
40
2_
50
V7
KC
Z6
22
00
P_
04
02
_5
0V
7K
12
RZ30 33_0402_5%RZ30 33_0402_5%1 2
CZ
12
@
0.1
U_
04
02
_2
5V
6C
Z1
2
@
0.1
U_
04
02
_2
5V
6
12
RZ26 33_0402_5%RZ26 33_0402_5%1 2
CZ
9@
EM
C@
0.1
U_
04
02
_2
5V
6C
Z9
@E
MC
@
0.1
U_
04
02
_2
5V
6
12
CZ
11
@
0.1
U_
04
02
_2
5V
6C
Z1
1
@
0.1
U_
04
02
_2
5V
6
12
CZ
72
20
0P
_0
40
2_
50
V7
KC
Z7
22
00
P_
04
02
_5
0V
7K
12
RZ29 33_0402_5%RZ29 33_0402_5%1 2
JUSH1
CONCR_205200FW010
CONN@JUSH1
CONCR_205200FW010
CONN@
11
33
44
55
66
88
99
22
77
GND21
GND22
1111
1212
1313
1414
1515
1616
1717
1818
1919
1010
2020
UZ1
AT97SC3205_TSSOP28~D
UZ1
AT97SC3205_TSSOP28~D
GPIO_317
PIRQ#20
MOSI23 MISO26
SPI_CLK21
SPI_CS#22
SPI_RST#16
NBO_527NBO_415
PP/GPIO7
GPIO_11
GPIO_22
GPIO-Express-006
TESTI8TESTBI9
VCC10
VCC19
VCC24
GND4 GND
11 GND18 GND25
VCC3
NBO_15
V_BAT12
NBO_213
NBO_314
NBO_628
PJP11@
PAD-OPEN1x1m
PJP11@
PAD-OPEN1x1m
1 2
RZ8 2.2K_0402_5%RZ8 2.2K_0402_5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SMBus Device Address 0xC8
Pin 6 is SVR_EN in Clarkville
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
RJ45 LOM circuit+3.3V_LAN:20mils
GNDCHASSISGNDCHASSIS use 40mil trace if necessary
Note:
+1.0V_LAN will work at 0.95V to 1.15V
Layout Notice : Place bead as
close UL4 as possible
Place CL3, CL4 and LL1 close to UL1
LAN ANALOG SWITCH
DOCKED1: TO DOCK
0: TO RJ45
Idc_min=500mA
DCR=100mohm
20130726 same as Goliad
10/15 change to
SP050006Y00 (S X'FORM_ NS692417 LAN)
For No-Vpro HW configs
+3.3V_LAN_OUT
+RSVD_VCC3P3_1
VCT_LAN_R1
LAN_DISABLE#_R
LAN_TEST_EN
LAN_TX0+LAN_TX0-
LAN_TX1+LAN_TX1-
LAN_TX2+LAN_TX2-
LAN_TX3+LAN_TX3-
LANCLK_REQ#
LOM_ACTLED_YEL#LOM_SPD100LED_ORG#LOM_SPD10LED_GRN#
PCIE_PRX_GLANTX_N3_C
PCIE_PRX_GLANTX_P3_C
PCIE_PTX_GLANRX_N3_C
PCIE_PTX_GLANRX_P3_C
REGCTL_PNP10RES_BIAS
TP_LAN_JTAG_TCK
TP_LAN_JTAG_TCK
TP_LAN_JTAG_TDITP_LAN_JTAG_TDOTP_LAN_JTAG_TMS
TP_LAN_JTAG_TMS
XTALIXTALOXTALO_R
+GND_CHASSIS
LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#
LED_100_ORG# LED_100_ORG_R#
LED_10_GRN# LED_10_GRN_R#
NB_LAN_TX0+
NB_LAN_TX0-
NB_LAN_TX1+
NB_LAN_TX1-
NB_LAN_TX2+
NB_LAN_TX2-
NB_LAN_TX3+
NB_LAN_TX3-
Z2805
Z2806
Z2807
Z2808
LAN_TX0+LLAN_TX0-L
LAN_TX1+LLAN_TX1-L
LAN_TX2+LLAN_TX2-L
LAN_TX3+LLAN_TX3-L
+3.3V_M_UL3
+3.3V_LAN_UL3
LAN_ACTLED_YEL#
LED_100_ORG#
SYS_LED_MASK#
SYS_LED_MASK#
SW_100_ORG#
SW_ACTLED_YEL#
LED_10_GRN#
SYS_LED_MASK#
SW_10_GRN#
LOM_ACTLED_YEL#LOM_SPD100LED_ORG#LOM_SPD10LED_GRN#
SW_100_ORG#SW_10_GRN#
SW_ACTLED_YEL#
SW_LAN_TX0+SW_LAN_TX0-
SW_LAN_TX1+SW_LAN_TX1-
SW_LAN_TX2+SW_LAN_TX2-
SW_LAN_TX3+SW_LAN_TX3-
LAN_TX0+L
LAN_TX0-L
LAN_TX1+L
LAN_TX1-L
LAN_TX2+L
LAN_TX2-L
LAN_TX3+L
LAN_TX3-L
NB_LAN_TX0+
NB_LAN_TX0-
NB_LAN_TX3+
NB_LAN_TX3-
NB_LAN_TX2+
NB_LAN_TX2-
NB_LAN_TX1+
NB_LAN_TX1-
SW_LAN_TX1+
SW_LAN_TX1-
SW_LAN_TX0+
SW_LAN_TX0-
SW_LAN_TX3+
SW_LAN_TX3-
SW_LAN_TX2+
SW_LAN_TX2-
LOM_SPD10LED_GRN#
LOM_SPD100LED_ORG#
+3.3V_LAN
+0.9V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+0.9V_LAN
+3.3V_M
+5V_ALW
+3.3V_ALW
+3.3V_LAN
+3.3V_LAN
+0.9V_LAN
+3.3V_LAN
+3.3V_M+3.3V_RUN
LANCLK_REQ#<7>
CLK_PCIE_LAN#<7>CLK_PCIE_LAN<7>
PCIE_PRX_GLANTX_P3<11>
PCIE_PRX_GLANTX_N3<11>
LAN_SMBDATA<7>LAN_SMBCLK<7>
PCIE_PTX_GLANRX_N3<11>
PCIE_PTX_GLANRX_P3<11>
PM_LANPHY_ENABLE<12,9>
LAN_DISABLE#_R<35>
LAN_WAKE#<12,36>
PLTRST_LAN#<9>
A_ON<36,38>
WLAN_LAN_DISBL# <35>
SYS_LED_MASK# <35,39>
DOCK_LOM_TRD0- <34>DOCK_LOM_TRD0+ <34>
DOCK_LOM_TRD1+ <34>DOCK_LOM_TRD1- <34>
DOCK_LOM_TRD2- <34>DOCK_LOM_TRD2+ <34>
DOCK_LOM_TRD3- <34>DOCK_LOM_TRD3+ <34>
DOCKED<22,31,35>
DOCK_LOM_ACTLED_YEL# <34>
DOCK_LOM_SPD10LED_GRN# <34>DOCK_LOM_SPD100LED_ORG# <34>
SIO_SLP_LAN#<36,9>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
LAN
28 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
LAN
28 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
LAN
28 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RL8@ 0_0603_5%RL8@ 0_0603_5%12
LL23 12NH_0603CS-120EJTS_5%EMC@ LL23 12NH_0603CS-120EJTS_5%EMC@
1 2
LL26 12NH_0603CS-120EJTS_5%EMC@ LL26 12NH_0603CS-120EJTS_5%EMC@
1 2
RL15
75_0402_1%
RL15
75_0402_1%
12
RL10@ 0_0402_5%RL10@ 0_0402_5%1 2
CL25
0.1
U_0402_25V
6C
L25
0.1
U_0402_25V
6
12
RL5
@10K
_0402_5%
RL5
@10K
_0402_5%
12
1:1
1:1
1:1
1:1
TL1
NS692417
1:1
1:1
1:1
1:1
TL1
NS692417
TD1+1
TD1-2
TDCT13
TDCT24
TD2+5
TD2-6
TD3+7
TD3-8
TDCT39
TDCT410
TD4+11
TD4-12
TX4-13
TX4+14 TXCT415
TXCT316
TX3-17
TX3+18
TX2-19
TX2+20 TXCT221
TXCT122
TX1-23
TX1+24
rev1
JLOM1
SANTA_130456-341
CONN@
rev1
JLOM1
SANTA_130456-341
CONN@
PR1+1
PR1-2
PR2+3
PR3+4
PR3-5
PR2-6
PR4+7
PR4-8
Yellow LED+9
Yellow LED-10
Green LED-11
Green-Orange LED+12
Orange LED-13
GND14
GND15
UL3
TPS22966DPUR_SON14_2X3
UL3
TPS22966DPUR_SON14_2X3
VIN11
VIN12
ON13
VBIAS4
ON25
VIN26
VIN27
VOUT28VOUT29
CT210
GND11
CT112
VOUT113VOUT114
GPAD15
LL21 12NH_0603CS-120EJTS_5%EMC@ LL21 12NH_0603CS-120EJTS_5%EMC@
1 2
QL1ADMN66D0LDW-7_SOT363-6
QL1ADMN66D0LDW-7_SOT363-6
1
2
6
CZ37 470P_0402_50V7KCZ37 470P_0402_50V7K1 2
CL19
0.1
U_0402_10V
7K
CL19
0.1
U_0402_10V
7K
12
RL19 150_0402_5%RL19 150_0402_5%1 2
RL111M_0402_5%RL111M_0402_5%
12
QL2ADMN66D0LDW-7_SOT363-6
QL2ADMN66D0LDW-7_SOT363-6
1
2
6
RL18
75_0402_1%
RL18
75_0402_1%
12
UL4
PI3L720ZHEX_TQFN42_9X3P5~D
UL4
PI3L720ZHEX_TQFN42_9X3P5~D
VD
D1
A0+2
A0-3
VD
D4
PD5
A1+6
A1-7
VD
D8
A2+9
A2-10
A3+11
A3-12
SEL13
VD
D14
LEDA015
LEDA116
LEDB017
LEDB118
LEDC019
LEDC120
VD
D21
C3-22C3+23
B3-24B3+25
C2-26C2+27
B2-28B2+29
VD
D30
C1-31C1+32
B1-33B1+34
C0-35C0+36
B0-37B0+38
VD
D39
LEDC240
LEDB241
LEDA242
PAD_GND43
CL15@
0.1U_0402_10V7K
CL15@
0.1U_0402_10V7K
1 2
PJP12
@
PAD-OPEN1x1m
PJP12
@
PAD-OPEN1x1m
12
LL24 12NH_0603CS-120EJTS_5%EMC@ LL24 12NH_0603CS-120EJTS_5%EMC@
1 2
CL6 0.1U_0402_10V7KCL6 0.1U_0402_10V7K1 2
RL9
@10K
_0402_5%
RL9
@10K
_0402_5%
12
RL17
75_0402_1%
RL17
75_0402_1%
12
T88@ PAD~DT88@ PAD~D
LL27 12NH_0603CS-120EJTS_5%EMC@ LL27 12NH_0603CS-120EJTS_5%EMC@
1 2
PCIE
MDI
SMBUS
JTAG
LED
UL1
WGI218LM-QQ89-B0_QFN48_6X6~D
PCIE
MDI
SMBUS
JTAG
LED
UL1
WGI218LM-QQ89-B0_QFN48_6X6~D
RSVD_VCC3P3_11
LANWAKE_N2
LAN_DISABLE_N3
VDD3P3_44
VDD3P3_IN5
SVR_EN_N6
CTRL0P97
VDD0P9_88
XTAL_OUT9
XTAL_IN10
VDD0P9_1111
RBIAS12
MDI_PLUS013
MDI_MINUS014
VDD3P3_1515
VDD0P9_1616
MDI_PLUS117
MDI_MINUS118
VDD3P3_1919
MDI_PLUS220
MDI_MINUS221
VDD0P9_2222
MDI_PLUS323
MDI_MINUS324
LED225
LED026
LED127
SMB_CLK28
VDD3P3_2929
TEST_EN30
SMB_DATA31
JTAG_TDI32
JTAG_TMS33 JTAG_TDO34
JTAG_TCK35
PE_RST_N36
VDD0P9_3737
PETp38
PETn39
VDD0P9_4040
PERp41
PERn42
VDD0P9_4343
PE_CLKP44
PE_CLKN45
VDD0P9_4646VDD0P9_4747
CLK_REQ_N48
VSS_EPAD49
CL3
0.1
U_0402_10V
7K
CL3
0.1
U_0402_10V
7K
12
CL26
0.1
U_0402_25V
6C
L26
0.1
U_0402_25V
6
12
CL4
10U
_0603_6.3
V6M
CL4
10U
_0603_6.3
V6M
12
LL1
4.7UH_BRC2012T4R7MD_20%
LL1
4.7UH_BRC2012T4R7MD_20%1 2
CL10
0.1
U_0402_10V
7K
CL10
0.1
U_0402_10V
7K
12
CL2 0.1U_0402_10V7KCL2 0.1U_0402_10V7K12
RL2@ 10K_0402_5%RL2@ 10K_0402_5%1 2
RL14 150_0402_5%RL14 150_0402_5%1 2
RL1@ 10K_0402_5%RL1@ 10K_0402_5%1 2
RL12
1K
_0402_5%
RL12
1K
_0402_5%
12
CZ36 0.1U_0402_10V7K@ CZ36 0.1U_0402_10V7K@1 2
CL17
0.4
7U
_0603_10V
7K
CL17
0.4
7U
_0603_10V
7K
12
T89@ PAD~DT89@ PAD~D
QL2BDMN66D0LDW-7_SOT363-6
QL2BDMN66D0LDW-7_SOT363-6
34
5
CL7
1U
_0603_10V
6K
CL7
1U
_0603_10V
6K
12
RL7 0_0402_5%@ RL7 0_0402_5%@1 2
RL4 4.7K_0402_5%@ RL4 4.7K_0402_5%@12
RZ54 0_0603_5%NVPRO@ RZ54 0_0603_5%NVPRO@1 2
CL1 0.1U_0402_10V7KCL1 0.1U_0402_10V7K12
RL13
3.0
1K
_0402_1%
RL13
3.0
1K
_0402_1%
12
CL5 0.1U_0402_10V7KCL5 0.1U_0402_10V7K1 2
CL
12
22
U_
06
03
_6
.3V
6M
CL
12
22
U_
06
03
_6
.3V
6M
1
2
LL22 12NH_0603CS-120EJTS_5%EMC@ LL22 12NH_0603CS-120EJTS_5%EMC@
1 2
RL20 150_0402_5%RL20 150_0402_5%1 2
LL25 12NH_0603CS-120EJTS_5%EMC@ LL25 12NH_0603CS-120EJTS_5%EMC@
1 2
LL28 12NH_0603CS-120EJTS_5%EMC@ LL28 12NH_0603CS-120EJTS_5%EMC@
1 2
CL21
0.4
7U
_0603_10V
7K
CL21
0.4
7U
_0603_10V
7K
12
RL16
75_0402_1%
RL16
75_0402_1%
12
CL11
0.1
U_0402_10V
7K
CL11
0.1
U_0402_10V
7K
12
CL
14
27
P_
04
02
_5
0V
8J
CL
14
27
P_
04
02
_5
0V
8J
12
RL6 4.7K_0402_5%RL6 4.7K_0402_5%12
UL2
TC7SH08FU_SSOP5
UL2
TC7SH08FU_SSOP5
B1
A2 Y
4
P5
G3
CL16
0.4
7U
_0603_10V
7K
CL16
0.4
7U
_0603_10V
7K
12
CL18
470P
_0402_50V
7K
CL18
470P
_0402_50V
7K
12
RL3 0_0402_5%@ RL3 0_0402_5%@12
CL27
0.1
U_0402_25V
6C
L27
0.1
U_0402_25V
6
12
YL1
25MHZ_18PF_7V25000034
YL1
25MHZ_18PF_7V25000034
IN1
GND2
OUT3
GND4
CL20
0.4
7U
_0603_10V
7K
CL20
0.4
7U
_0603_10V
7K
12
CL
13
27
P_
04
02
_5
0V
8J
CL
13
27
P_
04
02
_5
0V
8J
12
CL22EMC@
150P_1808_2.5KV8JCL22EMC@
150P_1808_2.5KV8J1 2
CL24 470P_0402_50V7KCL24 470P_0402_50V7K1 2
CL23 0.1U_0402_10V7K@ CL23 0.1U_0402_10V7K@1 2
CL8
0.1
U_0402_10V
7K
CL8
0.1
U_0402_10V
7K
12
CL9
0.1
U_0402_10V
7K
CL9
0.1
U_0402_10V
7K
12
QL1BDMN66D0LDW-7_SOT363-6
QL1BDMN66D0LDW-7_SOT363-6
34
5
RZ55 0_0603_5%VPRO@
RZ55 0_0603_5%VPRO@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
CR3 close to U27.9
CR1 CR2 close to U27.35
CR4 close to U27.42
CR6 close to U27.23
please routing daisy chain
1. from UR1.38 (SD_D0) -> UR1.30 (SD_RCLK_P) -> LR3.4
2. From UR1.37 (SD_D1) -> UR1.29 (SD_RCLK_N) -> LR3.1
EMI depop location
CR31 near UR1.22 CR34 near UR1.24
EMI solution for SD card
R231,R297,R306,R315,R333,R337 for EMI solution
If support RTD3 cold the AUX and MAIN power rail should be
use different power rail; for RTD3 hot please keep this circuit
20130726 SP070011L00 CIS Link OK
+AUX_LDO
+SD_IO_LDO
IO_LDOSELIO_LDOSEL
MEDIACARD_PWREN SD_REXT
PCIE_PRX_MMITX_N1_CPCIE_PRX_MMITX_P1_C
PCIE_PTX_MMIRX_N1_CPCIE_PTX_MMIRX_P1_C
PE_REXT
SD/MMCCD#
SD/MMCCD#
SD/MMCCLK
SD/MMCCLK
SD/MMCCLK_RSD/MMCCMD
SD/MMCCMD
SD/MMCDAT0SD/MMCDAT1SD/MMCDAT2 SD/MMCDAT2_R
SD/MMCDAT2_R
SD/MMCDAT3 SD/MMCDAT3_R
SD/MMCDAT3_R
SDWP
SDWP
SD_UHS2_D0N
SD_UHS2_D0N
SD_UHS2_D0P
SD_UHS2_D0P
SD_UHS2_D1N
SD_UHS2_D1N
SD_UHS2_D1P
SD_UHS2_D1P
SD/MMCDAT0SD/MMCDAT1
MEDIACARD_PWREN
+3.3V_MMI
+1.2V_LDO
+3.3V_RUN_CARD
+1.8V_RUN_CARD
+3.3V_MMI
+3.3V_RUN_CARD+1.8V_RUN_CARD
+1.2V_LDO
+3.3V_MMI
+3.3V_MMI
+3.3V_MMI+3.3V_RUN
+1.8V_RUN_CARD+3.3V_RUN_CARD
+3.3V_MMI
PCIE_PTX_MMIRX_N1<11>PCIE_PTX_MMIRX_P1<11>
PCIE_PRX_MMITX_P1<11>PCIE_PRX_MMITX_N1<11>
CLK_PCIE_MMI<7>CLK_PCIE_MMI#<7>
MMICLK_REQ#<6,7>
MEDIACARD_IRQ#<12>
PLTRST_MMI#<9>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Card Reader
29 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Card Reader
29 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Card Reader
29 48Wednesday, March 19, 2014
Compal Electronics, Inc.
CR25 0.1U_0402_10V7KCR25 0.1U_0402_10V7K1 2
RR2 191_0402_1%RR2 191_0402_1%1 2
CR
40
.1U
_0
40
2_
25
V6
CR
40
.1U
_0
40
2_
25
V6
12
CR
30
.1U
_0
40
2_
25
V6
CR
30
.1U
_0
40
2_
25
V6
12
CR
34
4.7
U_
06
03
_6
.3V
6K
CR
34
4.7
U_
06
03
_6
.3V
6K
12
RR
8@
10
0K
_0
40
2_
5%
RR
8@
10
0K
_0
40
2_
5%
12
RR5 4.7K_0402_1%RR5 4.7K_0402_1%1 2
CR26 0.1U_0402_10V7KCR26 0.1U_0402_10V7K1 2
RR
61
00
K_
04
02
_5
%R
R6
10
0K
_0
40
2_
5%
12
RR15 10K_0402_5%RR15 10K_0402_5%1 2
CR
19
0.1
U_
04
02
_2
5V
6C
R1
90
.1U
_0
40
2_
25
V6
12
CR
10
0.1
U_
04
02
_2
5V
6C
R1
00
.1U
_0
40
2_
25
V6
12
RR
11
1M
_0
40
2_
5%
RR
11
1M
_0
40
2_
5%
12
CR
35
0.1
U_
04
02
_2
5V
6C
R3
50
.1U
_0
40
2_
25
V6
12
CR
74
.7U
_0
60
3_
6.3
V6
KC
R7
4.7
U_
06
03
_6
.3V
6K
12
CR
20
.1U
_0
40
2_
25
V6
CR
20
.1U
_0
40
2_
25
V6
12
RR4@EMC@ 0_0402_5%RR4@EMC@ 0_0402_5%1 2
CR
31
1U
_0
40
2_
6.3
V6
KC
R3
11
U_
04
02
_6
.3V
6K
12
JSD1
ALPS_SCDADA0101_NR
CONN@JSD1
ALPS_SCDADA0101_NR
CONN@
D1+16
VDD214
DO-12
VSS310
DAT29 DAT1/RCLK-8
VSS26
VDD/VDD14
VSS13
D1-15
VSS413
D0+11
DAT0/RCLK+7
CLK5 CMD2
CD/DAT31
CARD DETECT18
WRITE PROTEC19
GND120
GND221
GND322
GND423
GND524
GND625
VSS517
GND726
CR
21
0.1
U_
04
02
_2
5V
6C
R2
10
.1U
_0
40
2_
25
V6
12
CR
23
@E
MC
@5
P_
04
02
_5
0V
8C
CR
23
@E
MC
@5
P_
04
02
_5
0V
8C
12
CR
80
.1U
_0
40
2_
25
V6
CR
80
.1U
_0
40
2_
25
V6
12
RR3@EMC@ 0_0402_5%RR3@EMC@ 0_0402_5%1 2
CR27 0.1U_0402_10V7KCR27 0.1U_0402_10V7K1 2
CR
14
.7U
_0
60
3_
6.3
V6
KC
R1
4.7
U_
06
03
_6
.3V
6K
12
PJP26@
PAD-OPEN1x1m
PJP26@
PAD-OPEN1x1m
1 2
CR
13
0.1
U_
04
02
_2
5V
6C
R1
30
.1U
_0
40
2_
25
V6
12
CR
18
4.7
U_
06
03
_6
.3V
6K
CR
18
4.7
U_
06
03
_6
.3V
6K
12
CR
60
.1U
_0
40
2_
25
V6
CR
60
.1U
_0
40
2_
25
V6
12
CR
14
4.7
U_
06
03
_6
.3V
6K
CR
14
4.7
U_
06
03
_6
.3V
6K
12
CR
94
.7U
_0
60
3_
6.3
V6
KC
R9
4.7
U_
06
03
_6
.3V
6K
12 C
R1
71
U_
04
02
_6
.3V
6K
CR
17
1U
_0
40
2_
6.3
V6
K
1
2
CR
22
0.1
U_
04
02
_2
5V
6C
R2
20
.1U
_0
40
2_
25
V6
12
CR24 0.1U_0402_10V7KCR24 0.1U_0402_10V7K1 2
CR
15
0.1
U_
04
02
_2
5V
6C
R1
50
.1U
_0
40
2_
25
V6
12
RR1 EMC@ 10_0402_5%RR1 EMC@ 10_0402_5%1 2
OZ777FJ2LN
UR1
OZ777FJ2LN_QFN48_6X6
OZ777FJ2LN
UR1
OZ777FJ2LN_QFN48_6X6
PE_12VCCAIN1
PE_REFCLKM2
PE_REFCLKP3
PE_REXT4
PE_RXM5 PE_RXP6
PE_TXP7
PE_TXM8
PE_33VCCAIN9
MAIN_LDO_12VOUT10
MAIN_LDO_VIN11
AUX_LDO_CAP12
AUX _33VIN13
MAIN_LDO_EN14
PE_RST#_GATE#15
DEV_WAKE#16
CLKREQ#17
IO0_LDOSEL18
LED#19
SD_WPI20
SD_CD#21
SD_SKT_33VOUT22
SD_SKT_33VIN23
SD_SKT_18VOUT24
SD_IO_LDO_CAP25
SD_REXT/NC26
UHSII_33VCCAIN/NC27
UHSII_12VCCAIN/NC28
SD_RCLK_M/NC29
SD_RCLK_P/NC30
UHSII_12VCCAIN/NC31
SD_D1P/NC32
SD_D1M/NC33
SD_D0M/NC34
SD_D0P/NC35
UHSII_12VCCAIN/NC36
SD_D137
SD_D038
MMC_D739
MMC_D640
CORE_12VCCD41
SD_33VCCD42
SD_CLK43
MMC_D544
SD_CMD45
MMC_D446
SD_D347
SD_D248
GND49
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+3.3V
VoltageTolerance
PWRRail
Primary Power Aux Power
Peak Normal Normal
LED control circuit
NGFF slot A Key A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Power Rating TBD
NGFF slot B Key B NGFF for UMA
STATE #
15
14
8
0
CONFIG_1
GND
CONFIG_0 CONFIG_2
1
CONFIG_3 Module Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDHIGH
HIGH
HIGH HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
SSD-SATA
SSD-PCIE
WWAN
HCA-PCIE
NA
3.3V_ALW for LID power
BT_RADIO_DIS#_R
BT_LED#
WLAN_LED#
WLAN_WIGIG60GHZ_DIS#_R
PCIE_PTX_WLANRX_P4_CPCIE_PTX_WLANRX_N4_C
WIGIG_32KHZ
PCIE_WAKE#
PCH_PLTRST#_ECBT_RADIO_DIS#_R
WLAN_WIGIG60GHZ_DIS#_R
PCIE_WAKE#
PCH_PLTRST#_EC
UIM_RESETUIM_CLKUIM_DATA
UIM_DET
PCIE_PTX_SATARX_N6_L0_CPCIE_PTX_SATARX_P6_L0_C
WWAN_LED#
WWAN_LED#WWAN_RADIO_DIS#_R
+3.3V_WWAN_UZ2
+3.3V_WLAN_UZ2
mSATA_DEVSLP
PCIE_PTX_SATARX_P6_L1_CPCIE_PTX_SATARX_N6_L1_C
PCH_PLTRST#_EC
PCIE_WAKE#
3.3V_WWAN_EN
BT_LED#
WLAN_LED#
WIGIG_LANE_P2_C
WIGIG_LANE_N3_CWIGIG_LANE_P3_C
WIGIG_LANE_N2_C
WIGIG_AUX#_CWIGIG_AUX_C
WIGIG_LANE_N1_CWIGIG_LANE_P1_C
WIGIG_LANE_N0_CWIGIG_LANE_P0_C
PCIE_PTX_WIGIGRX_P5_CPCIE_PTX_WIGIGRX_N5_C
HW_GPS_DISABLE2#_R
HW_GPS_DISABLE2#_R
UIM_DATAUIM_DETUIM_RESET
UIM_CLK
AUX_EN_WOWL
AUX_EN_WOWL
ANTCTL0
ANTCTL2ANTCTL1
ANTCTL3
ANTCTL0 ANTCTL1
ANTCTL2 ANTCTL3
UIM_RESETUIM_CLK
UIM_DATA
WWAN_RADIO_DIS#_R
WWAN_PWR_EN
WWAN_PWR_EN
AUX_EN_WOWLWIGIG_32KHZWIGIG_32KHZ_R
+3.3V_WLAN
+3.3V_WLAN
+3.3V_WLAN+3.3V_WWAN
+SIM_PWR
+3.3V_WWAN+3.3V_ALW
+5V_ALW
+3.3V_WLAN
+3.3V_WWAN
+3.3V_WWAN
+3.3V_ALW
+3.3V_ALW
+SIM_PWR
+3.3V_WWAN +3.3V_WWAN
+3.3V_WWAN
+3.3V_ALW
BT_RADIO_DIS#<35>
WIRELESS_LED# <35,39>
WLAN_WIGIG60GHZ_DIS#<35>
USBP2+<11>USBP2-<11>
PCIE_PTX_WLANRX_P4<11>PCIE_PTX_WLANRX_N4<11>
PCIE_PRX_WLANTX_N4<11>PCIE_PRX_WLANTX_P4<11>
CLK_PCIE_WLAN#<7>CLK_PCIE_WLAN<7>
WLANCLK_REQ#<12,7>
PCH_CL_RST1# <7>PCH_CL_DATA1 <7>
PCH_CL_CLK1 <7>
PCIE_WAKE#<35>
PCH_PLTRST#_EC <20,27,35,36,9>
PCIE_PRX_WIGIGTX_N5<11>PCIE_PRX_WIGIGTX_P5<11>
CLK_PCIE_WIGIG<7>CLK_PCIE_WIGIG#<7>
WIGIGCLK_REQ# <12,7>
WIGIG_HPD<26>
USBP7+<11>USBP7-<11>
mSATA_DEVSLP <12>
PCIE_PRX_SATATX_P6_L0<6>PCIE_PRX_SATATX_N6_L0<6>
PCIE_PTX_SATARX_P6_L0<6>PCIE_PTX_SATARX_N6_L0<6>
WWAN_RADIO_DIS#<35>
3.3V_WWAN_EN<35>
PCIE_PRX_SATATX_P6_L1<6>PCIE_PRX_SATATX_N6_L1<6>
PCIE_PTX_SATARX_P6_L1<6>PCIE_PTX_SATARX_N6_L1<6>
CLK_PCIE_SATA#<7>CLK_PCIE_SATA<7>
SATACLK_REQ# <7>
NGFF_CONFIG_3<35>
NGFF_CONFIG_0<35>
NGFF_CONFIG_1<35>
NGFF_CONFIG_2<35>
WIGIG_LANE_N3<26>WIGIG_LANE_P3<26>
WIGIG_LANE_N2<26>WIGIG_LANE_P2<26>
WIGIG_AUX# <26>
WIGIG_LANE_N0 <26>
WIGIG_LANE_P1 <26>WIGIG_LANE_N1 <26>
WIGIG_AUX <26>
WIGIG_LANE_P0 <26>
PCIE_PTX_WIGIGRX_P5<11>PCIE_PTX_WIGIGRX_N5<11>
HW_GPS_DISABLE2#<35>
WWAN_WAKE#<35>
LID_CL#<35,39>
AUX_EN_WOWL<35>
EC_32KHZ_MEC5085<35,36>
SUSCLK<9>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
NGFF Card
30 40Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
NGFF Card
30 40Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
NGFF Card
30 40Wednesday, March 19, 2014
Compal Electronics, Inc.
CZ
5333P
_0402_50V8J
CZ
5333P
_0402_50V8J
12
CZ59 0.1U_0402_10V7KCZ59 0.1U_0402_10V7K1 2
CZ
6333P
_0402_50V8J
@
CZ
6333P
_0402_50V8J
@
12
CZ
5533P
_0402_50V8J
CZ
5533P
_0402_50V8J
12
CZ22 0.1U_0402_10V7KCZ22 0.1U_0402_10V7K1 2
DZ2RB751S40T1G_SOD523-2
DZ2RB751S40T1G_SOD523-2
1 2
RZ40 100K_0402_5%RZ40 100K_0402_5%1 2
CV1520.1U_0402_25V6 CV1520.1U_0402_25V612
CZ
66
47P
_0402_50V
8J
@CZ
66
47P
_0402_50V
8J
@
12
CZ13 0.1U_0402_10V7KCZ13 0.1U_0402_10V7K1 2
CZ
6433P
_0402_50V8J
@
CZ
6433P
_0402_50V8J
@
12
RZ45 0_0603_5%@ RZ45 0_0603_5%@1 2
QZ11ADMN66D0LDW-7_SOT363-6
QZ11ADMN66D0LDW-7_SOT363-6
1
2
6
JNGFF2
BELLW_80149-3221
CONN@JNGFF2
BELLW_80149-3221
CONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
5353
5454
5555
5656
5757
5858
5959
6060
6161
6262
6363
6464
6565
6666
6767
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
GND68
GND69
RZ57 0_0402_5%RZ57 0_0402_5%1 2
RZ48 0_0603_5%@ RZ48 0_0603_5%@1 2
CZ
15@
0.1U_0402_25V
6C
Z15
@0.1U
_0402_25V6
12
CZ
170.1U
_0402_25V6
CZ
170.1U
_0402_25V61
2
CZ
160.047U
_0402_16V4Z
CZ
160.047U
_0402_16V4Z
12
CZ
6533P
_0402_50V8J
@
CZ
6533P
_0402_50V8J
@
12
CZ
200.047U
_0402_16V4Z
CZ
200.047U
_0402_16V4Z
12
JSH1
CONCR_205120FW010
CONN@
JSH1
CONCR_205120FW010
CONN@
44
33
22
11
66
55
GND113 GND214
77 88 99 10
10 1111 1212
CZ
510.047U
_0402_16V4Z
CZ
510.047U
_0402_16V4Z
12
UZ2
TPS22966DPUR_SON14_2X3
UZ2
TPS22966DPUR_SON14_2X3
VIN11
VIN12
ON13
VBIAS4
ON25
VIN26
VIN27
VOUT28VOUT29
CT210
GND11
CT112
VOUT113VOUT114
GPAD15
CV145 0.1U_0402_25V6CV145 0.1U_0402_25V61 2
CZ50
0.1U_0402_10V7K
@CZ50
0.1U_0402_10V7K
@
12
QZ2BDMN66D0LDW-7_SOT363-6
QZ2BDMN66D0LDW-7_SOT363-6
34
5
CZ32 0.1U_0402_10V7KCZ32 0.1U_0402_10V7K1 2
C263
0.1
U_0402_16V
4Z
@C263
0.1
U_0402_16V
4Z
@1
2
CV1490.1U_0402_25V6 CV1490.1U_0402_25V612
DZ5RB751S40T1G_SOD523-2
DZ5RB751S40T1G_SOD523-2
1 2
CZ14 0.1U_0402_10V7KCZ14 0.1U_0402_10V7K1 2
PJP42
@
PAD-OPEN1x1m
PJP42
@
PAD-OPEN1x1m
12
CZ49470P_0402_50V7K
CZ49470P_0402_50V7K
1 2
RZ
15100K
_0402_5%R
Z15
100K_0402_5%
12
CZ21 0.1U_0402_10V7KCZ21 0.1U_0402_10V7K1 2
RZ
37100K
_0402_5%R
Z37
100K_0402_5%
12
CV147 0.1U_0402_25V6CV147 0.1U_0402_25V61 2
PJP13 @
PAD-OPEN1x1m
PJP13 @
PAD-OPEN1x1m
12
RZ50 0_0402_5%@ RZ50 0_0402_5%@1 2
CV1500.1U_0402_25V6 CV1500.1U_0402_25V612
CV146 0.1U_0402_25V6CV146 0.1U_0402_25V61 2
CV1570.1U_0402_25V6 CV1570.1U_0402_25V612
PJP41 @
PAD-OPEN1x1m
PJP41 @
PAD-OPEN1x1m
12
CZ
180.1U
_0402_25V6
CZ
180.1U
_0402_25V61
2
CZ33 0.1U_0402_10V7KCZ33 0.1U_0402_10V7K1 2
DZ6RB751S40T1G_SOD523-2
DZ6RB751S40T1G_SOD523-2
1 2
+ CZ
57
150U
_B
2_6.3
VM
_R
35M
@+ CZ
57
150U
_B
2_6.3
VM
_R
35M
@
1
2
QZ11BDMN66D0LDW-7_SOT363-6
QZ11BDMN66D0LDW-7_SOT363-6
34
5
CZ
54
22U
_0603_6.3
V6M
CZ
54
22U
_0603_6.3
V6M
1
2
CV1530.1U_0402_25V6 CV1530.1U_0402_25V612
UZ11
TC7SH08FU_SSOP5
UZ11
TC7SH08FU_SSOP5
B1
A2 Y
4
P5
G3
CZ23470P_0402_50V7K
CZ23470P_0402_50V7K
1 2
QZ2ADMN66D0LDW-7_SOT363-6
QZ2ADMN66D0LDW-7_SOT363-6
1
2
6
CZ24 0.1U_0402_10V7K@ CZ24 0.1U_0402_10V7K@1 2
RZ46 0_0603_5%@ RZ46 0_0603_5%@1 2
CV1560.1U_0402_25V6 CV1560.1U_0402_25V612
CV148 0.1U_0402_25V6CV148 0.1U_0402_25V61 2
CZ58 0.1U_0402_10V7KCZ58 0.1U_0402_10V7K1 2
JNGFF1
BELLW_80148-3521
CONN@JNGFF1
BELLW_80148-3521
CONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
5353
5454
5555
5656
5757
5858
5959
6060
6161
6262
6363
6464
6565
6666
6767
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
GND68
GND69
PJP32
@PAD-OPEN1x1m
PJP32
@PAD-OPEN1x1m
12
DZ1RB751S40T1G_SOD523-2
DZ1RB751S40T1G_SOD523-2
1 2
RZ56 0_0402_5%@ RZ56 0_0402_5%@1 2
RZ
14100K
_0402_5%R
Z14
100K_0402_5%
12
RZ39@ 10K_0402_5%RZ39@ 10K_0402_5%1 2
CZ
520.047U
_0402_16V4Z
CZ
520.047U
_0402_16V4Z
12
RZ38 100K_0402_5%RZ38 100K_0402_5%1 2
CZ
194.7U
_0603_6.3V6K
CZ
194.7U
_0603_6.3V6K
12
RZ47 0_0603_5%@ RZ47 0_0603_5%@1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
PCB
G14U_En
G14D_En
G14 UMA
G14 DSC
G12 UMA
USB2 3
USB3102
USB2 0
G12 Entry NA
NA
NA
NA
NA
NX3DV221
NA
USB3102 NX3DV221
USB3102 NX3DV221
20130730 DC23300C0B0 CIS Link OK
20130730 DC23300C0B0 CIS Link OK
CI19 near UI3.1
M/B
Dock
function
0
1
check port mapping
DOCKED
function
Dock
M/B
1
0
DOCKED_LIO_EN
check port mapping
support APR/SPR/LIO Dock
USB3RN1_D- USB3RN1_D-
USB3RP1_D+ USB3RP1_D+
USB3TN1_D- USB3TN1_D-
USB3TP1_D+ USB3TP1_D+
USBP0_R_D+
USBP0_R_D-
USBP3_D+
USBP3_D-
USB3RN4_D-
USB3RN4_D- USB3RN4_D-
USB3RP4_D+
USB3RP4_D+ USB3RP4_D+USB3TN4_D-
USB3TN4_D- USB3TN4_D-USB3TP4_D+
USB3TP4_D+ USB3TP4_D+
USB3TN1_D-USB3TP1_D+
USB3RP1_D+USB3RN1_D-
USBP3_D+USBP3_D-
USB3TP4_D+USB3TN4_D-
USB3RP4_D+USB3RN4_D-
USB3RN1_D-
USB3RP1_D+
USB3TP1_D+SW_USB3TP1
SW_USB3TN1 USB3TN1_D-
USBP0_R_D-USBP0_R_D+
PS_USBP0_D-
PS_USBP0_D+
SW_USBP3+
SW_USBP3-
SW_USB3RN1
SW_USB3RP1
USB3TN1_C
USB3TP1_C
USB3TN4_C
USB3TP4_C
ILIM_SEL
ILIM_SEL
PS_USBP0_D-PS_USBP0_D+
SW_USBP0+SW_USBP0-
SW_USB3RP1SW_USB3RN1
SW_USBP0-SW_USBP0+
SW_USB3TP1SW_USB3TN1
SW_USBP3+SW_USBP3-
+5V_ALW +USB_RIGHT_PWR
+5V_USB_CHG_PWR
+USB_RIGHT_PWR
+5V_ALW+5V_ALW
+5V_ALW+5V_USB_CHG_PWR
+3.3V_SUS
+3.3V_SUS
USB_OC2# <11,12>USB_PWR_EN2#<35>
USB_PWR_SHR_VBUS_EN<35>
USB_OC0#<11>
USB_PWR_SHR_EN#<35,36>
USB3TP1<11>
USBP0-<11>
USB3RN1<11>USB3RP1<11>USB3TN1<11>
DOCKED<22,28,35>
USBP0+<11>
DOCK_USB3RN1 <34>DOCK_USB3RP1 <34>DOCK_USB3TN1 <34>DOCK_USB3TP1 <34>
DOCK_USBP0+ <34>DOCK_USBP0- <34>
USB3RP4<11>
USB3RN4<11>
USB3TP4<11>
USB3TN4<11>
DOCKED_LIO_EN<35>
DOCK_USBP3- <34>DOCK_USBP3+ <34>
USBP3-<11>USBP3+<11>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
USB3.0
31 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
USB3.0
31 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
USB3.0
31 48Wednesday, March 19, 2014
Compal Electronics, Inc.
CI12
0.1U_0402_25V
6C
I120.1U
_0402_25V6
12
CI8
100U_1206_6.3V
6MC
I8100U
_1206_6.3V6M
12
CI415
0.1U_0402_25V
6C
I4150.1U
_0402_25V6
12
LI8
DLW21HN900HQ2L_4P
EMC@LI8
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
CI10
0.1U_0402_25V
6C
I100.1U
_0402_25V6
12
CI27 0.1U_0402_10V7KCI27 0.1U_0402_10V7K12
CI5 0.1U_0402_10V7KCI5 0.1U_0402_10V7K12
CI419
@0.1U
_0402_25V6
CI419
@0.1U
_0402_25V6
12
JUSB1 CONN@
SANTA_373070-2
JUSB1 CONN@
SANTA_373070-2
VBUS1
D-2
D+3
GND4
SSRX-5
SSRX+6
GND7
SSTX-8
SSTX+9
GND10
GND11
GND12
GND13
CI420
4.7U_0603_6.3V
6KC
I4204.7U
_0603_6.3V6K
12
LI2
DLW21HN900HQ2L_4P
EMC@LI2
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
CI1
90.1
U_0402_25V
6C
I19
0.1
U_0402_25V
6
1
2
CI418
@0.1U
_0402_25V6
CI418
@0.1U
_0402_25V6
12
CI3
0.1U_0402_25V
6C
I30.1U
_0402_25V6
12
DI3
AZC199-02SPR7G_SOT23-3EMC@DI3
AZC199-02SPR7G_SOT23-3EMC@
22
33
11
CI414
0.1U_0402_25V
6C
I4140.1U
_0402_25V6
12
CI1
100U_1206_6.3V
6MC
I1100U
_1206_6.3V6M
12
RI1422.1K_0402_1%
RI1422.1K_0402_1%
12
CI4 0.1U_0402_10V7KCI4 0.1U_0402_10V7K12
RI1310K_0402_5%
RI1310K_0402_5%
12
UI2
SY6288D10CAC_MSOP8
UI2
SY6288D10CAC_MSOP8
GND1
VIN2
VIN3
EN4
FLG5VOUT6VOUT7VOUT8
LI3
DLW21HN900HQ2L_4P
EMC@LI3
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
JUSB2 CONN@
SANTA_373070-2
JUSB2 CONN@
SANTA_373070-2
VBUS1
D-2
D+3
GND4
SSRX-5
SSRX+6
GND7
SSTX-8
SSTX+9
GND10
GND11
GND12
GND13
LI1
DLW21HN900HQ2L_4P
EMC@LI1
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
UI5
NX3DV221GM_XQFN10U10_2X1P55
UI5
NX3DV221GM_XQFN10U10_2X1P55
1D+1
1D-2
2D+3
2D-4
GND5
OE#6 D-7 D+8 S9 VCC
10
8
7
65
4
3
2
1
9
10
DI1
L05ESDL5V0NA-4_SLP2510P8-10-9
EMC@
8
7
65
4
3
2
1
9
10
DI1
L05ESDL5V0NA-4_SLP2510P8-10-9
EMC@
4
5
1
6
2
7
3
9
8
8
7
65
4
3
2
1
9
10
DI6
L05ESDL5V0NA-4_SLP2510P8-10-9
EMC@
8
7
65
4
3
2
1
9
10
DI6
L05ESDL5V0NA-4_SLP2510P8-10-9
EMC@
4
5
1
6
2
7
3
9
8
UI3
TPS2544RTER_WQFN16_3X3
UI3
TPS2544RTER_WQFN16_3X3
IN1
NC9
FAULT#13
ILIM_SEL4
EN5
CTL16
CTL27
CTL38
OUT12
DP_IN10
DM_IN11
DM_OUT2
DP_OUT3
ILIM_LO15
ILIM_HI16
GND14
GNDP17
UI4
PI3USB3102ZLEX_TQFN32_6X3
UI4
PI3USB3102ZLEX_TQFN32_6X3
TX+1
TX-2
VDD3
RX+4
RX-5
D+6
D-7
USB_ID8
VDD9
SS_SEL10
OE#11
VDD12
USB_IDB13D-B14D+B15
VDD16
USB_IDA17D-A18D+A19VDD
20
GND21
RX-B22RX+B23TX-B24TX+B25
RX-A26RX+A27
GND28
VDD29
TX-A30TX+A31
HS_SEL32
HGND33
DI2
AZC199-02SPR7G_SOT23-3
EMC@DI2
AZC199-02SPR7G_SOT23-3
EMC@22
33
11
CI416
0.1U_0402_25V
6C
I4160.1U
_0402_25V6
12
CI38
0.1U_0402_25V
6C
I380.1U
_0402_25V6
12
CI417
@0.1U
_0402_25V6
CI417
@0.1U
_0402_25V6
12
CI11
10U_0603_6.3V
6M@
CI11
10U_0603_6.3V
6M@
12
LI9
DLW21HN900HQ2L_4P
EMC@LI9
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
CI28 0.1U_0402_10V7KCI28 0.1U_0402_10V7K12
LI4
DLW21HN900HQ2L_4P
EMC@LI4
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
USB3TP2_D+USB3TN2_D-
USB3RN2_D-USB3RP2_D+
USBP1_R_D-USBP1_R_D+
USB3TP2_D+
USB3TN2_D-
USB3TN2_D-
USB3TP2_D+
USB3TN2_D-
USB3TP2_D+
USB3RP2_D+
USB3RN2_D-
USB3RP2_D+
USB3RN2_D- USB3RN2_D-
USB3RP2_D+
USBP1_R_D-
USBP1_R_D+
USB3TN2_C
USB3TP2_C
+USB_SIDE_PWR
+5V_ALW +USB_SIDE_PWR
USB3TN2<11>
USB3TP2<11>
USB3RP2<11>
USB3RN2<11>
USB_PWR_EN1#<35> USB_OC1# <11,12>
USBP1-<11>
USBP1+<11>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
USB SW
32 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
USB SW
32 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
USB SW
32 48Wednesday, March 19, 2014
Compal Electronics, Inc.
CI7
0.1
U_
04
02
_2
5V
6C
I70
.1U
_0
40
2_
25
V6
12
LI7
DLW21HN900HQ2L_4P
EMC@LI7
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
JUSB3 CONN@
TAITW_PUBAUE-09FLBS1FF4H0
JUSB3 CONN@
TAITW_PUBAUE-09FLBS1FF4H0
VBUS1
D-2
D+3
GND4
StdA-SSRX-5
StdA-SSRX+6
GND-DRAIN7
StdA-SSTX-8
StdA-SSTX+9
GND10
GND11
GND12
GND13
DI5
AZC199-02SPR7G_SOT23-3
EMC@DI5
AZC199-02SPR7G_SOT23-3
EMC@22
33
11
CI1
7
0.1
U_
04
02
_2
5V
6K
~D
CI1
7
0.1
U_
04
02
_2
5V
6K
~D
1
2
8
7
65
4
3
2
1
9
10
DI4
L05ESDL5V0NA-4_SLP2510P8-10-9
EMC@
8
7
65
4
3
2
1
9
10
DI4
L05ESDL5V0NA-4_SLP2510P8-10-9
EMC@
4
5
1
6
2
7
3
9
8
LI6
DLW21HN900HQ2L_4P
EMC@LI6
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
CI1
41
00
U_
12
06
_6
.3V
6M
CI1
41
00
U_
12
06
_6
.3V
6M
12
LI5
DLW21HN900HQ2L_4P
EMC@LI5
DLW21HN900HQ2L_4P
EMC@
11
44
33
22
CI6
10
U_
06
03
_6
.3V
6M
@C
I61
0U
_0
60
3_
6.3
V6
M@1
2
CI16 0.1U_0402_10V7KCI16 0.1U_0402_10V7K12
UI1
SY6288D10CAC_MSOP8
UI1
SY6288D10CAC_MSOP8
GND1
VIN2
VIN3
EN4
FLG5VOUT6VOUT7VOUT8
CI13 0.1U_0402_10V7KCI13 0.1U_0402_10V7K12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
NFC on USH/B
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
NFC
33 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
NFC
33 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
NFC
33 48Wednesday, March 19, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
DOCK_DET_1
Close to DOCKIts for Enhance ESD ondock issue.
Close to DOCKIts for Enhance ESD on dockissue.
EMI solution for E-Docking USB
EMI depop location
20130730 SP0300017A0 CIS Link OK
BLUE_DOCK
DOCK_AC_OFF
DOCK_DET#
DOCK_DET_R#
DPB_CA_DET
DPB_DOCK_AUXDPB_DOCK_AUX#
DPB_DOCK_HPD
DPB_DOCK_HPD
DPB_DOCK_LANE_N0
DPB_DOCK_LANE_N1
DPB_DOCK_LANE_N2
DPB_DOCK_LANE_N3
DPB_DOCK_LANE_P0
DPB_DOCK_LANE_P1
DPB_DOCK_LANE_P2
DPB_DOCK_LANE_P3
DPB_LANE_N0_C
DPB_LANE_N1_C
DPB_LANE_N2_C
DPB_LANE_N3_C
DPB_LANE_P0_C
DPB_LANE_P1_C
DPB_LANE_P2_C
DPB_LANE_P3_C
DPC_CA_DET
DPC_DOCK_AUXDPC_DOCK_AUX#
DPC_DOCK_HPD
DPC_DOCK_HPD
DPC_DOCK_LANE_N0
DPC_DOCK_LANE_N1
DPC_DOCK_LANE_N2
DPC_DOCK_LANE_N3
DPC_DOCK_LANE_P0
DPC_DOCK_LANE_P1
DPC_DOCK_LANE_P2
DPC_DOCK_LANE_P3
DPC_LANE_N0_C
DPC_LANE_N1_C
DPC_LANE_N2_C
DPC_LANE_N3_C
DPC_LANE_P0_C
DPC_LANE_P1_C
DPC_LANE_P2_C
DPC_LANE_P3_C
GREEN_DOCK
RED_DOCKSATA_PRX_DKTX_N0SATA_PRX_DKTX_P0
SATA_PTX_DKRX_N0SATA_PTX_DKRX_P0
CLK_PCI_DOCKDAI_12MHZ# DAI_BCLK#
SLICE_BAT_PRES#_R
+DOCK_PWR_BAR +DOCK_PWR_BAR
+LOM_VCT
+NBDOCK_DC_IN_SS
+3.3V_ALW2+LOM_VCT
DOCK_AC_OFF <47>
RED_DOCK<22>
BLUE_DOCK<22>
GREEN_DOCK<22>
VSYNC_DOCK<22>
DAT_MSE<36>CLK_MSE<36>
DAI_BCLK#<21>DAI_LRCK#<21>
DAI_DI<21>DAI_DO#<21>
DAI_12MHZ#<21>
D_LAD1<35>D_LAD0<35>
D_LAD2<35>D_LAD3<35>
D_LFRAME#<35>D_CLKRUN#<35>
D_SERIRQ<35>D_DLDRQ1#<35>
CLK_PCI_DOCK<7>
DOCK_SMB_CLK<36>DOCK_SMB_DAT<36>
DOCK_SMB_ALERT#<35,40>DOCK_PSID<40>
DOCK_PWR_BTN#<36>
DOCK_LOM_SPD10LED_GRN#<28>
HSYNC_DOCK<22>
DOCK_LOM_SPD100LED_ORG# <28>
DAT_KBD <36>CLK_KBD <36>
DOCK_LOM_TRD0+ <28>DOCK_LOM_TRD0- <28>
DOCK_LOM_TRD2- <28>DOCK_LOM_TRD2+ <28>
ACAV_DOCK_SRC# <47>
CLK_DDC2_DOCK <22>DAT_DDC2_DOCK <22>
SATA_PTX_DKRX_P0_C <6>SATA_PTX_DKRX_N0_C <6>
SATA_PRX_DKTX_P0_C <6>
BREATH_LED# <36,39>DOCK_LOM_ACTLED_YEL# <28>
DOCK_LOM_TRD1- <28>DOCK_LOM_TRD1+ <28>
DOCK_LOM_TRD3- <28>DOCK_LOM_TRD3+ <28>
DOCK_DCIN_IS+ <46>DOCK_DCIN_IS- <46>
DOCK_POR_RST# <36>
SATA_PRX_DKTX_N0_C <6>
DOCK_USBP0+ <31>DOCK_USBP0- <31>
DOCK_DET# <35,47>
DPB_DOCK_AUX <26>DPB_DOCK_AUX# <26>
DPB_CA_DET <22,26>DPC_CA_DET<22,26>
DPC_DOCK_AUX#<26>DPC_DOCK_AUX<26>
DPC_DOCK_HPD<22> DPB_DOCK_HPD <22>
DOCK_USB3RN1 <31>DOCK_USB3RP1 <31>
DOCK_USB3TN1 <31>DOCK_USB3TP1 <31>
DPC_LANE_P0<22>DPC_LANE_N0<22>
DPC_LANE_P1<22>DPC_LANE_N1<22>
DPC_LANE_P2<22>DPC_LANE_N2<22>
DPC_LANE_P3<22>DPC_LANE_N3<22>
DPB_LANE_P2 <22>DPB_LANE_N2 <22>
DPB_LANE_P0 <22>DPB_LANE_N0 <22>
DPB_LANE_P3 <22>DPB_LANE_N3 <22>
DPB_LANE_P1 <22>DPB_LANE_N1 <22>
DOCK_USBP3- <31>DOCK_USBP3+ <31>
SLICE_BAT_PRES#<35,40,47>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
E-Dock
34 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
E-Dock
34 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
E-Dock
34 48Wednesday, March 19, 2014
Compal Electronics, Inc.
C309 0.1U_0402_10V7KC309 0.1U_0402_10V7K12
C4
3E
MC
@4
.7P
_0
40
2_
50
V8
CC
43
EM
C@
4.7
P_
04
02
_5
0V
8C
12
C297 0.1U_0402_10V7KC297 0.1U_0402_10V7K12
C314 0.01U_0402_16V7KC314 0.01U_0402_16V7K1 2
R257 33_0402_5%EMC@ R257 33_0402_5%EMC@ 1 2
C294 0.1U_0402_10V7KC294 0.1U_0402_10V7K12
C307 0.1U_0402_10V7KC307 0.1U_0402_10V7K12C305 0.1U_0402_10V7KC305 0.1U_0402_10V7K12
C3
18
0.1
U_
06
03
_5
0V
7K
C3
18
0.1
U_
06
03
_5
0V
7K
12
R264 33_0402_5%EMC@ R264 33_0402_5%EMC@ 1 2C306 0.1U_0402_10V7KC306 0.1U_0402_10V7K12
C312 0.01U_0402_16V7KC312 0.01U_0402_16V7K12
R6
10
_0
40
2_
5%
EM
C@
R6
10
_0
40
2_
5%
EM
C@
12
R265 33_0402_5%EMC@ R265 33_0402_5%EMC@ 1 2
C3
19
EM
C@
4.7
P_
04
02
_5
0V
8C
C3
19
EM
C@
4.7
P_
04
02
_5
0V
8C
12
R261 33_0402_5%EMC@ R261 33_0402_5%EMC@ 1 2
R255 33_0402_5%EMC@ R255 33_0402_5%EMC@ 1 2
R267 33_0402_5%EMC@ R267 33_0402_5%EMC@ 1 2
R256 33_0402_5%EMC@ R256 33_0402_5%EMC@ 1 2 C303 0.1U_0402_10V7KC303 0.1U_0402_10V7K12
C301 0.1U_0402_10V7KC301 0.1U_0402_10V7K12C308 0.1U_0402_10V7KC308 0.1U_0402_10V7K12C300 0.1U_0402_10V7KC300 0.1U_0402_10V7K12
C313 0.01U_0402_16V7KC313 0.01U_0402_16V7K12
WD2F144WB8
JDOCK1
CONN@
JAE_WD2F144WB8R500-DTWD2F144WB8
JDOCK1
CONN@
JAE_WD2F144WB8R500-DT
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
4141
4343
4545
4747
4949
5151
5353
5555
5757
5959
6161
6363
6565
6767
6969
7171
7373
7575
7777
7979
8181
8383
8585
8787
8989
9191
9393
9595
9797
9999
101101
103103
105105
107107
109109
111111
113113
115115
117117
119119
121121
123123
125125
127127
129129
131131
133133
135135
137137
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
4242
4444
4646
4848
5050
5252
5454
5656
5858
6060
6262
6464
6666
6868
7070
7272
7474
7676
7878
8080
8282
8484
8686
8888
9090
9292
9494
9696
9898
100100
102102
104104
106106
108108
110110
112112
114114
116116
118118
120120
122122
124124
126126
128128
130130
132132
134134
136136
138138
GND1145
PWR1146
PWR2149
Shield_G152
Shield_G153
Shield_G154
Shield_G155
Shield_G156
Shield_G158
139139
140140
141141
142142
143143
144144
PWR1147
GND2148
PWR2150
Shield_G151
Shield_G159
Shield_G160
Shield_G161
Shield_G162
Shield_G157
C3
3@
4.7
U_
08
05
_2
5V
6-K
C3
3@
4.7
U_
08
05
_2
5V
6-K
12
C295 0.1U_0402_10V7KC295 0.1U_0402_10V7K12
C3
16
@1
U_
04
02
_6
.3V
6K
C3
16
@1
U_
04
02
_6
.3V
6K
12
R263 33_0402_5%EMC@ R263 33_0402_5%EMC@ 1 2
C315 0.01U_0402_16V7KC315 0.01U_0402_16V7K1 2
R4
11
0_
04
02
_5
%
EM
C@
R4
11
0_
04
02
_5
%
EM
C@
12
R259 33_0402_5%EMC@ R259 33_0402_5%EMC@ 1 2
R2
68
10
0K
_0
40
2_
5%
R2
68
10
0K
_0
40
2_
5%
12
R266 33_0402_5%EMC@ R266 33_0402_5%EMC@ 1 2
C302 0.1U_0402_10V7KC302 0.1U_0402_10V7K12
C3
11
@
0.0
33
U_
04
02
_1
6V
7K
C3
11
@
0.0
33
U_
04
02
_1
6V
7K
12
C299 0.1U_0402_10V7KC299 0.1U_0402_10V7K12
C296 0.1U_0402_10V7KC296 0.1U_0402_10V7K12
C3
17
0.1
U_
06
03
_5
0V
7K
C3
17
0.1
U_
06
03
_5
0V
7K
12
R262 33_0402_5%EMC@ R262 33_0402_5%EMC@ 1 2
C3
10
@0
.03
3U
_0
40
2_
16
V7
KC
31
0@
0.0
33
U_
04
02
_1
6V
7K
12
D19
RB751S40T1G_SOD523-2
D19
RB751S40T1G_SOD523-2
1 2
R254 33_0402_5%EMC@ R254 33_0402_5%EMC@ 1 2
R260 33_0402_5%EMC@ R260 33_0402_5%EMC@ 1 2
C4
2E
MC
@4
.7P
_0
40
2_
50
V8
CC
42
EM
C@
4.7
P_
04
02
_5
0V
8C
12
R253 33_0402_5%EMC@ R253 33_0402_5%EMC@ 1 2
R258 33_0402_5%EMC@ R258 33_0402_5%EMC@ 1 2
R2
73
10
_0
40
2_
5%
EM
C@
R2
73
10
_0
40
2_
5%
EM
C@
12
R2
71
10
0K
_0
40
2_
5%
R2
71
10
0K
_0
40
2_
5%
12
R272100K_0402_5% R272100K_0402_5%1 2
R252 33_0402_5%EMC@ R252 33_0402_5%EMC@ 1 2
C298 0.1U_0402_10V7KC298 0.1U_0402_10V7K12
D2
0@
L3
0E
SD
24
VC
3-2
_S
OT
23
-3D
20
@L
30
ES
D2
4V
C3
-2_
SO
T2
3-3
123
C304 0.1U_0402_10V7KC304 0.1U_0402_10V7K12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+CAP_LDO trace width 20 mils
EMI depop location
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
EXPRESS_DET# for 15U no dock only
1UMA
Discrete
VGA_ID0
0
Stuff RE275 and no stuff RE274 keep E5 designStuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
+CAP_LDO
AUD_HP_NB_SENSE
AUD_NB_MUTE#
AUX_EN_WOWL
BC_CLK_ECE5048BC_DAT_ECE5048BC_INT#_ECE5048
BT_RADIO_DIS#
CLKRUN#
CLK_PCI_SIO
CLK_PCI_SIO
DOCKED
DOCK_AC_OFF_EC
DOCK_DET#
DOCK_HP_DETDOCK_MIC_DET
DOCK_SMB_ALERT#
EC5048_TX
EN_DOCK_PWR_BAR
EN_I2S_NB_CODEC#
USB_PWR_EN1#
GPIO_PSID_SELECT
IRQ_SERIRQ
LCD_TST
LCD_VCC_TEST_EN
LED_SATA_DIAG_OUT#
LID_CL_SIO#
LID_CL_SIO#
LPC_LAD0LPC_LAD1LPC_LAD2LPC_LAD3LPC_LFRAME#
MASK_SATA_LED#
EXPRESS_DET#
PCH_PLTRST#_EC
PSID_DISABLE#
RUNPWROK
SLICE_BAT_ON
SLICE_BAT_ON
SLICE_BAT_PRES#
SLICE_BAT_PRES#
SYS_LED_MASK#
SYS_LED_MASK#
TOUCH_SCREEN_PD#
PCIE_WAKE#_R
USB_PWR_EN2#
USH_PWR_STATE#
WIRELESS_LED#
NGFF_CONFIG_0
D_CLKRUN#D_DLDRQ1#D_SERIRQ
D_DLDRQ1#D_SERIRQD_CLKRUN#
D_LAD0D_LAD1D_LAD2D_LAD3D_LFRAME#
SMART_DET#
WLAN_WIGIG60GHZ_DIS#
USB_DB_DET#
NGFF_CONFIG_1NGFF_CONFIG_2
NGFF_CONFIG_3
WWAN_RADIO_DIS#
WWAN_RADIO_DIS#
NGFF_CONFIG_0NGFF_CONFIG_1NGFF_CONFIG_2NGFF_CONFIG_3
USB_PWR_SHR_VBUS_ENUSB_PWR_EN1#
DOCK_SMB_ALERT#
WLAN_WIGIG60GHZ_DIS#
BT_RADIO_DIS#
USB_PWR_EN2#
HW_GPS_DISABLE2#HW_GPS_DISABLE2#
PROCHOT_GATE
PROCHOT_GATE
VGA_ID
VGA_ID
VGA_ID
DIS_BAT_PROCHOT#
LPC_LDRQ1#
LPC_LDRQ1#
LCD_TST
PCIE_WAKE#_R
PCIE_WAKE#_R
WWAN_WAKE#
WWAN_WAKE#
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
+3.3V_ALW +3.3V_ALW_UE1
+3.3V_ALW
+3.3V_ALW
LPC_LFRAME# <20,36,7>
SYS_LED_MASK#<28,39>
LID_CL# <30,39>
CLK_PCI_SIO <7>PCH_PLTRST#_EC <20,27,30,36,9>
IRQ_SERIRQ <10,12,36>
CLKRUN# <10,36,9>
BC_CLK_ECE5048 <36>
BC_INT#_ECE5048 <36>BC_DAT_ECE5048 <36>
PSID_DISABLE#<40>
LCD_TST<23>
USH_PWR_STATE#<27>
AUD_NB_MUTE#<21>
LCD_VCC_TEST_EN<23>
AUD_HP_NB_SENSE<21>
EC_32KHZ_MEC5085 <30,36>
WIRELESS_LED#<30,39>
MASK_SATA_LED# <39>
LED_SATA_DIAG_OUT# <39>
RUNPWROK <36,9>
LPC_LAD0 <20,36,7>LPC_LAD1 <20,36,7>LPC_LAD2 <20,36,7>LPC_LAD3 <20,36,7>
USB_PWR_SHR_VBUS_EN<31>
SIO_SLP_WLAN#<9>
USB_PWR_EN2#<31>
USB_PWR_EN1#<32>
BT_RADIO_DIS#<30>
EN_I2S_NB_CODEC#<21>
EC5048_TX<36>
AUX_EN_WOWL <30>
NGFF_CONFIG_0 <30>
DOCK_AC_OFF_EC <47>
GPIO_PSID_SELECT <40>
DOCK_HP_DET <21>DOCK_MIC_DET <21>
D_LFRAME# <34>
D_LAD0 <34>D_LAD1 <34>D_LAD2 <34>D_LAD3 <34>
D_CLKRUN# <34>D_DLDRQ1# <34>D_SERIRQ <34>
DOCK_DET#<34,47>DOCKED<22,28,31>
DOCKED_LIO_EN<31>
DOCK_SMB_ALERT#<34,40>
EN_DOCK_PWR_BAR<47>
SLICE_BAT_ON<47>SLICE_BAT_PRES#<34,40,47>
WLAN_WIGIG60GHZ_DIS#<30>
SATA2_PCIE6_L1 <12,6>
NGFF_CONFIG_1 <30>NGFF_CONFIG_2 <30>
NGFF_CONFIG_3 <30>
WWAN_RADIO_DIS#<30>
LAN_DISABLE#_R<28>
3.3V_WWAN_EN<30>
HW_GPS_DISABLE2#<30>
BCM5882_ALERT#<27>
WLAN_LAN_DISBL# <28>
PANEL_BKEN_EC<23>
DIS_BAT_PROCHOT# <47>
PCH_PCIE_WAKE# <36,9>
PCIE_WAKE# <30>
USB_PWR_SHR_EN# <31,36>
WWAN_WAKE#<30>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
ECE5048
35 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
ECE5048
35 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
ECE5048
35 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RE85100K_0402_5%@ RE85100K_0402_5%@1 2
CE
60
.1U
_0
40
2_
25
V6
CE
60
.1U
_0
40
2_
25
V6
12
RE
27
@E
MC
@3
3_
04
02
_5
%R
E2
7@
EM
C@
33
_0
40
2_
5%
12
PJP14
PAD-OPEN1x1m
@ PJP14
PAD-OPEN1x1m
@
1 2
T97@ PAD~DT97@ PAD~D
CE
80
.04
7U
_0
40
2_
16
V4
ZC
E8
0.0
47
U_
04
02
_1
6V
4Z
12
RE83 100K_0402_5%@ RE83 100K_0402_5%@1 2
RE21 10K_0402_5%RE21 10K_0402_5%1 2
RE24 10K_0402_5%RE24 10K_0402_5%1 2
RE20 100K_0402_5%RE20 100K_0402_5%1 2
RPE4
100K_0804_8P4R_5%
RPE4
100K_0804_8P4R_5%
12345
678
RE27610K_0402_5% RE27610K_0402_5%12
T96@ PAD~DT96@ PAD~D
RPE8
100K_0804_8P4R_5%
RPE8
100K_0804_8P4R_5%
1234 5
678RE9 100K_0402_5%RE9 100K_0402_5%
1 2
RE275 0_0402_5%@RE275 0_0402_5%@1 2
T98@ PAD~DT98@ PAD~D
RE11 100K_0402_5%RE11 100K_0402_5%1 2
RE5 100K_0402_5%RE5 100K_0402_5%1 2
CE
30
.1U
_0
40
2_
25
V6
CE
30
.1U
_0
40
2_
25
V6
12
RPE9
100K_0804_8P4R_5%
RPE9
100K_0804_8P4R_5%
12345
678
UE1
DB Version 0.4ECE5048-LZY_DQFN132_11X11~D
UE1
DB Version 0.4ECE5048-LZY_DQFN132_11X11~D
GPIOA0B52
GPIOA1A49
GPIOA2B53
GPIOA3A50
GPIOA4B54
GPIOA5A51
GPIOA6B55
GPIOA7A52
GPIOD1B32
GPIOD2A31
GPIOD3B33
GPIOD4B15
GPIOD5A15
GPIOD6B16
GPIOD7A16
GPIOF7B58 GPIOF6A55 GPIOF5B59 GPIOF4/TACH7A56
GPIOL0/PWM7B60
GPIOL1/PWM8A57
GPIOF3/TACH8B61 GPIOF2A58 GPIOF1B62 GPIOF0A59
VC
C1
B5
CAP_LDOB46
TEST_PINB19
LAD0A27
LAD1A26
LAD2B26
LAD3B25
LFRAME#A21
LRESET#B22
PCICLKA28
CLKRUN#B20
GPIOI0A23
LDRQ1#A22
SER_IRQB21
14.318MHZ/GPIOM0A32
GPIOM4/PWM6B51
DLAD0B29
DLAD1B28
DLAD2A25
DLAD3A24
DLFRAME#B23
DCLKRUN#A19
DLDRQ1#B24
DSER_IRQA20
PWRGDA4
OUT65B56
VSSB27
GPIOM3/PWM4B39
GPIOL2/PWM0B64
VC
C1
A1
7
VC
C1
B3
0
VC
C1
A4
3
VC
C1
A5
4
BC_INT#A29
BC_DATB31
BC_CLKA30
GPIOB0A33
GPIOB1B36
GPOC2A34
GPOC3B37
GPOC4A35
GPOC5B38
GPOC6/TACH4A36
GPIOC7A37
GPIOD0B40
GPIOC1A38
GPIOC0B41
GPIOB7A39
GPIOB6B42
GPIOB5A40
GPIOB4B43
GPIOB3A41
GPIOB2B44
GPIOH0B13
GPIOH1A13
SYSOPT1/GPIOH2A53
SYSOPT0/GPIOH3B57
GPIOH4B14
GPIOH5A14
GPIOH6B17
GPIOH7B18
GPIOE0/RXDA1
GPIOE1/TXDB2
GPIOE2/RTS#A2
GPIOE3/DSR#B3
GPIOE4/CTS#A3
GPIOE5/DTR#B45
GPIOE6/RI#A42
GPIOE7/DCD#B4
GPIOG0/TACH5B47
GPIOG1A45
GPIOG2B48
GPIOG3A46
GPIOG4B49
GPIOG5A47
GPIOG6B50
GPIOG7/TACH6A48
GPIOK0A8
GPIOK1/TACH3B9
GPIOK2B10
GPIOK3A10
GPIOK4B11
GPIOK5A11
GPIOK6B12
GPIOK7A12
GPIOI1B63
GPIOI2/TACH0A60
GPIOI3A61
GPIOI4B65
GPIOI5A62
GPIOI6B66
GPIOI7A63
GPIOJ0B67
GPIOJ1/TACH1A64
GPIOJ2/TACH2A5
GPIOJ3B6
GPIOJ4A6
GPIOJ5B7
GPIOJ6A7
GPIOJ7B8
GPIOM1B34
CLK32/GPIOM2B35
EPC1
GPIOL3/PWM1B68
GPIOL4/PWM3A9
GPIOL5/PWM2B1
GPIOL6A18
GPIOL7/PWM5A44
RE12 100K_0402_5%RE12 100K_0402_5%1 2
CE
40
.1U
_0
40
2_
10
V7
KC
E4
0.1
U_
04
02
_1
0V
7K
12
RE3510K_0402_5% RE3510K_0402_5%12
RE17 100K_0402_5%RE17 100K_0402_5%12
RE8 100K_0402_5%RE8 100K_0402_5%1 2
RE
25
10
0K
_0
40
2_
5%
RE
25
10
0K
_0
40
2_
5%
12
CE
11
0U
_0
60
3_
6.3
V6
MC
E1
10
U_
06
03
_6
.3V
6M
12
CE
50
.1U
_0
40
2_
25
V6
CE
50
.1U
_0
40
2_
25
V6
12
CE
20
.1U
_0
40
2_
25
V6
CE
20
.1U
_0
40
2_
25
V6
12
CE
74
.7U
_0
60
3_
6.3
V6
KC
E7
4.7
U_
06
03
_6
.3V
6K
12
RE10 100K_0402_5%RE10 100K_0402_5%1 2
T99@ PAD~DT99@ PAD~D
RE26 10_0402_5%RE26 10_0402_5%12
RE87100K_0402_5% RE87100K_0402_5%1 2
RE2740_0402_5% @ RE2740_0402_5% @1 2
CE
9@
EM
C@
33
P_
04
02
_5
0V
8J
CE
9@
EM
C@
33
P_
04
02
_5
0V
8J
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1K4700p4700p
X02X01X00
33K
RE79 CE40
130K 4700p
REV
240K 4700p*
BOARD_ID rise time is measured from 5%~68%.
A00
15mil
Place close pin A29
32 KHz Clock
CE24, CE26, CE27 Place near UE2
ESR <2ohms
Pin8 5075_TXD for EC Debug
pin9 5048_TXD for SBIOS
debug
EMI depop location
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
for no-dock : A21 use LID_CL_SIO#
for no-dock : A38 use LCD_TST
for no-dock : A39 use SLP_ME_CSW_DEV#
for no-dock : A43 use BC_CLK_ECE1099
for no-dock : B45 use BC_DAT_ECE1099
for no-dock : A42 use BC_INT#_ECE1099
for no-dock : B2 use Free
for no-dock : B41 use Free
for no-dock :B42 use Free
trace width 20 milstrace width 20 mils
DN2a/DP2a WiGig
Thermistor Readings
Diode Readings
HIGH
LOW
Channel 1
Thermal Monitoring Interface Strap Option
Rest=1.58K , Tp=96 degree
V.R
DP1/DN1
DP2/DN2
DP4/DN4
Location
CPU
DIMM
Thermal diode mapping
5085 Channel
Place under CPU
Place CE35 close to the QE3 as possible
DP2/DN2 for SODIMM on QE5, place QE5 close
to SODIMM and CE37 close to QE5
DP4/DN4 for Skin on QE6, place QE6 close to Vcore VR choke.
Setting for Thermal Design
reserve for DC fanDP3/DN3 VGA
20130730 same as Goliad
Close to UE2 at least 250mils
DN2a/DP2a for WiGig on QE7, place QE7 close
to WiGig/WLAN and CE46 close to QE7
+RTC_CELL_VBAT
+V
R_C
AP
AC_PRESENT
ALW_PWRGD_3V_5V_EC
BC_CLK_ECE1117
BC_CLK_ECE5048
BC_DAT_ECE1117
BC_DAT_ECE5048
BC_DAT_ECE5048
BC_INT#_ECE1117
BC_INT#_ECE5048
BIA_PWM_EC
BOARD_ID
BOARD_ID
CHARGER_SMBCLK
CHARGER_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBDATCLKRUN#
CLK_PCI_MEC
CLK_PCI_MEC
CLK_TP_SIODAT_TP_SIO BAT1_LED#
DOCK_SMB_CLKDOCK_SMB_DAT
SIO_SLP_S3#
EN_INVPWR
EN_INVPWR
FAN1_PWM
FAN1_PWM
FAN1_TACH
FAN1_TACH
FWP#
FWP#
GPU_SMBCLKGPU_SMBDAT
ME_FWP_EC
HOST_DEBUG_TX
HOST_DEBUG_TX
IRQ_SERIRQ
JTAG_CLK
JTAG_CLK
JTAG_RST#
JTAG_RST#
JTAG_TDI
JTAG_TDI
JTAG_TDO
JTAG_TDO
JTAG_TMS
JTAG_TMS
LAN_WAKE#
LPC_LAD0LPC_LAD1LPC_LAD2LPC_LAD3
LPC_LFRAME#
MEC_XTAL1
MEC_XTAL1
MEC_XTAL2
MEC_XTAL2 MEC_XTAL2_R
MSCLK
MSCLK
MSDATA
MSDATA
PBAT_SMBCLK
PBAT_SMBCLK
PBAT_SMBDAT
PBAT_SMBDAT
PCH_PCIE_WAKE#
PCH_PLTRST#_EC
PM_APWROK
POA_WAKE#
POWER_SW_IN#
H_PROCHOT#
BAT2_LED#
REM_DIODE1_NREM_DIODE1_PREM_DIODE2_NREM_DIODE2_P
REM_DIODE4_NREM_DIODE4_P
RESET_OUT#
RESET_OUT#
RUNPWROK
RUNPWROK
RUN_ON#
SIO_EXT_SCI#
SIO_EXT_SMI#
SIO_PWRBTN#
SIO_RCIN#
PCH_DPWROK
SIO_SLP_S5#
SML1_SMBCLKSML1_SMBDATA
THERMATRIP2#THERMATRIP3#THSEL_STRAP
USH_SMBCLKUSH_SMBDAT
VCI_IN2#
VSET_5085
PCH_RSMRST#
PECI_EC_RPECI_EC_R
POA_WAKE#
POWER_SW_IN#
VCI_IN2#DOCK_PWR_SW#
ACAV_INALWON
+PECI_VREF
GPU_SMBCLKGPU_SMBDAT
DOCK_PWR_SW#
PCH_ALW_ON
A_ON
BEEP
PCH_ALW_ONA_ON
RUN_ON
THERMATRIP3#
FAN1_PWMFAN1_TACH
REM_DIODE1_N
REM_DIODE1_P
REM_DIODE2_N
REM_DIODE2_P
REM_DIODE4_N
REM_DIODE4_P
THERMATRIP2#
THSEL_STRAPVSET_5085
BC_DAT_ECE1117
MSDATA
CLK_KBD
CLK_MSEDAT_KBD
DAT_MSE
CLK_KBD
CLK_MSEDAT_KBD
DAT_MSE
DOCK_POR_RST#
DOCK_SMB_CLKDOCK_SMB_DAT
SUS_ON_ECSUS_ON
SUS_ON_EC
SIO_SLP_S4#
SIO_SLP_S3#
RUN_ON_EC
RUN_ON_EC
LPC_LAD0
PCH_PLTRST#_ECLPC_LFRAME#
LPC_LAD3LPC_LAD2LPC_LAD1
PCH_RSMRST#
ALW_PWRGD_3V_5V_EC
+3.3V_ALW
+3.3V_ALW
+RTC_CELL
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+1.05V_RUN
+RTC_CELL
+3.3V_RUN
+3.3V_ALW
+3.3V_ALW2
+3.3V_RUN
+3.3V_ALW
+RTC_CELL
+3.3V_ALW
+3.3V_ALW_UE2
+3.3V_ALW_UE2
+3.3V_ALW +3.3V_ALW_UE2
+3.3V_RUN
+RTC_CELL
+1.05V_RUN
+3.3V_ALW
+5V_RUN
+3.3V_ALW
+5V_RUN
+3.3V_RUN
POWER_SW#_MB <39,9>
H_PROCHOT# <45,46,9>
LPC_LAD1<20,35,7>LPC_LAD2<20,35,7>LPC_LAD3<20,35,7>
LPC_LAD0<20,35,7>
SIO_EXT_SCI#<12>CLKRUN#<10,35,9>
AC_PRESENT <9>
SML1_SMBDATA<7>SML1_SMBCLK<7>
BAT2_LED# <39>
SIO_PWRBTN# <9>
PCH_PCIE_WAKE# <35,9>
ME_SUS_PWR_ACK <9>
PM_APWROK <9>
BC_CLK_ECE1117<37>BC_DAT_ECE1117<37>
BC_INT#_ECE1117<37>
RESET_OUT# <15,9>
BIA_PWM_EC<23>
SIO_EXT_SMI#<12>
PBAT_SMBDAT<40>PBAT_SMBCLK<40>
SIO_RCIN#<10,12>
RUNPWROK <35,9>
IRQ_SERIRQ<10,12,35>
EN_INVPWR <23>
PCH_PLTRST#_EC<20,27,30,35,9>
CHARGER_SMBCLK <46>CHARGER_SMBDAT <46>
CLK_PCI_MEC<7>
BC_DAT_ECE5048<35>BC_INT#_ECE5048<35>
BC_CLK_ECE5048<35>
LPC_LFRAME#<20,35,7>
USH_SMBDAT <27>USH_SMBCLK <27>
I_BATT <46>
SIO_SLP_S5#<9>
CLK_TP_SIO<37>DAT_TP_SIO<37>
RUN_ON<36,38>
EC5048_TX <35>
I_ADP <46>
LAN_WAKE# <12,28>
USB_PWR_SHR_EN# <31,35>
AC_DIS <40,47>
DOCK_POR_RST#<34> DOCK_SMB_CLK <34>DOCK_SMB_DAT <34>
PCH_DPWROK <9>
PCH_RSMRST# <37>
PECI_EC <9>
PBAT_PRES# <40,46,47>
I_SYS <46>
ALWON <41>ACAV_IN <46,47>
BAT1_LED# <39>
EC_32KHZ_MEC5085 <30,35>
ACAV_IN_NB<46,47>
SIO_EXT_WAKE# <12>
SIO_SLP_SUS# <9>
BREATH_LED# <34,39>
SYS_PWROK <9>ENVDD_PCH <10,23>
mCARD_PCIE#_SATA <6,7>
DOCK_PWR_BTN# <34>
PS_ID<40>SUSACK#<9>
PCH_ALW_ON <38>
A_ON <28,38>
BEEP<21>
SIO_SLP_A# <9>
SIO_SLP_S4# <9>SIO_SLP_LAN# <28,9>
SIO_SLP_S3# <9>
ME_FWP_EC <6>
H_THERMTRIP#<12>
CLK_KBD<34>
CLK_MSE<34>DAT_KBD<34>
DAT_MSE<34>
SUS_ON <38,42>
RUN_ON <36,38>
CLK_PCI_LPDEBUG <20,7>
ALW_PWRGD_3V_5V <37,41>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
MEC5085
36 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
MEC5085
36 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
MEC5085
36 48Wednesday, March 19, 2014
Compal Electronics, Inc.
RE60 43_0402_5%RE60 43_0402_5%1 2
JTA
G1
CO
NN
@@
SH
OR
T P
AD
S~
DJT
AG
1C
ON
N@
@S
HO
RT
PA
DS
~D
11
22
CE27 2200P_0402_50V7KCE27 2200P_0402_50V7K1 2
CE10@
1U_0402_6.3V6K
CE10@
1U_0402_6.3V6K
1 2
RPE5
100K_0804_8P4R_5%
RPE5
100K_0804_8P4R_5%
1234 5
678
CE
23
0.1
U_
04
02
_2
5V
6C
E2
30
.1U
_0
40
2_
25
V6
12
YE132.768KHZ_12.5PF_Q13FC135000040
YE132.768KHZ_12.5PF_Q13FC135000040
1 2
CE26 2200P_0402_50V7KCE26 2200P_0402_50V7K1 2
CE
14
1U
_0402_6.3
V6K
CE
14
1U
_0402_6.3
V6K
1
2
CE
35
@1
00
P_
04
02
_5
0V
8J
CE
35
@1
00
P_
04
02
_5
0V
8J
12
RE70 2.2K_0402_5%RE70 2.2K_0402_5%1 2
RE64 4.7K_0402_5%RE64 4.7K_0402_5%1 2
CE
11
0.1
U_
04
02
_2
5V
6C
E1
10
.1U
_0
40
2_
25
V6
12
CE
17
0.1
U_
04
02
_2
5V
6C
E1
70
.1U
_0
40
2_
25
V6
12
RE
58
10
0K
_0
40
2_
5%
RE
58
10
0K
_0
40
2_
5%
12
RE78 1K_0402_5%RE78 1K_0402_5%1 2
RE
74
10
K_
04
02
_5
%R
E7
41
0K
_0
40
2_
5%
12
RE
67
10
K_
04
02
_5
%R
E6
71
0K
_0
40
2_
5%
12
RE51 10K_0402_5%RE51 10K_0402_5%1 2
EB
C
QE6MMBT3904WT1G_SC70-3~D
EB
C
QE6MMBT3904WT1G_SC70-3~D
2
31
PJP15
PAD-OPEN1x1m
@ PJP15
PAD-OPEN1x1m
@
1 2
RPE10
100K_0804_8P4R_5%
RPE10
100K_0804_8P4R_5%
12345
678
RE
65
@1
00
_0
40
2_
1%
RE
65
@1
00
_0
40
2_
1%
12
CE
38
0.1
U_
04
02
_2
5V
6C
E3
80
.1U
_0
40
2_
25
V6
12
RE277 100K_0402_5%RE277 100K_0402_5%1 2
EB
C
QE5MMBT3904WT1G_SC70-3~D
EB
C
QE5MMBT3904WT1G_SC70-3~D
2
31
RE
68
10
0K
_0
40
2_
5%
RE
68
10
0K
_0
40
2_
5%
12
RE
81
10
K_
04
02
_5
%R
E8
11
0K
_0
40
2_
5%
12
CE
46
@1
00
P_
04
02
_5
0V
8J
CE
46
@1
00
P_
04
02
_5
0V
8J
12
CE
18
0.1
U_
04
02
_2
5V
6C
E1
80
.1U
_0
40
2_
25
V6
12
CE
32
10
U_
06
03
_6
.3V
6M
CE
32
10
U_
06
03
_6
.3V
6M
12
RE
72
10
K_
04
02
_5
%R
E7
21
0K
_0
40
2_
5%
12
JDEG1
ACES_50521-01041-P01
CONN@
JDEG1
ACES_50521-01041-P01
CONN@
44332211
6655
GND111
GND212
77
88
99
1010
CE44@
1U_0402_6.3V6K
CE44@
1U_0402_6.3V6K
1 2
RE48 10K_0402_5%RE48 10K_0402_5%1 2
RE
79
130K
_0402_5%
RE
79
130K
_0402_5%
12
RE
69
8.2
K_
04
02
_5
%R
E6
98
.2K
_0
40
2_
5%
12
CE
19
0.1
U_
04
02
_2
5V
6C
E1
90
.1U
_0
40
2_
25
V6
12
RE32@ 0_0402_5%RE32@ 0_0402_5%1 2
RE
73
10
K_
04
02
_5
%R
E7
31
0K
_0
40
2_
5%
12
CE24 2200P_0402_50V7KCE24 2200P_0402_50V7K1 2
CE
22
0.1
U_
04
02
_2
5V
6C
E2
20
.1U
_0
40
2_
25
V6
12
CE
39
@1
00
P_
04
02
_5
0V
8J
CE
39
@1
00
P_
04
02
_5
0V
8J
12
CE
16
@
0.1
U_
04
02
_2
5V
6C
E1
6@
0.1
U_
04
02
_2
5V
6
12
RE283 0_0402_5%@RE283 0_0402_5%@1 2
QE
2B
DM
N6
6D
0L
DW
-7_
SO
T3
63
-6Q
E2
BD
MN
66
D0
LD
W-7
_S
OT
36
3-6
34
5
CE
30
1U
_0
40
2_
6.3
V6
KC
E3
01
U_
04
02
_6
.3V
6K
12
E
B
C
QE7
MMBT3904WT1G_SC70-3~D
E
B
C
QE7
MMBT3904WT1G_SC70-3~D
2
31
CE
37
@1
00
P_
04
02
_5
0V
8J
CE
37
@1
00
P_
04
02
_5
0V
8J
12
RE
75
@1
00
K_
04
02
_5
%R
E7
5@
10
0K
_0
40
2_
5%
12
RE
71
49
.9_
04
02
_1
%R
E7
14
9.9
_0
40
2_
1%
12
RE42 10K_0402_5%RE42 10K_0402_5%1 2
RPE3
2.2K_0804_8P4R_5%
RPE3
2.2K_0804_8P4R_5%
1234 5
678
CE
15
1U
_0402_6.3
V6K
CE
15
1U
_0402_6.3
V6K
1
2
CE
13
0.1
U_
04
02
_2
5V
6C
E1
30
.1U
_0
40
2_
25
V6
12
RE43 2.2K_0402_5%RE43 2.2K_0402_5%1 2
RPE2
4.7K_8P4R_5%
RPE2
4.7K_8P4R_5%
1234 5
678
RE
82
@1
0K
_0
40
2_
5%
RE
82
@1
0K
_0
40
2_
5%1
2
RE8847K_0402_5% RE8847K_0402_5%1 2
RE
77
1.5
8K
_0
40
2_
1%
RE
77
1.5
8K
_0
40
2_
1%
12
RP
E7
10
K_
8P
4R
_5
%R
PE
71
0K
_8
P4
R_
5%1 2 3 4
5678
RE86 10K_0402_5%RE86 10K_0402_5%1 2
CE
25
0.1
U_
04
02
_2
5V
6C
E2
50
.1U
_0
40
2_
25
V6
12
CE
36
0.1
U_
04
02
_2
5V
6
CE
36
0.1
U_
04
02
_2
5V
6
12
CE
40
47
00
P_
04
02
_2
5V
7K
CE
40
47
00
P_
04
02
_2
5V
7K
12
JLPDE1CONN@
HB_A531015-SCHR21
JLPDE1CONN@
HB_A531015-SCHR21
11
22
33
44
55
66
77
88
99
1010
G111
G212
DE
1R
B751S
40T
1G
_S
OD
523-2
@DE
1R
B751S
40T
1G
_S
OD
523-2
@
21
RE56 10K_0402_5%RE56 10K_0402_5%1 2
E
B
C QE
4M
MB
T3904W
T1G
_S
C70-3
E
B
C QE
4M
MB
T3904W
T1G
_S
C70-3
2
31
CE
20
0.1
U_
04
02
_2
5V
6C
E2
00
.1U
_0
40
2_
25
V6
12
RE61@ 0_0402_5%RE61@ 0_0402_5%12
RE281 0_0402_5%@ RE281 0_0402_5%@
1 2
RE33 10K_0402_5%RE33 10K_0402_5%1 2
RE36 100K_0402_5%RE36 100K_0402_5%1 2
JFAN1
ACES_50277-0040N-001
CONN@
JFAN1
ACES_50277-0040N-001
CONN@
112233
GND15GND26
44
CE
12
1U
_0
40
2_
6.3
V6
KC
E1
21
U_
04
02
_6
.3V
6K
12
E
B
C
QE3MMBT3904WT1G_SC70-3~D
E
B
C
QE3MMBT3904WT1G_SC70-3~D
2
31
RE
66
10_0402_5%
@E
MC
@R
E66
10_0402_5%
@E
MC
@
12
RE279 0_0402_5%@ RE279 0_0402_5%@1 2
CE
34
@E
MC
@
4.7
P_
04
02
_5
0V
8C
CE
34
@E
MC
@
4.7
P_
04
02
_5
0V
8C
12
RE37 2.2K_0402_5%RE37 2.2K_0402_5%1 2
CE
45
1U
_0
40
2_
6.3
V6
KC
E4
51
U_
04
02
_6
.3V
6K
12
RPE6
10K_8P4R_5%
RPE6
10K_8P4R_5%
1234 5
678
RE
62
10
0K
_0
40
2_
5%
RE
62
10
0K
_0
40
2_
5%
12
RE55 100K_0402_5%RE55 100K_0402_5%1 2
RE280 0_0402_5%@ RE280 0_0402_5%@1 2
CE
29
22
P_
04
02
_5
0V
8J
CE
29
22
P_
04
02
_5
0V
8J
12
CE
28
22
P_
04
02
_5
0V
8J
CE
28
22
P_
04
02
_5
0V
8J
12
RE282 0_0402_5%@ RE282 0_0402_5%@1 2
CE
31
4.7
U_
06
03
_6
.3V
6K
CE
31
4.7
U_
06
03
_6
.3V
6K
12
RE57 1K_0402_5%RE57 1K_0402_5%1 2
CE
21
10
U_
06
03
_6
.3V
6M
CE
21
10
U_
06
03
_6
.3V
6M
12
RE
63
10
0K
_0
40
2_
5%
RE
63
10
0K
_0
40
2_
5%
12
RE
31
10
0K
_0
40
2_
5%
RE
31
10
0K
_0
40
2_
5%
12
UE2
MEC5085-LZY_DQFN132_11X11
UE2
MEC5085-LZY_DQFN132_11X11
GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATAA5
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_DATA0B6
GPIO011/nSMIA6
GPIO030/GPTP-IN2/BCM_E_INT#/GANG_DATA7B19 GPIO031/GPTP-OUT2/BCM_E_DATA18 GPIO032/BCM_E_CLKB20
GPIO045/LSBCM_D_INT#A19 GPIO046/LSBCM_D_DAT/GANG_STROBEB21 GPIO047/LSBCM_D_CLKA20
GPIO061/LPCPD#A27
GPIO024/THSEL_STRAPB29
SER_IRQA28
LRESET#B30
GPIO100/NEC_SCIA33
GPIO110/PS2_CLK2/GPTP-IN6A37
GPIO111/PS2_DAT2/GPTP-OUT6B40
BGP0B62
XTAL1A61
XTAL2A62
GPIO112/PS2_CLK1AA38
GPIO113/PS2_DAT1AB41
GPIO114/PS2_CLK0AA39
GPIO115/PS2_DAT0AB42
GPIO154/I2C1C_DATA/PS2_CLK1B/GANG_DATA5B59
GPIO155/I2C1C_CLK/PS2_DAT1B/GANG_DATA6A56
GPIO145/I2C1K_DATA/JTAG_TDIA51
GPIO146/I2C1K_CLK/JTAG_TDOB55
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLKB56
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMSA53
GPIO156/LED1/GANG_DATA1B57
GPIO050/FAN_TACH1/GTACH0/GANG_STARTB22
GPIO051/FAN_TACH2/GANG _MODEA21
GPIO052/FAN_TACH3/GTACH1/GANG_ERRORB23
GPIO053/PWM0B24
GPIO054/PWM1/GPWM1A23
GPIO055/PWM2B25
GPIO056/PWM3/GPWM0A24
GPIO121/BCM_A_INT#A42 GPIO122/BCM_A_DATB45 GPIO123/BCM_A_CLKA43
PCI_CLKA29
LFRAME#B31
LAD0A30
LAD1B32
LAD2A31
LAD3B33
CLKRUN#A32
GPIO001/ECSPI_CS1/32KHZ_OUTB2
GPIO015/GPTP-OUT7A8
GPIO016/GPTP-IN8B9
GPIO017/GPTP-OUT8A9
GPIO020/RC_ID2B10GPIO021/RC_ID1A10
VCC_PWRGDB26
GPIO060/KBRST/BCM_B_INT#A25
GPIO101/ECGP_SCLKB36
GPIO102/BCM_C_INT#A34
GPIO103/ECGP_MISOB37
GPIO104/SLP_S0#A35
GPIO105/ECGP_MOSIB38
GPIO106A36
GPIO107/NRESET_OUTB39
GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAPA40
GPIO117/MSCLK/V2P_COUT_HIB43
GPIO120/UART_TX/V2P_COUT_HI1B44
GPIO124/GPTP-OUT5/UART_RX/V2P_COUT_LO1B46
GPIO125/GPTP-IN5/PECI_REQUEST#/GANG_BUSYA44
JTAG_RST#B47
GPIO127/A20MA45
PROCHOT_IN#/PROCHOT_IO#A46
GPIO151/GPTP-IN4/GANG_DATA2A54
GPIO152/GPTP-OUT4B58
GPIO153/LED2/GANG_DATA4A55
V_ISYS1A57
nFWPB65
VBATB64
H_VTRA22
PECI_DATA48VREF_PECIB51
VCI_OVRD_INA64
VCI_IN3#B68
GPIO003/I2C1A_DATAA3
GPIO004/I2C1A_CLKB4
GPIO005/I2C1B_DATA/BCM_B_DATA4
GPIO006/I2C1B_CLK/BCM_B_CLKB5
GPIO012/I2C1H_DATA/I2C2D_DATAB7
GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA3A7
GPIO130/I2C2A_DATA/BCM_C_DATB48
GPIO131/I2C2A_CLK/BCM_C_CLKB49
GPIO132/I2C1G_DATAA47
GPIO140/I2C1G_CLKB50
GPIO141/I2C1F_DATA/I2C2B_DATAB52
GPIO142/I2C1F_CLK/I2C2B_CLKA49
GPIO143/I2C1E_DATAB53
GPIO144/I2C1E_CLKA50
SYSPWR_PRESA59
VCI_IN2#B63
VCI_OUTA60
VCI_IN1#A63VCI_IN0#B67
VTR_ADCA58
GPIO157/LED0B1
GPIO027/GPTP-OUT1A1
DN1_DP1A/THERMB13
DP1_DN1A/VREF_TA13
VSETA17
DN2_DP2AB14
DP2_DN2AA14
VINB15
DN3_DP3AA15
DP3_DN3AB16
VCPA12
DN4_DP4AA16
DP4_DN4AB17
THERMTRIP2#B34
GPIO002/THERMTRIP3#A2
VTRB3
VTRA11
VTRA26
VTRB35
VTRA41
VTRA52
AG
ND
B66
VS
SB
11
VS
S_A
DC
B60
VR
_C
AP
B12
VS
S_R
OB
54
H_V
SS
B18
EP
C1
GPIO026/GPTP-IN1B28
GPIO025/UART_CLKB27
V_ISYS0B61
GPIO014/GPTP-IN7/RC_ID3B8
QE
2A
DM
N6
6D
0L
DW
-7_
SO
T3
63
-6Q
E2
AD
MN
66
D0
LD
W-7
_S
OT
36
3-6
1
2
6
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
EMI depop location
Touch Pad
Place close to JKBTP1
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Keyboard
RSMRST circuit
20130730 same as Goliad
+5V_ALW_U41RSMRST#
CLK_TP_SIO
CLK_TP_SIO
DAT_TP_SIO
DAT_TP_SIO
+3.3V_TP
+3.3V_TP
+5V_RUN+3.3V_ALW
+3.3V_ALW+3.3V_ALW
+3.3V_RUN +3.3V_TP
+5V_ALW
+5V_RUN+3.3V_ALW+3.3V_TP
BC_CLK_ECE1117<36>
BC_INT#_ECE1117<36>BC_DAT_ECE1117<36>
KB_DET#<11,12>
PCH_RSMRST#<36>PCH_RSMRST#_Q <9>
CLK_TP_SIO<36>
DAT_TP_SIO<36>
ALW_PWRGD_3V_5V<36,41>
Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Keyboard
37 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Keyboard
37 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet ofLA-A971P
0.1
Keyboard
37 48Wednesday, March 19, 2014
Compal Electronics, Inc.
CZ34@
0.1U_0402_25V6
CZ34@
0.1U_0402_25V6
1 2RZ
22
10
K_
04
02
_5
%@
RZ
22
10
K_
04
02
_5
%@1
2UZ5
RT9818A-44GU3_SC70-3
@UZ5
RT9818A-44GU3_SC70-3
@
VCC1
GND2 RESET#
3
Part Number Description
NBX0001CY00 FFC 20P G P0.5 PAD=0.3 75MM MB-USH/B 0VN
@USH Board FFC
Part Number Description
NBX0001CY00 FFC 20P G P0.5 PAD=0.3 75MM MB-USH/B 0VN
@USH Board FFC
Part Number Description
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@KBTP FFC
Part Number Description
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@KBTP FFC
RZ
19
4.7
K_
04
02
_5
%R
Z1
94
.7K
_0
40
2_
5%
12
Part Number Description
DC02C004K00 H-CONN SET 0VN MB-HDD
@SATA Cable
Part Number Description
DC02C004K00 H-CONN SET 0VN MB-HDD
@SATA Cable
RZ
21
33
_0
40
2_
5%
@R
Z2
13
3_
04
02
_5
%@1
2
PJP16
PAD-OPEN1x1m
@ PJP16
PAD-OPEN1x1m
@
1 2
CZ
28
@0
.1U
_0
40
2_
25
V6
CZ
28
@0
.1U
_0
40
2_
25
V6
12
Part Number Description
PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
@ Speak
Part Number Description
PK230003Q0L SPK PACK ZJX 2.0W 4 OHM FG
@ Speak
Part Number Description
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
@ FAN
Part Number Description
DC28A000800 FAN SET DAQ20 DC5V AB7405HB-HB3 ADDA
@ FAN
CZ
27
@0
.1U
_0
40
2_
25
V6
CZ
27
@0
.1U
_0
40
2_
25
V6
12
Part Number Description
DC02C004T00 H-CONN SET 0VN MB-LCD-LED-CAM
@eDP Cable
Part Number Description
DC02C004T00 H-CONN SET 0VN MB-LCD-LED-CAM
@eDP Cable
Part Number Description
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@DC-IN Cable
Part Number Description
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@DC-IN Cable
Part Number Description
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@RTC BATT
Part Number Description
DC30100MF00 CONN SET 0VN DCJACK-MB 2DW1003-038110F
@RTC BATT
Part Number Description
NBX0001D100 FFC 6P G P0.5 PAD=0.3 75MM USH/B-FP 0VN
@FP FFC
Part Number Description
NBX0001D100 FFC 6P G P0.5 PAD=0.3 75MM USH/B-FP 0VN
@FP FFC
CZ
30
@E
MC
@1
0P
_0
40
2_
50
V8
JC
Z3
0@
EM
C@
10
P_
04
02
_5
0V
8J
12
CZ
31
@E
MC
@1
0P
_0
40
2_
50
V8
JC
Z3
1@
EM
C@
10
P_
04
02
_5
0V
8J
12
Part Number Description
NBX0001CW00 FFC 8P G P0.5 PAD0.3 50MM MB-MEDIA/B 0VN
@MEDIA Board FFC
Part Number Description
NBX0001CW00 FFC 8P G P0.5 PAD0.3 50MM MB-MEDIA/B 0VN
@MEDIA Board FFC
Part Number Description
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@NFC Board FFC
Part Number Description
NBX0001CZ00 FFC 15P G P.5 PAD.3 85MM MB-NFC MODU 0VN
@NFC Board FFC
CZ
35
0.0
1U
_0
40
2_
16
V7
K@
CZ
35
0.0
1U
_0
40
2_
16
V7
K@
12
JKBTP1
CONCR_205160FW010
CONN@
JKBTP1
CONCR_205160FW010
CONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
GND117
GND218
UZ6TC7SH08FU_SSOP5~D
UZ6TC7SH08FU_SSOP5~D
B1
A2
G3
O4
P5
RZ51 0_0402_5%@ RZ51 0_0402_5%@1 2
Part Number Description
DA30000GZ00 FPC 0VN LF-9591P REV0 M/B-IO/B
@IO FFC
Part Number Description
DA30000GZ00 FPC 0VN LF-9591P REV0 M/B-IO/B
@IO FFC
CZ
29
@0
.1U
_0
40
2_
25
V6
CZ
29
@0
.1U
_0
40
2_
25
V6
12
RZ
18
4.7
K_
04
02
_5
%R
Z1
84
.7K
_0
40
2_
5%
12
Part Number Description
DC02C004S00 H-CONN SET 0VN MB-LCD-LED-CAM-TS
@eDP TS Cable
Part Number Description
DC02C004S00 H-CONN SET 0VN MB-LCD-LED-CAM-TS
@eDP TS Cable
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_RUN/+5V_RUN source
+1.05V_MODPHY
if support MODPHY off keep DSC solution
MODPHY timing spec 0.7V/us and <65us
+3.3V_SUS/+3.3V_HDD source
+1.05V_RUN/+3.3V_ALW_PCH source
For Vpro +1.05V PWR configs
+1.05V_MMax Rating: 2495 mA
For No-Vpro HW configs
RUN_ON
+3.3V_RUN_UZ9
+5V_RUN_UZ9
1.05V_MODPHY_EN
MPHYP_PWR_EN#
+3.3V_SUS_UZ8
+3.3V_HDD_UZ8
+3.3V_ALW_PCH_UZ7
+1.05V_RUN_UZ7
RUN_ON
3.3V_HDD_EN
+5V_RUN
+3.3V_ALW
+5V_ALW
+3.3V_RUN
+3.3V_ALW2
+5V_ALW+1.05V_M +1.05V_MODPHY
+3.3V_HDD
+3.3V_SUS
+5V_ALW
+3.3V_ALW
+5V_ALW
+1.05V_M
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_ALW
+3.3V_RUN
+3.3V_RUN
+1.05V_RUN+1.05V_M
+1.05V_MODPHY+1.05V_RUNMPHYP_PWR_EN<12>
3.3V_HDD_EN<12>
SUS_ON<36,42>
RUN_ON<36>
PCH_ALW_ON<36>
EN_+V1.05SP <43>A_ON<28,36>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Power control
38 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Power control
38 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
Power control
38 48Wednesday, March 19, 2014
Compal Electronics, Inc.
PJP19
@
PAD-OPEN1x1m
PJP19
@
PAD-OPEN1x1m
12
QZ
10
B
DM
N6
6D
0L
DW
-7_
SO
T3
63
-6
QZ
10
B
DM
N6
6D
0L
DW
-7_
SO
T3
63
-6
34
5
RZ41 0_0402_5%NVPRO@ RZ41 0_0402_5%NVPRO@1 2
RN7
10K_0402_5%
RN7
10K_0402_5%
12
PJP20@
PAD-OPEN1x1m
PJP20@
PAD-OPEN1x1m
1 2
UZ7
TPS22966DPUR_SON14_2X3
UZ7
TPS22966DPUR_SON14_2X3
VIN11
VIN12
ON13
VBIAS4
ON25
VIN26
VIN27
VOUT28VOUT29
CT210
GND11
CT112
VOUT113VOUT114
GPAD15
RN6
10K_0402_5%
@RN6
10K_0402_5%
@
12
CZ60 470P_0402_50V7KCZ60 470P_0402_50V7K1 2
CZ40 0.1U_0402_10V7K@CZ40 0.1U_0402_10V7K@1 2
PJP29@
PAD-OPEN1x1m
PJP29@
PAD-OPEN1x1m
1 2
RZ
51
00
K_
04
02
_5
%R
Z5
10
0K
_0
40
2_
5%
12
CZ
38
10
U_
06
03
_6
.3V
6M
CZ
38
10
U_
06
03
_6
.3V
6M
12
CZ
47
0.1
U_
04
02
_1
0V
7K
@
CZ
47
0.1
U_
04
02
_1
0V
7K
@
12
RZ52 0.01_1206_1%NVPRO@ RZ52 0.01_1206_1%NVPRO@1 2
CZ
43
0.1
U_
04
02
_1
0V
7K
@
CZ
43
0.1
U_
04
02
_1
0V
7K
@
12
CZ42 470P_0402_50V7KCZ42 470P_0402_50V7K1 2
CZ62 470P_0402_50V7KCZ62 470P_0402_50V7K1 2
CZ
56
0.1
U_
04
02
_1
0V
7K
@CZ
56
0.1
U_
04
02
_1
0V
7K
@
12
CZ45 470P_0402_50V7KCZ45 470P_0402_50V7K1 2
S
G
D
QZ6SI3456DDV-T1-GE3_TSOP6
S
G
D
QZ6SI3456DDV-T1-GE3_TSOP6
12
3
456
UZ9
TPS22966DPUR_SON14_2X3
UZ9
TPS22966DPUR_SON14_2X3
VIN11
VIN12
ON13
VBIAS4
ON25
VIN26
VIN27
VOUT28VOUT29
CT210
GND11
CT112
VOUT113VOUT114
GPAD15
QZ
10
AD
MN
66
D0
LD
W-7
_S
OT
36
3-6
QZ
10
AD
MN
66
D0
LD
W-7
_S
OT
36
3-6
1
2
6
UZ8
TPS22966DPUR_SON14_2X3
UZ8
TPS22966DPUR_SON14_2X3
VIN11
VIN12
ON13
VBIAS4
ON25
VIN26
VIN27
VOUT28VOUT29
CT210
GND11
CT112
VOUT113VOUT114
GPAD15
CZ39 0.1U_0402_10V7K@CZ39 0.1U_0402_10V7K@12
CZ44 0.1U_0402_10V7K@CZ44 0.1U_0402_10V7K@1 2
CZ41 470P_0402_50V7KCZ41 470P_0402_50V7K1 2
CZ46 1000P_0402_50V7KCZ46 1000P_0402_50V7K1 2
RZ53
0_0603_5%
VPRO@RZ53
0_0603_5%
VPRO@
12
CZ
25
22
0P
_0
40
2_
50
V7
KC
Z2
52
20
P_
04
02
_5
0V
7K
1
2
RZ42 0_0402_5%VPRO@ RZ42 0_0402_5%VPRO@
1 2
PJP22@
PAD-OPEN1x3m
PJP22@
PAD-OPEN1x3m
1 2
RZ
16
10
0K
_0
40
2_
5%
RZ
16
10
0K
_0
40
2_
5%
12
PJP21
@
PAD-OPEN1x3m
PJP21
@
PAD-OPEN1x3m
12
PJP36@
PAD-OPEN1x1m
PJP36@
PAD-OPEN1x1m
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SYS_LED_MASK# LID_CL#
Mask All LEDs (Sniffer Function)
Mask Base MB LEDs (Lid Closed)
0
1 0
X
LED Circuit Control Table
Do not Mask LEDs (Lid Opened) 11
HDD LED solution for White LED
WLAN LED solution for White LED
Battery LED
Breath LED
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Fiducial Mark
POWER & INSTANT ON SWITCH
Place LED3 close to SW3
BAT1_LED#_Q
BAT2_LED#_Q BATT_WHITE#
BATT_YELLOW#
BREATH_LED#_Q
MASK_BASE_LEDS#
MASK_BASE_LEDS#
MASK_BASE_LEDS#
SYS_LED_MASK#
MASK_BASE_LEDS#
MASK_BASE_LEDS#
BREATH_WHITE_LED#
PANEL_HDD_LED#
MASK_BASE_LEDS#SATA_LED
SATA_LED#
BREATH_WHITE_LED
WLAN_LED
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+5V_ALW
+5V_ALW +5V_ALW
+5V_ALW
+5V_ALW
BREATH_LED#<34,36>
SYS_LED_MASK#<28,35>
LID_CL#<30,35>
WIRELESS_LED#<30,35>
SATA_ACT#<6>
LED_SATA_DIAG_OUT#<35>
MASK_SATA_LED#<35>
BAT2_LED#<36>
BAT1_LED#<36>
PANEL_HDD_LED# <23>
BATT_YELLOW_LED# <23>
BATT_WHITE_LED# <23>
BREATH_WHITE_LED# <23>
POWER_SW#_MB<36,9>
Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
PAD, LED
39 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
PAD, LED
39 48Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P0.1
PAD, LED
39 48Wednesday, March 19, 2014
Compal Electronics, Inc.
H9@H_2P8
H9@H_2P8
1
RZ
31
100K
_0402_5%
RZ
31
100K
_0402_5%
12
QZ7BDMN66D0LDW-7_SOT363-6
QZ7BDMN66D0LDW-7_SOT363-6
34
5
H13@H_3P4
H13@H_3P4
1
RZ
24
10K
_0402_5%
RZ
24
10K
_0402_5%
12
H21@H_3P0N
H21@H_3P0N
1
H1@H_2P3
H1@H_2P3
1
H14@H_3P4
H14@H_3P4
1
W
Y
LED7
LTW-295DSKS-5A_YEL-WHITE
W
Y
LED7
LTW-295DSKS-5A_YEL-WHITE
21
43
H3@H_2P5
H3@H_2P5
1
H15@H_3P4
H15@H_3P4
1
QZ12DDTA114EUA-7-F_SOT323-3
QZ12DDTA114EUA-7-F_SOT323-3
2
13
RZ28 330_0402_5%RZ28 330_0402_5%1 2
RZ44 390_0402_5%RZ44 390_0402_5%1 2
H5@H_2P8
H5@H_2P8
1
DZ4
RB751S40T1G_SOD523-2
DZ4
RB751S40T1G_SOD523-2
1 2
QZ14BDMN66D0LDW-7_SOT363-6
QZ14BDMN66D0LDW-7_SOT363-6
34
5
H16@H_3P4
H16@H_3P4
1
FD1@
FIDUCIAL MARK~D
FD1@
FIDUCIAL MARK~D
1
UZ10TC7SH08FU_SSOP5~D
UZ10TC7SH08FU_SSOP5~D
B1
A2
G3
O4
P5
RZ43 1K_0402_5%RZ43 1K_0402_5%1 2
QZ14ADMN66D0LDW-7_SOT363-6
QZ14ADMN66D0LDW-7_SOT363-6
1
2
6
ST3@H_3P3
ST3@H_3P3
1
RZ36 270_0402_5%RZ36 270_0402_5%1 2
QZ3BDMN66D0LDW-7_SOT363-6
QZ3BDMN66D0LDW-7_SOT363-6
34
5QZ5A
DMN66D0LDW-7_SOT363-6QZ5A
DMN66D0LDW-7_SOT363-61
2
6
ST1CLIP_C5P1@ ST1CLIP_C5P1@
1
LED5
LTW-193ZDS5_WHITE
LED5
LTW-193ZDS5_WHITE
2 1RZ33 390_0402_5%RZ33 390_0402_5%
1 2
ST2@H_3P3
ST2@H_3P3
1
RZ27 680_0402_5%RZ27 680_0402_5%1 2
H11@H_2P8
H11@H_2P8
1
QZ7ADMN66D0LDW-7_SOT363-6
QZ7ADMN66D0LDW-7_SOT363-6
1
2
6
SW2
SKRBAAE010_4P
SW2
SKRBAAE010_4P
1
3
2
4
QZ5BDMN66D0LDW-7_SOT363-6
QZ5BDMN66D0LDW-7_SOT363-6
34
5FD2@
FIDUCIAL MARK~D
FD2@
FIDUCIAL MARK~D
1
LED3LTW-193ZDS5_WHITE
LED3LTW-193ZDS5_WHITE
1 2
RZ34 680_0402_5%RZ34 680_0402_5%1 2
DZ3
RB751S40T1G_SOD523-2
DZ3
RB751S40T1G_SOD523-2
1 2
H19@H_2P1
H19@H_2P1
1
H17@H_2P8
H17@H_2P8
1
H2@H_2P5
H2@H_2P5
1
H10@H_2P8
H10@H_2P8
1
QZ9
DDTA114EUA-7-F_SOT323-3
QZ9
DDTA114EUA-7-F_SOT323-3
2
13
QZ4DDTA114EUA-7-F_SOT323-3
QZ4DDTA114EUA-7-F_SOT323-3
2
13
H8@H_2P8
H8@H_2P8
1
FD3@
FIDUCIAL MARK~D
FD3@
FIDUCIAL MARK~D
1
RZ25 390_0402_5%RZ25 390_0402_5%1 2
H4@H_2P8
H4@H_2P8
1
FD4@
FIDUCIAL MARK~D
FD4@
FIDUCIAL MARK~D
1
H18@H_2P8
H18@H_2P8
1
H12@H_2P8
H12@H_2P8
1
RZ32 270_0402_5%RZ32 270_0402_5%1 2
H7@H_2P5
H7@H_2P5
1
LED6
LTW-193ZDS5_WHITE
LED6
LTW-193ZDS5_WHITE
2 1
H6@H_2P8
H6@H_2P8
1
H20@H_3P0N
H20@H_3P0N
1
QZ3ADMN66D0LDW-7_SOT363-6
QZ3ADMN66D0LDW-7_SOT363-6
1
2
6
CZ48@
0.1U_0402_25V6
CZ48@
0.1U_0402_25V6
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DELL CONFIDENTIAL/PROPRIETARY
DC_IN+ Source
COIN RTC Battery
Primary Battery Connector
NB_PSID_TS5A63157NB_PSID
+DCIN_JACK
-DCIN_JACK
+Z
4012
PBATT+_C
PBAT_SMBDAT_CPBAT_PRES#_C
PBAT_SMBCLK_C
+3.3V_ALW
+5V_ALW
+DC_IN_SS+DC_IN
+5V_ALW
+COINCELL
+RTC_CELL
+3.3V_RTC_LDO
+COINCELL
+3.3V_ALW
+PBATT
GND
PSID_DISABLE# <35>
DOCK_PSID<34> GPIO_PSID_SELECT <35>
PS_ID <36>
SOFT_START_GC <47>
AC_DIS <36,47>
PBAT_SMBDAT <37>
SLICE_BAT_PRES#<34,36,48>
PBAT_PRES# <36,48>
PBAT_SMBCLK <37>
DOCK_SMB_ALERT# <34,36,48>
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+DCIN
40 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+DCIN
40 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+DCIN
40 53Wednesday, March 19, 2014
Compal Electronics, Inc.
PD5
AZC199-02SPR7G_SOT23-3
@EMC@PD5
AZC199-02SPR7G_SOT23-3
@EMC@
231
PR7
0_0402_5%
@ PR7
0_0402_5%
@1 2
PRP2
100_0804_8P4R_5%
PRP2
100_0804_8P4R_5%
18273645
PR10
100K_0402_1%
PR10
100K_0402_1%
12
PBATT1
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
@ PBATT1
LLTOP_ALLTOP C144LS-109A9-L 9P BATT P2
@
11
33
44
55
66
88
99
22
77
GND10
GND11
G
D S
PQ2FDV301N-G_SOT23-3G
D S
PQ2FDV301N-G_SOT23-32
1 3
PL4FBMJ4516HS720NT_2P
EMC@ PL4FBMJ4516HS720NT_2P
EMC@
1 2
PR13
10K_0402_5%
@ PR13
10K_0402_5%
@1 2
PR60_0402_5%
PR60_0402_5%
1 2
PR8
2.2K_0402_5%
PR8
2.2K_0402_5%
12
PR17
10K_0402_5%
PR17
10K_0402_5%
1 2
PR2
100K_0402_5%
PR2
100K_0402_5%
12
PJP1
PAD-OPEN 1x3m
PJP1
PAD-OPEN 1x3m
1 2
PC
10
10
U_
08
05
_2
5V
6K
PC
10
10
U_
08
05
_2
5V
6K
12
PD3
BAS40CW SOT-323
PD3
BAS40CW SOT-323
231
PD1
TVNST52302AB0_SOT523-3
EMC@PD1
TVNST52302AB0_SOT523-3
EMC@
2 31
PR12
15K_0402_1%
PR12
15K_0402_1%
12
PD2
TVNST52302AB0_SOT523-3
EMC@PD2
TVNST52302AB0_SOT523-3
EMC@
2 31
PQ6B
DC
X1
24
EK
-7-F
PN
P/N
PN
_S
C7
4-6
~D
PQ6B
DC
X1
24
EK
-7-F
PN
P/N
PN
_S
C7
4-6
~D
2
43
PC
91
00
0P
_0
60
3_
50
V7
KE
MC
@P
C9
10
00
P_
06
03
_5
0V
7K
EM
C@
12
PQ4
FDMC6679AZ_MLP8-5
PQ4
FDMC6679AZ_MLP8-5
3 52
4
1
PD4
SDMK0340L-7-F_SOD323-2~D
PD4
SDMK0340L-7-F_SOD323-2~D
1 2
PR933_0402_5%
PR933_0402_5%
1 2
PR
15
10
0K
_0
40
2_
5%
PR
15
10
0K
_0
40
2_
5%1
2
10U_0805_25V6K
PC22
EMC15U@10U_0805_25V6K
PC22
EMC15U@
PR11
10K_0402_1%
PR11
10K_0402_1%
12
2
1 3
PQ1
ME2301D-G 1P SOT-23-3
2
1 3
PQ1
ME2301D-G 1P SOT-23-3
2
1 3
PJPDC1
ACES_50299-0050N-001
@ PJPDC1
ACES_50299-0050N-001
@
1122334455
GND6GND7
JRTC1
TYCO_2-1775293-2~D
@ JRTC1
TYCO_2-1775293-2~D
@
11
22
G4G3
PC11U_0603_10V4ZPC11U_0603_10V4Z
1
2
PR11K_0402_5%PR11K_0402_5%
12
10U_0805_25V6K
PC22
EMC12U@10U_0805_25V6K
PC22
EMC12U@
PR
16
4.7
K_
08
05
_5
%
@P
R1
6
4.7
K_
08
05
_5
%
@1
2
PC
32
20
0P
_0
40
2_
50
V7
K~
DP
C3
22
00
P_
04
02
_5
0V
7K
~D
12
PL1
FBMJ4516HS720NT_2P~D
EMC@PL1
FBMJ4516HS720NT_2P~D
EMC@
1 2
PC4
1500P_0402_50V7K
PC4
1500P_0402_50V7K
12
PR
14
1M
_0
40
2_
5%
PR
14
1M
_0
40
2_
5%
12
PU1
TS5A63157DCKR_SC70-6~D
PU1
TS5A63157DCKR_SC70-6~D
V+5
NC3
COM4
GND2
IN6
NO1
E
B
C
PQ3MMST3904-7-F_SOT323~D
E
B
C
PQ3MMST3904-7-F_SOT323~D
2
31
AZC199-02SPR7G_SOT23-3
PD5
EMC12U@AZC199-02SPR7G_SOT23-3
PD5
EMC12U@
PC
50
.02
2U
_0
80
5_
50
V7
KP
C5
0.0
22
U_
08
05
_5
0V
7K
12
PR18
1M_0402_5%
PR18
1M_0402_5%
12
PC
11
0.1
U_
06
03
_2
5V
7K
@E
MC
@P
C1
10
.1U
_0
60
3_
25
V7
K@
EM
C@
12
PL2
FBMJ4516HS720NT_2P~DEMC@PL2
FBMJ4516HS720NT_2P~DEMC@
1 2
PL3BLM15AG102SN1D_2PEMC@ PL3BLM15AG102SN1D_2PEMC@
12
PQ6A
DCX124EK-7-F PNP/NPN_SC74-6~D
PQ6A
DCX124EK-7-F PNP/NPN_SC74-6~D
5
16
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DELL CONFIDENTIAL/PROPRIETARY
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
3VALWP
TDC 4.5 A
Peak Current 6.4 A
OCP Current 7.68 A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 15.5mohm
CAP ESR 18mohm
5VALWP
TDC 3.5 A
Peak Current 5.0 A
OCP Current 6.0 A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 25mohm
CAP ESR 18mohm
DELL CONFIDENTIAL/PROPRIETARY
LG_3V
EN
SW1
PGOOD_3V_5V
FB_3V
BST_5V BST_5V_C
LG_5VEN
BST_3V_C BST_3V
SW2
FB
_5
V
EN
UG_5VUG_3V
SN
UB
_3
V
SN
UB
_5
V
+3.3V_ALW2
+3V5V_PWR_SRC
+5V_ALWP
+3V5V_PWR_SRC
+3V5V_PWR_SRC
+3.3V_ALWP
+5V_ALW2
+5V_ALWP
+3.3V_ALW
+5V_ALW
+3.3V_ALWP
+3.3V_ALW
+PWR_SRC
+3.3V_RTC_LDO
ALWON<36>
ALW_PWRGD_3V_5V<36,37>
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+5V_ALW/3.3V_ALW
41 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+5V_ALW/3.3V_ALW
41 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+5V_ALW/3.3V_ALW
41 53Wednesday, March 19, 2014
Compal Electronics, Inc.
PQ
10
3S
I77
16
AD
N-T
1-G
E3
_P
OW
ER
PA
K8
-5P
Q1
03
SI7
71
6A
DN
-T1
-GE
3_
PO
WE
RP
AK
8-5
4
5
123
PQ
10
1S
IS4
12
DN
-T1
-GE
3_
PO
WE
RP
AK
8-5
PQ
10
1S
IS4
12
DN
-T1
-GE
3_
PO
WE
RP
AK
8-5
4
5
123
PL1001UH +-20% 6.6A
@EMC@PL1001UH +-20% 6.6A
@EMC@
1 2
TPS51285BRUKR_QFN20_3X3
PU100
TPS51285BRUKR_QFN20_3X3
PU100
CS
11
VF
B1
2
VR
EG
33
VF
B2
4
CS
25
EN26
PGOOD7
SW28
VBST29
DRVH210
DR
VL
21
1
VIN
12
VR
EG
51
3
VO114
DR
VL
11
5
DRVH116
VBST117
SW118
VCLK19
EN
12
0
PAD21
PR1092.2_0603_5%
PR1092.2_0603_5%1 2
PR
11
24
.7_
12
06
_5
%@
EM
C@
PR
11
24
.7_
12
06
_5
%@
EM
C@
12
PQ
10
0S
IS4
12
DN
-T1
-GE
3_
PO
WE
RP
AK
8-5
PQ
10
0S
IS4
12
DN
-T1
-GE
3_
PO
WE
RP
AK
8-5
4
5
1 2 3
PC1090.1U_0603_25V7K
PC1090.1U_0603_25V7K
1 2
PC
11
46
80
P_
06
03
_5
0V
7K
@E
MC
@P
C1
14
68
0P
_0
60
3_
50
V7
K@
EM
C@
12
PR10210K_0402_1%
PR10210K_0402_1%
1 2
PL1012.2UH_7.8A_20%
PL1012.2UH_7.8A_20%
1 2
PJP101
PAD-OPEN 1x3m
PJP101
PAD-OPEN 1x3m
1 2
PC
10
11
0U
_0
80
5_
25
V6
KP
C1
01
10
U_
08
05
_2
5V
6K
12
PC
11
70
.1U
_0
60
3_
25
V7
KP
C1
17
0.1
U_
06
03
_2
5V
7K
12
PR106
16.9K_0402_1%
PR106
16.9K_0402_1%
12
PL1023.3UH_6.3A_20%
PL1023.3UH_6.3A_20%
1 2
0.1U_0402_25V6
PC106
[email protected]_0402_25V6
PC106
EMC12UwithD@
PC
11
16
80
P_
06
03
_5
0V
7K
@E
MC
@P
C1
11
68
0P
_0
60
3_
50
V7
K@
EM
C@
12
PC
10
52
20
0P
_0
40
2_
50
V7
K@
EM
C@
PC
10
52
20
0P
_0
40
2_
50
V7
K@
EM
C@
12
PR10410K_0402_1%
PR10410K_0402_1%
1 2
PC
10
60
.1U
_0
40
2_
25
V6
@E
MC
@P
C1
06
0.1
U_
04
02
_2
5V
6@
EM
C@
12
PC
10
04
.7U
_0
60
3_
10
V6
KP
C1
00
4.7
U_
06
03
_1
0V
6K
12
PR1080_0402_5%
PR1080_0402_5%
1 2
PJP100
PAD-OPEN 1x3m
PJP100
PAD-OPEN 1x3m
1 2
PC
11
91
U_
06
03
_1
0V
6K
@
PC
11
91
U_
06
03
_1
0V
6K
@
12
PR
10
5
20
K_
04
02
_1
%
PR
10
5
20
K_
04
02
_1
%1
2
PC
11
84
.7U
_0
60
3_
10
V6
KP
C1
18
4.7
U_
06
03
_1
0V
6K
12
+
PC
11
31
50
U_
D_
6.3
VM
_R
15
M
+
PC
11
31
50
U_
D_
6.3
VM
_R
15
M
1
2
PR103
0_0402_5%
PR103
0_0402_5%
12
PR114200_0402_1%
PR114200_0402_1%
1 2
PR1130_0402_5%
PR1130_0402_5%
1 2
PQ
10
2S
I77
16
AD
N-T
1-G
E3
_P
OW
ER
PA
K8
-5P
Q1
02
SI7
71
6A
DN
-T1
-GE
3_
PO
WE
RP
AK
8-5
4
5
1 2 3
PR
11
14
.7_
12
06
_5
%@
EM
C@
PR
11
14
.7_
12
06
_5
%@
EM
C@
12
PR1006.49K_0402_1%
PR1006.49K_0402_1%
1 2
PR1102.2_0603_5%
PR1102.2_0603_5%1 2
PC
10
21
0U
_0
80
5_
25
V6
KP
C1
02
10
U_
08
05
_2
5V
6K
12
2200P_0402_50V7K
PC105
EMC12UwithD@2200P_0402_50V7K
PC105
EMC12UwithD@
PR10115K_0402_1%
PR10115K_0402_1%
1 2
PR107
100K_0402_1%
PR107
100K_0402_1%
12
PJP102
PAD-OPEN 1x3m
PJP102
PAD-OPEN 1x3m
1 2
+
PC
11
51
50
U_
D_
6.3
VM
_R
15
M
+
PC
11
51
50
U_
D_
6.3
VM
_R
15
M
1
2
PC1100.1U_0603_25V7K
PC1100.1U_0603_25V7K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
FB sense trace
FB sense trace when FB pull down to GND
+1.35V_MEM
TDC 6.6 A
Peak Current 9.5 A
OCP Current 11.4 A
TYP MAX
H/S Rds(on) 24mohm , 30mohm
L/S Rds(on) 13.5mohm , 16.5mohm
Choke DCR 7.4mohm
CAP ESR 17mohm
Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P
S5 L L off off off
S3 L H on on off
S0 H H on on on
0.675Volt +/- 5%
TDC 0.7 A
Peak Current 1.0 A
OCP Current 2.6 A fix by IC
DH_1.35V
SW_1.35V
CS_1.35V
BOOT_1.35V_C
VDD_1.35V
+VLDOIN_1.35V
S5_1.35V
SN
UB
_1
.35
V
BOOT_1.35V
1.35V_B+
+V_DDR_REF
1.35V_FB
+1.35V_MEN_P
DL_1.35V
1.35V_B+
+1.35V_MEN_P +1.35V_MEM
+0.675V_DDR_VTT+0.675V_P
+PWR_SRC
+5V_ALW
+5V_ALW
+1.35V_MEN_P
+0.675V_P
+1.35V_MEN_P
+V_DDR_REF
+1.35V_MEN_P
0.675V_DDR_VTT_ON<18>
SUS_ON<30,36>
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.35V_MEN/+0.675V_DDR_VTT
42 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.35V_MEN/+0.675V_DDR_VTT
42 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.35V_MEN/+0.675V_DDR_VTT
42 53Wednesday, March 19, 2014
Compal Electronics, Inc.
+
PC
20
72
20
U_
D2
_2
VY
_R
17
M
+
PC
20
72
20
U_
D2
_2
VY
_R
17
M
1
2
PR20119.6K_0402_1%
PR20119.6K_0402_1%
1 2
PR204
0_0603_5%
PR204
0_0603_5%
12 PR205
8.06K_0402_1%PR205
8.06K_0402_1%1 2
PR200
2.2_0603_5%
PR200
2.2_0603_5%
1 2
PC213100P_0402_50V8J
PC213100P_0402_50V8J
1 2
PQ201SI7716ADN-T1-GE3_POWERPAK8-5
PQ201SI7716ADN-T1-GE3_POWERPAK8-5
4
5
1 2 3
PC
20
4
0.2
2U
_0
60
3_
16
V7
K
PC
20
4
0.2
2U
_0
60
3_
16
V7
K
12
PR202
5.1_0603_5%
PR202
5.1_0603_5%
1 2
PC
20
11
0U
_0
80
5_
25
V6
K
@
PC
20
11
0U
_0
80
5_
25
V6
K
@
12
PJP203
JUMP_1x3m
PJP203
JUMP_1x3m
11
22
PJP200
PAD-OPEN 1x2m~D
PJP200
PAD-OPEN 1x2m~D
21
PC214
.1U_0402_16V7K
@ PC214
.1U_0402_16V7K
@12
PC215
.1U_0402_16V7K
@ PC215
.1U_0402_16V7K
@
12
PC211
1U_0603_10V6K
PC211
1U_0603_10V6K
PR2070_0402_5%
PR2070_0402_5%1 2
PL2001UH_11A_20%
PL2001UH_11A_20%1 2
PR209
10K_0402_1%
PR209
10K_0402_1%
12
PQ200SIS412DN-T1-GE3_POWERPAK8-5
PQ200SIS412DN-T1-GE3_POWERPAK8-5
4
5
1 2 3
PU200
RT8207MZQW_WQFN20_3X3
PU200
RT8207MZQW_WQFN20_3X3
VTTSNS2
FB
6
S5
8
PG
OO
D1
0
VDDP12
PH
AS
E1
6
BO
OT
18
VTTREF4
PGND14
VTTGND1
GND3
VDDQ5
S3
7
TO
N9
VDD11
CS13
LGATE15 U
GA
TE
17
VT
T2
0
VL
DO
IN1
9
PAD21
PJP204
JUMP_1x3m
PJP204
JUMP_1x3m
11
22
PC
20
01
0U
_0
80
5_
25
V6
KP
C2
00
10
U_
08
05
_2
5V
6K
12
PR2100_0402_5%
PR2100_0402_5%1 2
PJP201
PAD-OPEN1x1m
PJP201
PAD-OPEN1x1m
1 2
PJP202
PAD-OPEN1x1m
PJP202
PAD-OPEN1x1m
1 2
2200P_0402_50V7K
PC203
EMC12UwithD@2200P_0402_50V7K
PC203
EMC12UwithD@
PC
20
32
20
0P
_0
40
2_
50
V7
K
@E
MC
@P
C2
03
22
00
P_
04
02
_5
0V
7K
@E
MC
@
12
PR
20
34.7
_1206_5%
@E
MC
@P
R2
03
4.7
_1206_5%
@E
MC
@
12
PC2091U_0603_10V6K
PC2091U_0603_10V6K
PC
20
60
.1U
_0
40
2_
25
V6
@E
MC
@P
C2
06
0.1
U_
04
02
_2
5V
6
@E
MC
@
12
PC2120.033U_0402_16V7K
PC2120.033U_0402_16V7K
PR206
768K_0402_1%
PR206
768K_0402_1%
1 2
PC
20
86
80
P_
06
03
_5
0V
7K
@E
MC
@P
C2
08
68
0P
_0
60
3_
50
V7
K@
EM
C@
12
PC
20
52
2U
_0
80
5_
6.3
V6
MP
C2
05
22
U_
08
05
_6
.3V
6M
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
+1.05V_MEM
TDC 5.7 A
Peak Current 8.1 A
OCP Current 9.72 A
TYP MAX
Choke DCR 13.0mohm , 14.0mohm
+V1.05SP_B+
SW_+V1.05SP
FB_+V1.05SP
SNB_1.05V
BST_+V1.05SP
ILMT_1.05V
ILMT_1.05V
EN_+V1.05SP
BST_+V1.05SP_C
1.05V_MP_PWROK
+PWR_SRC
+3.3V_ALW
+1.05V_MP
+3.3V_ALW
+3.3V_ALW
+1.05V_MP +1.05V_M
EN_+V1.05SP <38>
1.05V_M_PWRGD<9>
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.05V_M
43 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.05V_M
43 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.05V_M
43 53Wednesday, March 19, 2014
Compal Electronics, Inc.
PR3130_0402_5%
PR3130_0402_5%
1 2
PR
31
010K
_0402_1%
PR
31
010K
_0402_1% 1
2
PC3020.1U_0603_25V7K
PC3020.1U_0603_25V7K
1 2
PR315100K_0402_1%
PR315100K_0402_1%
1 2
PR
30
77.5
K_0402_1%
PR
30
77.5
K_0402_1%
12
PC
31
04
.7U
_0
60
3_
6.3
V6
KP
C3
10
4.7
U_
06
03
_6
.3V
6K
12
PU300
SY8208DQNC_QFN10_3X3
PU300
SY8208DQNC_QFN10_3X3
IN8
BYP7
PG2
ILMT3
LX10
FB4
LDO5
GND9
EN1
BS6
PR308
0_0402_5%
@PR308
0_0402_5%
@
12
PC
30
64
7U
_0
80
5_
6.3
V6
MP
C3
06
47
U_
08
05
_6
.3V
6M
12
PL3010.68UH +-20% 7.9A
PL3010.68UH +-20% 7.9A
1 2
PR306
0_0402_5%
@PR306
0_0402_5%
@
12
PC301680P_0603_50V7K
@EMC@ PC301680P_0603_50V7K
@EMC@
1 2
PC
30
82
2U
_0
80
5_
6.3
VA
M@
PC
30
82
2U
_0
80
5_
6.3
VA
M@
12
PC
30
02
20
0P
_0
40
2_
50
V7
K
@E
MC
@P
C3
00
22
00
P_
04
02
_5
0V
7K
@E
MC
@
12
PJP300
PAD-OPEN 1x2m~D
PJP300
PAD-OPEN 1x2m~D
21
PC
30
54
7U
_0
80
5_
6.3
V6
MP
C3
05
47
U_
08
05
_6
.3V
6M
12
PC
30
94
.7U
_0
60
3_
6.3
V6
KP
C3
09
4.7
U_
06
03
_6
.3V
6K
12
PC
31
10
.1U
_0
40
2_
25
V6
@E
MC
@P
C3
11
0.1
U_
04
02
_2
5V
6
@E
MC
@
12
2200P_0402_50V7K
PC300
EMC12UwithD@2200P_0402_50V7K
PC300
EMC12UwithD@
PR
30
91
K_
04
02
_5
%P
R3
09
1K
_0
40
2_
5%
12
PC
30
31
0U
_0
80
5_
25
V6
KP
C3
03
10
U_
08
05
_2
5V
6K
12
PR303
1M_0402_1%
PR303
1M_0402_1%
12
PJP302
PAD-OPEN 1x2m~D
PJP302
PAD-OPEN 1x2m~D
21 PR3120_0603_5%
PR3120_0603_5%1 2
0.1U_0402_25V6
PC311
[email protected]_0402_25V6
PC311
EMC12UwithD@
PC
30
72
2U
_0
80
5_
6.3
VA
MP
C3
07
22
U_
08
05
_6
.3V
AM
12
PC
30
43
30
P_
04
02
_5
0V
7K
PC
30
43
30
P_
04
02
_5
0V
7K
12
PR3054.7_1206_5%
@EMC@ PR3054.7_1206_5%
@EMC@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.5V_RUN
TDC 0.47 A
Peak Current 0.67 A
DELL CONFIDENTIAL/PROPRIETARY
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5V_VIN
1.5VSP
+3.3V_RUN
+1.5V_RUN
+5V_ALW
+3.3V_RUN
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.5V_RUN
44 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.5V_RUN
44 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+1.5V_RUN
44 53Wednesday, March 19, 2014
Compal Electronics, Inc.
PR40310K_0402_1%
PR40310K_0402_1%
12
PJP401
PAD-OPEN1x1m
PJP401
PAD-OPEN1x1m
1 2PR400
100K_0402_5%
PR400
100K_0402_5%
1 2
PC404
22U_0805_6.3V6M
PC404
22U_0805_6.3V6M
12
PC4001U_0402_6.3V6KPC4001U_0402_6.3V6K
12
PJP400
PAD-OPEN1x1m
PJP400
PAD-OPEN1x1m
12
PR
401
47K
_0402_5%
@P
R401
47K
_0402_5%
@
12
PR4028.66K_0402_1%
PR4028.66K_0402_1%
12
PC4014.7U_0805_6.3V6KPC4014.7U_0805_6.3V6K
12
PC4030.01U_0402_25V7KPC403
0.01U_0402_25V7K
12
PU400
APL5930KAI-TRG_SO8
PU400
APL5930KAI-TRG_SO8
GN
D1
VOUT4POK
7
EN8
VC
NT
L6
VIN5
VOUT3
FB2
VIN9
PC
402
.1U
_0402_16V
7K
@E
MC
@P
C402
.1U
_0402_16V
7K
@E
MC
@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
TI recommend 1nF
from processor
CPU 15W
TDC 10 A
Peak Current 32 A
OCP Current 38.4 A
DC Load line -2.0 mV/A
Icc_Dyn_VID1 27 A
Choke DCR: 0.66m +-7% ohm
PH500 B Value : 4250k 1%
PH501 B Value : 3370k 1%
O-USR
PWM1
CO
RE
_S
NU
B
CSN1
CSP1
CSP1
CSN1
CO
RE
_B
OO
T_C
IMON
OCP-I
+VCC_PWR_SRC
VFB
GFB
SLEWA
VREF
B-RAMP
VID
ALE
RT
_N
VID
SC
LK
VF
B
GF
B
SKIP#
PWM1
F-IMAX
VID
SO
UT
+VCC_PWR_SRC
VR
_H
OT
#
VREF
CORE_SW
CORE_BOOT_R
CORE_BOOT
SKIP#
SKIP#1
+V
CC
_P
WR
_S
RC
OCP-I
+VCC_CORE
+3.3V_RUN
+5V_RUN+5V_ALW
+3.3V_RUN
+3.3V_RUN
+1.05V_VCCST
+PWR_SRC
+3.3V_RUN
H_PROCHOT#<9,36,46>
VCCSENSE<15>
VSSSENSE<17>
VIDALERT_N<15>
VIDSCLK<15>
H_VR_EN <15>
H_VR_READY <15>
VIDSOUT<15>
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+VCC_CORE
45 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+VCC_CORE
45 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
+VCC_CORE
45 53Wednesday, March 19, 2014
Compal Electronics, Inc.
PR5320_0402_5%
PR5320_0402_5%
1 2
PR5390_0402_5%
PR5390_0402_5%
1 2
PR
509
20K
_0402_1%
PR
509
20K
_0402_1%
12
2200P_0402_50V7K
PC520
EMC12UwithD@2200P_0402_50V7K
PC520
EMC12UwithD@
PC
514
47P
_0402_50V
8J
PC
514
47P
_0402_50V
8J
12
PR518
2M_0402_1%
@ PR518
2M_0402_1%
@
12
PR
534
0_0402_5%
PR
534
0_0402_5%
12
PR
522
4.7
_1206_5%
@E
MC
@P
R522
4.7
_1206_5%
@E
MC
@
12
PR525
27K_0402_1%
@ PR525
27K_0402_1%
@
12
PR
528
75
_0
40
2_
1%
@
PR
528
75
_0
40
2_
1%
@
12
PR500
75_0402_1%
@ PR500
75_0402_1%
@
12
PC
505
1U
_0603_10V
6K
PC
505
1U
_0603_10V
6K
12
PR511
10K_0402_5%
PR511
10K_0402_5%
1 2
PC
500
4700P
_0603_50V
7K
PC
500
4700P
_0603_50V
7K
12
PR
514
20
K_
04
02
_1
%P
R514
20
K_
04
02
_1
% 12
PC
520
2200P
_0402_50V
7K
@E
MC
@P
C520
2200P
_0402_50V
7K
@E
MC
@
12
PR
508
100K
_0402_1%
PR
508
100K
_0402_1%
12
PR
502
75
_0
40
2_
1%
@
PR
502
75
_0
40
2_
1%
@
12
PC
502
0.0
68U
_0402_16V
7K
PC
502
0.0
68U
_0402_16V
7K
12
PC
508
680P
_0603_50V
7K
@E
MC
@P
C508
680P
_0603_50V
7K
@E
MC
@
12
PR
527
54
.9_
04
02
_1
%P
R527
54
.9_
04
02
_1
%
12
PC509
1U_0603_10V7K
PC509
1U_0603_10V7K
12
PR516
1.91K_0402_1%
@ PR516
1.91K_0402_1%
@1 2
PC
517
10U
_0805_25V
6K
@P
C517
10U
_0805_25V
6K
@
12
PL5000.15UH_PCME064T-R15MS0R667_36A_20%
PL5000.15UH_PCME064T-R15MS0R667_36A_20%
1
3
4
2
PH
500
100K_0402_1%_NCP15WF104F03RC
PH
500
100K_0402_1%_NCP15WF104F03RC
12
PR5122.15K_0402_1%
PR5122.15K_0402_1%
12
PR
507
150K
_0402_1%
PR
507
150K
_0402_1%
12
PU501
CSD97374CQ4M_SON8_3P5X4P5
PU501
CSD97374CQ4M_SON8_3P5X4P5
PGND13
VDD2
SKIP#1
VSW4PWM
8
VIN5
BOOT7
BOOT_R6
PGND29
PR5172.2_0603_5%
PR5172.2_0603_5%
12
PR
501
316K
_0402_1%
PR
501
316K
_0402_1%1
2
PJP500
PAD-OPEN 4x4m
PJP500
PAD-OPEN 4x4m
1 2
PC5121500P_0402_50V7K
PC5121500P_0402_50V7K
1 2
PC
513
0.0
68U
_0402_16V
7K
PC
513
0.0
68U
_0402_16V
7K
12
PC
516
10U
_0805_25V
6K
PC
516
10U
_0805_25V
6K
12
PL501
FBMA-L11-453215800LMA90T_2P
@EMC@ PL501
FBMA-L11-453215800LMA90T_2P
@EMC@1 2
PC511
0.1U_0402_25V6
PC511
0.1U_0402_25V6
12
PC
518
10U
_0805_25V
6K
@P
C518
10U
_0805_25V
6K
@
12
PR536
0_0402_5%
PR536
0_0402_5%12
4.7_1206_5%
PR522
[email protected]_1206_5%
PR522
EMC12UwithD@
PR519
1_0603_5%
PR519
1_0603_5%
12
PR5354.75K_0402_1%
PR5354.75K_0402_1%
1 2
PC
515
10U
_0805_25V
6K
PC
515
10U
_0805_25V
6K
12
PR
529
11
0_
04
02
_1
%P
R529
11
0_
04
02
_1
%
12
0.1U_0402_25V6
PC521
[email protected]_0402_25V6
PC521
EMC12UwithD@
PR
505
10K
_0402_5%
PR
505
10K
_0402_5%
12
PR
504
36.5
K_0402_1%
PR
504
36.5
K_0402_1%
12
PR5310_0402_5%
PR5310_0402_5%
1 2
PR
506
39K
_0402_1%
PR
506
39K
_0402_1%
12
PR513
75_0402_1%
@ PR513
75_0402_1%
@1 2
PR51039K_0402_5%~N
PR51039K_0402_5%~N
12
PC
521
0.1
U_0402_25V
6@
EM
C@
PC
521
0.1
U_0402_25V
6@
EM
C@
12
PR
503
681K
_0402_1%
PR
503
681K
_0402_1%
12
PR523
10K_0402_5%
PR523
10K_0402_5%
1 2
PR5200_0402_5%
PR5200_0402_5%
1 2
PC504
0.1U_0402_25V6
PC504
0.1U_0402_25V6
1 2
+
PC
519
100U
_D
_20V
M_R
55M
+
PC
519
100U
_D
_20V
M_R
55M
1
2
680P_0603_50V7K
PC508
EMC12UwithD@680P_0603_50V7K
PC508
EMC12UwithD@
PC
501
.1U
_0402_16V
7K
PC
501
.1U
_0402_16V
7K
12
PR5242M_0402_1%@ PR5242M_0402_1%@
1 2
PU500
TPS51624RSM_QFN32_4X4
PU500
TPS51624RSM_QFN32_4X4
SLE
WA
15
VB
AT
16
TH
ER
M14
GFB23
PU321
CO
MP
26
VC
LK
31
V5A
28
DR
OP
25
ALE
RT
#32
VFB24
N/C22
GN
D33
GN
D29
PGOOD3
VR
_H
OT
#30
VR
EF
27
VDIO1VDD2
N/C4PWM25PWM16SKIP#7VR_ON8
IMO
N13
OC
P-I
12
B-R
AM
P11
F-I
MA
X10
O-U
SR
9CSP2
20
CSP117
CSN219 CSN118
PH
501
10K
_0402_1%
_T
SM
0A
103F
34D
1R
ZP
H501
10K
_0402_1%
_T
SM
0A
103F
34D
1R
Z
12
PC
510
1U
_0603_10V
7K
PC
510
1U
_0603_10V
7K
12
PC503
1000P_0402_50V7K
PC503
1000P_0402_50V7K1 2
PR
515
3.0
1K
_0
40
2_
1%
PR
515
3.0
1K
_0
40
2_
1% 1
2
PR52610_0603_1%
PR52610_0603_1%
12
PR521
4.22K_0402_1%
PR521
4.22K_0402_1%
1 2PC506
100P_0402_50V8J
@ PC506
100P_0402_50V8J
@1 2
PC507
0.33U_0603_10V7K
PC507
0.33U_0603_10V7K 12
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DELL CONFIDENTIAL/PROPRIETARY
CHARGER_SMBCLK
CHARGER_SMBDAT
pull up 10K in HW side (R827 R828)
Near PL701
TYP MAX
H/S Rds(on) 7.4mohm , 8.8mohm
L/S Rds(on) 2.6mohm , 3.1mohm
Choke DCR 5.8mohm , 7.0mohm
AC Det
Max:16.82V
Typ :16.54V
Min :16.26V
CS
SN
_1
CS
SP
_1
+DCIN
BQ
24
77
0_
RE
GN
BQ
24
77
0_
RE
GN
CHARGER_CELL_PIN
CHG_LGATE
CHG_SW
CHG_UGATE
BQ24770_REGN
CHG_BTS CHG_BTS_C
+P
WR
_S
RC
CH
G_
SN
UB
CMPOUT
CMPIN
CMPOUT
CMPIN
BQ24770_REGN
+VCHGR
CHAGER_SRC+PWR_SRC_AC
GNDA_CHG
GNDA_CHG
+SDC_IN
+DC_IN_SS
GNDA_CHGGNDA_CHG
GNDA_CHGGNDA_CHG
+DOCK_PWR_BAR
+DC_IN_SS
+SDC_IN
GNDA_CHG
GNDA_CHG
GNDA_CHG
GNDA_CHG
+PBATT
+PWR_SRC
+DC_IN
+3.3V_ALW
+PBATT
GNDA_CHG
DOCK_DCIN_IS- <34>
DOCK_DCIN_IS+ <34>
CSS_GC<47>DC_BLOCK_GC <47>
DK_CSS_GC <47>
CHARGER_SMBCLK<36>
CHARGER_SMBDAT<36>
ACAV_IN<36,47>
I_ADP<36>
I_BATT<36>
I_SYS<36>
H_PROCHOT#<9,36,45>
BATDRV# <47>
ACAV_IN_NB<36,47>
PBAT_PRES#<36,40,47>
/BATPRES<47>
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
Charger
46 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
Charger
46 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
Charger
46 53Wednesday, March 19, 2014
Compal Electronics, Inc.
PR7224.02K_0402_1%
PR7224.02K_0402_1%1 2
PR713100K_0402_1%
PR713100K_0402_1%
12
PR
72
64
.7_
12
06
_5
%@
EM
C@
PR
72
64
.7_
12
06
_5
%@
EM
C@1
2
PC7280.1U_0402_25V6
@ PC7280.1U_0402_25V6
@
1 2
PC
73
20
.1U
_0
40
2_
25
V6
@E
MC
@P
C7
32
0.1
U_
04
02
_2
5V
6@
EM
C@
12
PC711
0.1U_0402_25V6
PC711
0.1U_0402_25V6
12
PR714 0_0402_5%PR714 0_0402_5%1 2
PD705
SDMK0340L-7-F_SOD323-2~D
PD705
SDMK0340L-7-F_SOD323-2~D
12
PR7280_0402_5%
PR7280_0402_5%1 2
PR74010K_0402_1%PR74010K_0402_1%
12
PC7260.1U_0402_25V6
PC7260.1U_0402_25V6
1 2
PU700
BQ24777RUYR_WQFN28_4x4
PU700
BQ24777RUYR_WQFN28_4x4
HIDRV26
SRP20
PHASE27
/BATDRV18
SDA11
IDCHG8
AC
DR
V4
VCC28
CMSRC3
ACDET6
SCL12
ACOK5
IADP7
BTST25
BAT17
CMPIN13
REGN24
GND22
AC
P2
SRN19
NC21
LODRV23
ISYS9
/PROCHOT10
AC
N1
CMPOUT14
/BATPRES15
CELL16
PWPD29
PR
70
6100K
_0402_1%
PR
70
6100K
_0402_1%
12
PR703100_0402_1%
PR703100_0402_1%
12
PR702
0_0402_5%
PR702
0_0402_5%
1 2
PR7251K_0402_1%
PR7251K_0402_1%
12
PR799
10K_0402_1%
PR799
10K_0402_1%
1 2
PR7383M_0402_5%
PR7383M_0402_5%
12
PC
71
20
.04
7U
_0
60
3_
25
V7
K~
DP
C7
12
0.0
47
U_
06
03
_2
5V
7K
~D 1
2
PR
78
820K
_0402_1%
PR
78
820K
_0402_1%
12
PR71149.9K_0402_1%
PR71149.9K_0402_1%
12
PC
72
20
.1U
_0
60
3_
25
V7
K@
EM
C@
PC
72
20
.1U
_0
60
3_
25
V7
K@
EM
C@
12
G
DS
PQ703ASI3993CDV-T1-GE3_TSOP6
G
DS
PQ703ASI3993CDV-T1-GE3_TSOP6
1
65
PR
70
7100K
_0402_1%
PR
70
7100K
_0402_1% 1
2
PR7122.2_0603_5%
PR7122.2_0603_5%1 2
PC
72
31
0U
_0
80
5_
25
V6
KP
C7
23
10
U_
08
05
_2
5V
6K
12
1000P_0603_50V7K
PC721
EMC12UwithD@1000P_0603_50V7K
PC721
[email protected]_0402_25V6
PC732
[email protected]_0402_25V6
PC732
EMC12UwithD@
PC710
1U_0603_10V6K
PC710
1U_0603_10V6K
1 2
PD704
SDMK0340L-7-F_SOD323-2~D
PD704
SDMK0340L-7-F_SOD323-2~D
12
PC7270.1U_0402_25V6
PC7270.1U_0402_25V6
1 2
PC737100P_0402_50V8J
PC737100P_0402_50V8J
12
G
DS
PQ703BSI3993CDV-T1-GE3_TSOP6
G
DS
PQ703BSI3993CDV-T1-GE3_TSOP6
3
42
PR729154K_0402_1%
@ PR729154K_0402_1%
@
12
PC
70
72
2U
_0
80
5_
25
V6
M
@
PC
70
72
2U
_0
80
5_
25
V6
M
@
12
PC
71
91
00
P_
04
02
_5
0V
8J
PC
71
91
00
P_
04
02
_5
0V
8J
12
PC
71
52
2U
_0
80
5_
25
V6
MP
C7
15
22
U_
08
05
_2
5V
6M
12
PC
72
41
0U
_0
80
5_
25
V6
KP
C7
24
10
U_
08
05
_2
5V
6K
12
4.7_1206_5%
PR726
[email protected]_1206_5%
PR726
EMC12UwithD@
PC
70
51
0U
_0
80
5_
25
V6
KP
C7
05
10
U_
08
05
_2
5V
6K
12
PR7010.01_1206_1%
PR7010.01_1206_1%
1
3
4
2
PC741100P_0402_50V8J
PC741100P_0402_50V8J1
2
PR716 0_0402_5%PR716 0_0402_5%1 2
PR737649K_0402_1%
PR737649K_0402_1%
12
PR700
0_0402_5%
PR700
0_0402_5%
1 2
AO
N6970_D
FN
5X
6D
-8-7
PQ
704
AO
N6970_D
FN
5X
6D
-8-7
PQ
704
S2
4
S2
5G
11
S2
3
G2
6
D1
2
D2/S17
PC
70
00
.1U
_0
60
3_
25
V7
K
@
PC
70
00
.1U
_0
60
3_
25
V7
K
@
12
PC7020.1U_0402_25V6
PC7020.1U_0402_25V6
1 2
PT2@ PAD~DPT2@ PAD~D
PR70810_1206_5%
PR70810_1206_5%
12
PC7030.1U_0402_25V6
PC7030.1U_0402_25V6
1 2
PC
72
51
0U
_0
80
5_
25
V6
K
@
PC
72
51
0U
_0
80
5_
25
V6
K
@
12
PJP700
PAD-OPEN 1x2m~D
PJP700
PAD-OPEN 1x2m~D
21
PR7210.01_1206_1%
PR7210.01_1206_1%
1
3
4
2
G
S
DPQ701NTR4502PT1G_SOT23-3G
S
DPQ701NTR4502PT1G_SOT23-3
2
13
PL7012.2UH_12A_20%
PL7012.2UH_12A_20%
12
PR715154K_0402_1%
PR715154K_0402_1%
12
PC
71
81
00
P_
04
02
_5
0V
8J
PC
71
81
00
P_
04
02
_5
0V
8J
12
PD702
SDMK0340L-7-F_SOD323-2~D
PD702
SDMK0340L-7-F_SOD323-2~D
12
PC
71
42
2U
_0
80
5_
25
V6
MP
C7
14
22
U_
08
05
_2
5V
6M
12
PR72310_0603_1%
PR72310_0603_1%
1 2
PR
70
40_0402_5%
PR
70
40_0402_5%
12
PC7291U_0603_25V6K
PC7291U_0603_25V6K
1 2
PL7001UH_PCMB042T-1R0MS_4.5A_20%
EMC@ PL7001UH_PCMB042T-1R0MS_4.5A_20%
EMC@
12
PC
70
41
0U
_0
80
5_
25
V6
KP
C7
04
10
U_
08
05
_2
5V
6K
12
PR720 0_0402_5%PR720 0_0402_5%1 2
PC
71
72
2U
_0
80
5_
25
V6
MP
C7
17
22
U_
08
05
_2
5V
6M
12
PC
70
82
2U
_0
80
5_
25
V6
M
@
PC
70
82
2U
_0
80
5_
25
V6
M
@
12
PC
71
62
2U
_0
80
5_
25
V6
MP
C7
16
22
U_
08
05
_2
5V
6M
12
PQ700 V30415-T1-GE3 1P POWERPAK1212-8PQ700 V30415-T1-GE3 1P POWERPAK1212-8
352
4
1
PC70910U_0805_25V6K
PC70910U_0805_25V6K
12
PR743
0_0402_5%
PR743
0_0402_5%
12
PR745100K_0402_1%
PR745100K_0402_1%
12
PR7090_0402_5%
PR7090_0402_5%
12
PC
71
32
20
0P
_0
40
2_
50
V7
K@
EM
C@
PC
71
32
20
0P
_0
40
2_
50
V7
K@
EM
C@
12PT1@ PAD~DPT1@ PAD~D
PC
70
62
2U
_0
80
5_
25
V6
M
@
PC
70
62
2U
_0
80
5_
25
V6
M
@
12
PR
71
02
94
K_
04
02
_1
%P
R7
10
29
4K
_0
40
2_
1%
12
2200P_0402_50V7K
PC713
EMC12UwithD@2200P_0402_50V7K
PC713
EMC12UwithD@
PR
70
5
0_0402_5%
PR
70
5
0_0402_5%
12
G
S
D
PQ702NTR4502PT1G_SOT23-3
G
S
D
PQ702NTR4502PT1G_SOT23-3
2
13
PC
72
11
00
0P
_0
60
3_
50
V7
K@
EM
C@
PC
72
11
00
0P
_0
60
3_
50
V7
K@
EM
C@
12
PR718 0_0402_5%PR718 0_0402_5%1 2
PR717 0_0402_5%PR717 0_0402_5%1 2
PJP701
PAD-OPEN1x1m
PJP701
PAD-OPEN1x1m
1 2
PC7011U_0603_25V6K
PC7011U_0603_25V6K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
Purpose: Trigger PROCHOT# when active battery is removed from system. Allows EC to re-establish system performance for batterynext in line.
Purpose: Turn on the PQ817 for primary or module bay battery to provide power to dock side without AC exist.
Vth=0.5-1.5V
DK_AC_OFF
SL_BAT_PRES#
ER
C2
ERC1
P33ALW
ACAVDK_SRCACAVDK_SRC
ERC3
DK_AC_OFF_ENCD3301_SDC_IN
3301_PWRSRC
3301_ACAV_IN_NB
STSTART_DCBLOCK_GC
P50ALW
CD_PBATT_OFF
DK
_P
WR
BA
RD
C_IN
_S
S
ACAVIN
CD3301_DCIN
P33ALW2
EN_DK_PWRBAR
ST
ST
AR
T_
DC
BL
OC
K_
GC
ACAV_IN#
ACAV_IN#
+PWR_SRC_AC
+DC_IN_SS
+DC_IN
+SDC_IN
+3.3V_ALW2
+PWR_SRC_AC
+3.3V_ALW
+5V_ALW+3.3V_ALW2
+PBATT
+DOCK_PWR_BAR
+3.3V_ALW
+VCHGR
+3.3V_ALW2+3.3V_ALW2
+DOCK_PWR_BAR
+3.3V_ALW
+3.3V_ALW2
+NBDOCK_DC_IN_SS
+3.3V_ALW2
+3.3V_ALW
+PBATT
+NBDOCK_DC_IN_SS
+DC_IN_SS
+3.3V_ALW
+3.3V_ALW
CSS_GC<46>DK_CSS_GC<46>
SLICE_BAT_ON <35>
ACAV_IN_NB <36,46>
DOCK_AC_OFF_EC <35>
SLICE_BAT_PRES# <34,35,40>
SOFT_START_GC<40>
ACAV_DOCK_SRC#<34>
DC_BLOCK_GC<46>
ACAV_IN<36,46,47>
DOCK_AC_OFF <34>
EN_DOCK_PWR_BAR <35>
BATDRV#<46>
DOCK_DET# <34,35,47>
DIS_BAT_PROCHOT#<35>
ACAV_IN<36,46,47>
DOCK_DET#<34,35,47>
AC_DIS<36,40>
/BATPRES <46>
PBAT_PRES#<36,40,46>
Title
Size Document Number Rev
Date: Sheet of
LA-A901P0.3
Selector
47 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P0.3
Selector
47 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P0.3
Selector
47 53Wednesday, March 19, 2014
Compal Electronics, Inc.
PR857 0_0402_5%PR857 0_0402_5%
1 2
PC809
1500P_0402_50V7K
@PC809
1500P_0402_50V7K
@
12
PR864100K_0402_5%
PR864100K_0402_5%
12
PR826
100K_0402_5%
PR826
100K_0402_5%
12
PU804
TC7SH08FU_SSOP5~D
PU804
TC7SH08FU_SSOP5~D
B1
A2
G3
O4
P5
PR8120_0402_5%
PR8120_0402_5%1 2
PU806
TC7SH08FU_SSOP5~D
PU806
TC7SH08FU_SSOP5~D
B1
A2
G3
O4
P5
PR8470_0402_5%
PR8470_0402_5%1 2
PQ
806A
DM
N65D
8LD
W-7
_S
OT
363-6
PQ
806A
DM
N65D
8LD
W-7
_S
OT
363-6
61
2
PR8420_0402_5%
PR8420_0402_5%1 2
PQ800SI4835DDY-T1-GE3_SO8
PQ800SI4835DDY-T1-GE3_SO8
3 65
78
2
4
1 PR8110_0402_5%
PR8110_0402_5%1 2
PD808
PDS5100H-13_POWERDI5-3
PD808
PDS5100H-13_POWERDI5-3
2 31
PR819
100K_0402_5%
PR819
100K_0402_5%
1 2
PR851
0_0402_5%
PR851
0_0402_5%
1 2
PR829
100K_0402_5%
PR829
100K_0402_5%
12
PR815
100K_0402_5%
PR815
100K_0402_5%
12
PD813
SDMK0340L-7-F_SOD323-2~D
PD813
SDMK0340L-7-F_SOD323-2~D
12
PR8600_0402_5%
PR8600_0402_5%1 2
PC
817
0.1
U_0402_25V
4Z
~D
@
PC
817
0.1
U_0402_25V
4Z
~D
@
12
PR814330K_0402_5%
PR814330K_0402_5%
12
PR874
1M_0402_5%
PR874
1M_0402_5%
1 2
PC8130.1U_0603_50V4Z
PC8130.1U_0603_50V4Z
12
PR835
47_0805_5%~D
PR835
47_0805_5%~D
1 2
PR8540_0402_5%
PR8540_0402_5%1 2
PD817
BAT54CW_SOT323-3
PD817
BAT54CW_SOT323-3
3
2
1
PQ810FDS6679AZ-G_SO8PQ810FDS6679AZ-G_SO8
36 578
2
4
1
PR845 0_0402_5%PR845 0_0402_5%
1 2
PQ
817B
DM
N65D
8LD
W-7
_S
OT
363-6
PQ
817B
DM
N65D
8LD
W-7
_S
OT
363-6
3
5
4
PR850 0_0402_5%PR850 0_0402_5%
1 2
PR828
10K_0402_5%
PR828
10K_0402_5%1 2
PR858
1M_0402_5%
PR858
1M_0402_5%
1 2
PR846
100K_0402_5%
PR846
100K_0402_5%
1 2
PR855 0_0402_5%PR855 0_0402_5%
1 2
PR8320_0402_5%
PR8320_0402_5%1 2
PR827
100K_0402_5%
PR827
100K_0402_5%
1 2
PR830100K_0402_5%
PR830100K_0402_5%
12
PD800PDS5100H-13_POWERDI5-3
PD800PDS5100H-13_POWERDI5-3
2
31
PR
818
100K
_0402_5%
PR
818
100K
_0402_5%
12
2
13
PQ829DMG2301U-7 1P SOT23-3
2
13
PQ829DMG2301U-7 1P SOT23-3
2
13
PR853
0_0402_5%
PR853
0_0402_5%
12
PQ813A
DMN65D8LDW-7_SOT363-6
PQ813A
DMN65D8LDW-7_SOT363-6
61
2
PQ813B
DMN65D8LDW-7_SOT363-6
PQ813B
DMN65D8LDW-7_SOT363-6
35
4
PR8430_0402_5%
PR8430_0402_5%1 2
PR8160_0402_5%@ PR8160_0402_5%@
1 2
PQ826
FDMC6679AZ_MLP8-5
PQ826
FDMC6679AZ_MLP8-5
4
5
1 2 3
PQ815
FDS6679AZ-G_SO8
PQ815
FDS6679AZ-G_SO8
36 578
2
4
1
PR813
100K_0402_5%
PR813
100K_0402_5%
12
PR8480_0402_5%
PR8480_0402_5%1 2
PR895
0_0402_5%
PR895
0_0402_5%
1 2
PR844
10K_0402_5%
PR844
10K_0402_5%
12
PR8380_0402_5%
PR8380_0402_5%1 2
2
1
3
PQ
814
NT
R4502P
T1G
_S
OT
23-3
2
1
3
PQ
814
NT
R4502P
T1G
_S
OT
23-3
2
13
PU800
CD3301BRHHR_QFN36_6X6~D
PU800
CD3301BRHHR_QFN36_6X6~D
DC_IN1
SS_GC2
ERC13
ACAVDK_SRC4
GND5
SDC_IN6
DC_BLK_GC7
ACAV_IN8
SS
_D
CB
LK
_G
C1
6
CS
S_
GC
10
DK
_C
SS
_G
C1
1
ER
C3
12
ER
C2
13
GN
D1
4
PW
R_
SR
C1
5
BLKNG_MOSFET_GC20SL_BAT_PRES#21DK_AC_OFF_EN22GND23ACAV_IN_NB24DK_AC_OFF_EN25PBATT_OFF26P50ALW27
PB
att
+2
8D
SC
HR
G_
MO
SF
ET
_G
C2
9B
LK
_M
OS
FE
T_
GC
30
NC
31
DK
_P
WR
BA
R3
3D
C_
IN_
SS
34
CH
AR
GE
RV
R_
DC
IN3
5
P33ALW29
EN
_D
K_
PW
RB
AR
17
P3
3A
LW
18
TP37
NBDK_DCINSS19
NC
36
GN
D3
2
PC807
0.47U_0805_25V6K
PC807
0.47U_0805_25V6K
1 2
G
D
SPQ
816
DM
N65D
8LW
-7_S
OT
323-3
G
D
SPQ
816
DM
N65D
8LW
-7_S
OT
323-3
2
13
PC810
0.1U_0402_10V7K
PC810
0.1U_0402_10V7K
12
PR8310_0402_5%
PR8310_0402_5%1 2
PC
815
0.1
U_0603_25V
7K
PC
815
0.1
U_0603_25V
7K
12
PR8590_0402_5%
PR8590_0402_5%1 2
PD815
BAT54CW_SOT323-3
PD815
BAT54CW_SOT323-3
3
2
1
G
D
S
PQ832
DMN65D8LW-7_SOT323-3
G
D
S
PQ832
DMN65D8LW-7_SOT323-32
13
PC
816
0.0
47U
_0603_25V
7M
PC
816
0.0
47U
_0603_25V
7M
12
PQ
817A
DM
N65D
8LD
W-7
_S
OT
363-6
PQ
817A
DM
N65D
8LD
W-7
_S
OT
363-6
61
2
PC8050.1U_0402_10V7K
PC8050.1U_0402_10V7K
1 2
PR810
100K_0402_5%
PR810
100K_0402_5%
12
PR
822
10K
_0402_5%
PR
822
10K
_0402_5%
12
PQ
806B
DM
N65D
8LD
W-7
_S
OT
363-6
PQ
806B
DM
N65D
8LD
W-7
_S
OT
363-6
3
5
4
PR8630_0402_5%
@ PR8630_0402_5%
@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DELL CONFIDENTIAL/PROPRIETARY
961
Based on _RF Cheng. Hill
鄭鄭鄭(11257) for PT 20131107
+VCC_CORE
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
PROCESSOR DECOUPLING
48 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
PROCESSOR DECOUPLING
48 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
PROCESSOR DECOUPLING
48 53Wednesday, March 19, 2014
Compal Electronics, Inc.
+
PC
96
62
20
U 2
.5V
Y D
2 E
SR
9M
H1
.9 S
X
+
PC
96
62
20
U 2
.5V
Y D
2 E
SR
9M
H1
.9 S
X
1
2
PC90322U_0805_6.3V6MPC90322U_0805_6.3V6M
1
2
0.1U_0402_25V6
PC311
[email protected]_0402_25V6
PC311
EMC14UwithD@
4.7_1206_5%
PR726
[email protected]_1206_5%
PR726
EMC14UwithD@680P_0603_50V7K
PC721
EMC14UwithD@680P_0603_50V7K
PC721
EMC14UwithD@
PC9152.2U_0805_10V6K
PC9152.2U_0805_10V6K
1
2
4.7_1206_5%
PR522
[email protected]_1206_5%
PR522
EMC14UwithD@
PC90222U_0805_6.3V6MPC90222U_0805_6.3V6M
1
2
680P_0603_50V7K
PC508
EMC14UwithD@680P_0603_50V7K
PC508
EMC14UwithD@
2200P_0402_50V7K
PC105
EMC14UwithD@2200P_0402_50V7K
PC105
EMC14UwithD@
PC91722U_0805_6.3V6M
@PC91722U_0805_6.3V6M
@
1
2
PC90122U_0805_6.3V6MPC90122U_0805_6.3V6M
1
2
0.1U_0402_25V6
PC106
[email protected]_0402_25V6
PC106
EMC14UwithD@
PC90022U_0805_6.3V6MPC90022U_0805_6.3V6M
1
2
PC91422U_0805_6.3V6MPC91422U_0805_6.3V6M
1
2
2200P_0402_50V7K
PC520
EMC14UwithD@2200P_0402_50V7K
PC520
EMC14UwithD@
PC91322U_0805_6.3V6MPC91322U_0805_6.3V6M
1
2
2200P_0402_50V7K
PC203
EMC14UwithD@2200P_0402_50V7K
PC203
EMC14UwithD@
0.1U_0402_25V6
PC521
[email protected]_0402_25V6
PC521
EMC14UwithD@
2200P_0402_50V7K
PC713
EMC14UwithD@2200P_0402_50V7K
PC713
EMC14UwithD@
PC9162.2U_0805_10V6K
PC9162.2U_0805_10V6K
1
2
0.1U_0402_25V6
PC206
[email protected]_0402_25V6
PC206
EMC14UwithD@
PC90422U_0805_6.3V6MPC90422U_0805_6.3V6M
1
2
2200P_0402_50V7K
PC300
EMC14UwithD@2200P_0402_50V7K
PC300
EMC14UwithD@
0.1U_0402_25V6
PC732
[email protected]_0402_25V6
PC732
EMC14UwithD@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Version Change List ( P. I. R. List )
Item Issue DescriptionDateRequest
Owner Solution Description Rev.Page# Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
X01
Remove PC808, PC811, PC812 , PC814, PD806, PD807, PD811, PD814, PD819,
PD821, PQ801, PQ807, PQ809, PQ811, PQ812, PQ818, PQ821, PQ828, PQ830,
PQ831, PR802, PR804, PR808, PR813, PR815, PR816, PR817, PR821, PR823,
PR825, PR834, PR836, PR837, PR839, PR849, PR852, PR861, PU805, PU807,
PU808
1 10/8 Compal
2 X01
3 X01
4 X01
5 X01
Remove slice battery support circuit
6 X01
7 X01
8 X01
X019
10
Selector47
45 VCC_CORE 10/8 Compal
Remove PC923, PC924, PC925, PC926, PC927, PC928, PC929, PC930, PC931,
PC940, PC941, PC943, PC946, PC947, PC948
Add PC966To prevent acoustic noise issue
42 1.35V_MEN 10/8 RICHTEK To prevent IC damage Add PR204
46 Charger 10/8 Compal Fine tune divider voltageChange PR713, PR725 to 100k
Change PR715, PR729 to 154k
41,43,44+1.05V_M
+1.5V_RUN
+3V/+5V10/22 Compal To improve the ability of anti-noise
46 Charger 10/25 CompalChange /BATPRES pin control net from /BATPRES
to PBAT_PRES#
45 VCC_CORE 10/31 Compal Fine tune IMON
Pop PR728
Depop PR816
ALL ALL 10/31 Compal RF request Add PC521, PC206, PC106, PC311, PC732 ( 0.1uF )
ALL ALL 10/31 Compal RF requestPop PR111,PC111,PR112,PC114,PR203,PC208,PR305,PC301,PR522,PC508,
(4.7ohm, 680pF)
Change PR307 to 7.5k
Change PR310, PR102, PR104, PR403 to 10k
Change PR100 to 6.49k
Change PR101 to 15k
Change PR402 to 8.66k
Add PR518, PR524, PR525
46 Charger 10/31 Compal PR703 change to 100ohmTo prevent VCP trigger PROCHOT# X01
Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
PWR P.I.R (1/1)
49 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
PWR P.I.R (1/1)
49 53Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A901P 0.3
PWR P.I.R (1/1)
49 53Wednesday, March 19, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
TitlePage# Rev.Solution DescriptionRequest
OwnerDate Issue DescriptionItem
Version Change List ( P. I. R. List )
HW 2013/10/81 COMPAL 0.2(X01)
0.2(X01)
0.2(X01)
0.2(X01)
2
3
4
5
6 Follow intel reference circuit. Add CC100, RC300 on CPU pin AC4, net name is PM_TEST_RST
Dell drop POA function.
Dell drop POA function.remove POA_WAKE# off page symbol
remove POA_ON/OFF#,make UE2.B62 to be NC pin
Change JUSH1 from 26 pin to 20 pin, pin define follow E5
2013/10/9 COMPAL24 HW correct HDMI schematic error. swap HDMI LANE0 & LANE2 BUS
0.2(X01)
IC version changed.COMPAL2013/10/9HW22
Follow EMC suggestion
Change LI1,LI2,LI3,LI4,LI5,LI6,LI7,LI8,LI9,LV3,LV6,LV10,LV12,LV27
From SM070003K00 (S COM FI_ CHILISIN CMMI21T-900Y-N)
To SM070003Y00 (S COM FI_ MURATA DLW21HN900HQ2L)
0.2(X01)
COMPAL2013/10/9HW23
reserved for S3 within 2s , system shutdown
issue debug.add RC26, reserved RC27.
0.2(X01)
COMPAL2013/10/9HW9
board ID change. RE79 change to 130KCOMPAL2013/10/9HW36
0.2(X01)
COMPALHW
36
0.2(X01)
0.2(X01)
COMPAL
COMPAL
2013/10/8
2013/10/8
HW
HW
27
36
6
7
8
9
10 2013/10/14 COMPAL follow intel latest design guide.pop RE56 and change from 8.2K to 10K , it's RESET_OUT# pull down
resistor
0.2(X01)
24
HW
11
2013/10/9
VMM2320 circuit change:
1. UV8 from VMM2320 change to VMM 2330 (SA00007G800)
2. UV8 pin J3, E5 to +1.05V_RUN
3. VMM_SPI_WP# reserved RV517, 2.2K resistor PU to +3.3V_RUN_VMM
4. VMM_GPIO4,reserved RV518, 2.2K resistor PU to +3.3V_RUN_VMM
5. VMM_GPIO5 reserved RV519, 2.2K resistor PU to +3.3V_RUN_VMM
6. UV8 pin B5, B6 change to +3.3V_RUN_VMM
7. LP_CTL reserved RV516, 2.2K resistor PU to +3.3V_RUN_VMM
8. Depop RV73
HW COMPAL RF requirement. add CC14, CC15 and move CC12, CC13 to behind the resistor (RC72)7 2013/10/16 0.2(X01)
HW COMPAL
change all ESD diode CPN
change DI2, DI3, DI5, DV4 from SCA00001100(S ZEN ROW PJDLC05C 3P C/A
SOT23) to SC600001600(S DIO ROW AZC199-02S.R7G C/C SOT23 ESD)
change DI1,DI6,DI4 from SC300002800(S DIO(BR) TVWDF1004AD0 DFN ESD)
to SC300002C00(S DIO(BR) L05ESDL5V0NA-4 SLP2510P8 ESD)
change DA1,DA2,DA3,DA6,DA7 from SCA00001L00(S ZEN ROW L30ESDL5V0C3-2
C/A SOT23 ESD) to SCA00002900(S ZEN ROW L03ESDL5V0CC3-2 C/A SOT-23
ESD)
2013/10/1720,23,31,32 follow ESD recommend list.12
0.2(X01)power doesn't split VPRO & NPRO BOM. add RZ41, RZ42, reserve it for VPRO & NVPRO option.2013/10/17 COMPALHW3813
0.2(X01)SSI design will cause LED behavior error. QL1 Pin2,5 & QL2 Pin2 change from MASK_BASE_LEDS# to SYS_LED_MASK#2013/10/17 COMPALHW3914
SATA ciruit issue Swap mSATA P & N
Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (1/3)
60 70Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (1/3)
60 70Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (1/3)
60 70Wednesday, March 19, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
TitlePage# Rev.Solution DescriptionRequest
OwnerDate Issue DescriptionItem
Version Change List ( P. I. R. List )
To solve Line-on HDD dirty shut down issue.
follow Dell requirement.
UZ8 Pin2 change from +3.3V_ALW to 3.3V_RUN
Add back SUS_ON, change control pin from SUS_ON to SIO_SLP_S4#
1. UZ8.3 from SIO_SLP_S4# to SUS_ON
2. UE2.B23 → SUS_ON_EC , RPE10.2 → SUS_ON
3. add RE282, RE281, RE280, RE279
4. UE2.B9 → RUN_ON_EC
0.2(X01)
0.2(X01)
COMPAL
COMPAL
2013/10/17
2013/10/17
HW
HW
20
28, 36, 38
HW COMPAL 0.2(X01)add GPIO pin for DIMM quantity detection. add DIMM_DET on UC1.U4? to replace PCH_GPIO48 ,Reserve RC302 &RC3032013/10/2412
debug usage. add RC301COMPAL 0.2(X01)2013/10/246 HW
reserve it to prevent PCH_PLTRST# floating
when power onadd RC304, 100K pull down, on PCH_PLTRST#_EC 0.2(X01)9 HW 2013/10/28 COMPAL
it's designed for E5 Goliad, E6 GMLK doesn't
need.remove RZ1COMPAL 0.2(X01)HW 2013/10/2923
HW 2013/10/29 COMPAL To solve WWAN can not detec issue. Add RZ50, 100k pull up for WWAN_PWR_EN 0.2(X01)30
2013/10/29 COMPAL To solve backdrive issue. Change TPM_PIRQ# pull up ( RC247) to +3.3V_RUN from +3.3V_ALW_PCH 0.2(X01)12 HW
15
16
17
18
19
20
21
22
23
24
25
26
27
6, 7, 22,
28follow xtal vender suggest 2013/10/23 COMPAL
1 CC1 &CC2 change from 18PF to 3PF
2 CC8 & CC11 change from 18PF to 15PF
3 CL13 & CL14 change from 33PF to 27PF
4 RV81 change from 0 ohm to 2.2K & CV113 change to 18PF
HW 0.2(X01)
0.2(X01)add PJP36, depop QZ6, QZ10, RZ16, RZ5, CZ25, CZ38Dell doesn't support MODPHY.COMPAL2013/10/30HW30
2013/11/2 0.2(X01)7
2013/11/2
SMBUS Pull High Add RN3&RN4 pull high to +3.3V_RUN for DDR_XDP_WAN_SMBDAT/SMBCLKHW COMPAL
COMPAL 0.2(X01)HW EMC request. Add RA42, RA43.21
add CA12, CA13
change DA1, DA2, DA3, DA4 from GNDA to GND
follow vender suggestion. It's for 15KV
ESD fail issue.0.2(X01)COMPAL2013/11/05HW21
GPIO 14 is sus power well, it has risk to
cause back drive.0.2(X01)move TPM_PIRQ# from PCH_GPIO14 to PCH_GPIO17, add T21 on PCH_GPIO14COMPAL2013/11/05HW1228
0.3(X01)1.UA1 pin22 add RA45 0 ohm PU to +3.3V_RUN_AUDIO
2.UA1 pin21 add RA44 100k ohm to GNDfollow vender suggest to solve "Bo" noiseHW21 COMPAL2013/12/1739
1.RPC8 change from 2.2k to 10k
2.UC1.F2 &RPC8.3 change name from I2C0_SDA to PCH_GPIO4
3.UC1.F3 &RPC8.4 change name from I2C0_SCL to PCH_GPIO5
4.UC1.G4 &RPC8.1 change name from I2C1_SDA_VMM to PCH_GPIO6
5.UC1.F1 &RPC8.2 change name from I2C1_SCL_VMM to PCH_GPIO7
6.RPV2.1 connect to I2C1_SDA_VMM
8.RPV2.2 connect to I2C1_SCL_VMM
9.Depop RV516, CV116, CV117
0.3(X01)follow vender suggest22 COMPALHW 2013/12/1740
Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (2/3)
61 70Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (2/3)
61 70Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (2/3)
61 70Wednesday, March 19, 2014
Compal Electronics, Inc.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
TitlePage# Rev.Solution DescriptionRequest
OwnerDate Issue DescriptionItem
Version Change List ( P. I. R. List )
29
30
31
To solve CRT display jitter issue1.LV23,LV25 change from BLM15AX102SN1D to BLM15PX181SN1D
2.CV90,CV101 change from 1uF to 10uF0.3(X01)22 COMPALHW
Base on Pre-PT RSMRST EA result22 COMPALHW0.3(X01)1.POP RE88,UZ6,RE51
2. remove QZ12,RZ48,RZ49,RZ50
2013/12/17
2013/12/17
follow vender suggestionCOMPALHW 2013/12/17
1. change LV22 , LV24
From SM01000N400 S SUPPRE_ MURATA BLM15AX102SN1D 0402
To SM01000NO00 S SUPPRE_ MURATA BLM15PX181SN1D 0402
2. change CV82, CV94 from 1uF to 10uF
3. UV8 pin D3 from +1.05V_VMM_VDDTX to +1.05V_VMM_VDD.
4. UV8 Pin H3, E10, H11 change to NC
5. Change UV8 pin B5, B6 from +3.3V_RUN_VMM to +3.3V_RUN_VDDIO"
0.3(X01)22
7 RF recommendHW COMPAL Change CC12, CC13, CC14, CC15 from 16pF to 33pF 0.3(X01)2013/12/2632
HW Intel recommend33 2013/12/27 COMPAL Change RC33, RC34 from 1k to 499 ohm7 0.3(X01)
Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (3/3)
62 70Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (3/3)
62 70Wednesday, March 19, 2014
Compal Electronics, Inc.Title
Size Document Number Rev
Date: Sheet of
LA-A971P 0.3
EE P.I.R (3/3)
62 70Wednesday, March 19, 2014
Compal Electronics, Inc.