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Italian Universities NanoElectronics
Team
ConsorzioNazionale
Interuniversitarioper la
Nanoelettronica
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Members of IU.net
Politecnico di Milano
Università di UdineUniversità di PadovaUniversità di
Modena
Università di Pisa
Università di Ferrara
Università di Roma “La Sapienza”
Università di Bologna
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Permanent scientific staffBologna: 5Ferrara: 2Milano: 4Modena: 2Padova: 2Pisa: 5Roma: 2Udine: 5Total: 27 (plus ~ 30 Ph.D. students)
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Mission of the ConsortiumDevelop collaborative research between associate Universities and other public and private Research centersFoster collaboration with industry to jointly develop new ideas and concepts, and prove them at demonstrator levelPerform studies and research commissioned by private or public entities, by exploiting the means and the know-how of the associate members of IU.netDisseminate and valorize the Consortium know-how and competences by promoting the participation of associate members to national and international research projects
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Governance• Cor Claeys
IMEC, Leuven, Belgio
• Andrea LacaitaPolitecnico di Milano
• Alessandro PaccagnellaUniversità di Padova
• Luca SelmiUniversità di Udine
• Università di Bologna –Massimo Rudan
• Università di Ferrara –Piero Olivo
• Politecnico di Milano –Alessandro Spinelli
• Università di Modena –Paolo Pavan (Chairman)
• Università di Padova –Andrea Cester
• Università di Pisa –Giuseppe Iannaccone
• Università di Roma LS –Fernanda Irrera
• Università di Udine –David Esseni
Scientific Committee
Enrico Sangiorgi
Director
Assembly
location: via Toffano 2, Bologna
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Main research lines
Nano-transistors: CMOS and post-CMOSNanoelectronic non-volatile Memories
Providing support to the development of technology platforms for micro- and nano-electronics
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Nanometric transistors
Specific activities:Architectures for nanoMOSFETSimulation of nanowire devicesMonte Carlo simulation of transport in nanoMOSFETNanowires and nanotubes transport
Physical understanding, analysis and optimization of device architectures for 32 nm node and beyond
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Electrical performance of CNT-FETsbased on atomistic simulations
Fiori et al., IEDM 2005
Efs
Efd
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Nanoelectronic NV Memories
Specific activities:Flash memoriesPhase-change memoriesNROM and SONOS MemoriesCharacterization and reliability assessmentRadiation effects on NVM performancesTechnology optimization
Assessment of innovative technologies for non-volatile nanoelectronic memories
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Phase-change memories
2001 2003 2005 2007 2009 2011 201310-3
10-2
10-1
100
32 nm
32 nm
180 nm
180 nm
130 nm
90 nm65 nm
45 nm
130 nm
90 nm
65 nm
45 nm
45 nm
65 nm
90 nm
demonstrator FLASH NOR FLASH NAND PCM
Cel
l siz
e (μ
m2 )
Year
I
V
Lacaita, EPCOS 2005
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SONOS and NROM memories
Drain Source
NO
Ohe
Gate
Channel
+-
ONO2F
Planar NROM
Larcher et al., TED 2004Arreghini et al.,INFOS 2005
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PULLing the limits of NANOcmos electronicsEC Contract N. 26828Period: 06/2006 - 05/2009Four companies (ST, Freescale, Philips, Infineon, ), four research institution (IMEC, CEA, Fraunhofer, CNRS), seventeen universities/consortia, three SMEsUniBO, UniUD, UniPI and PoliMI participating for IUNET (approx €660 000)Purpose: pulling forward CMOS Technologies: exploratory research; characterization; modelling and advance simulation; demonstration of feasibility of concepts; process modules integration; definition of specifications of advanced new equipment; demonstration of feasibility of a 32nm CMOS logic technology; exploratory action towards the 22nm node
EC Project PULLNANO
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IU.NET in PULLNANO
Role of IU.NETcoordination of WP/Cluster 6.4 «Advanced modelling and simulation»
Partners of the Cluster:IU.NETETHZTechnical University of WarsawCNRS
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PULLNANO WP6.4 Objectives
Develop advanced physical models addressing the needs foreseen for the 22nm technology node:
strained siliconadoption of different crystal orientations for the channelhigh-k gate dielectricsfluctuations of dopants, dielectric and silicon layer thickness and effects of line-edge roughness
Implement the developed models in device simulators and compare different device architectures and technological options
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EC Project EMMAEmerging Materials for Mass-storage ApplicationsPeriod: 09/2006 – 08/2009Two companies (ST, IMEC), two research institution (CNR-MDM, CNRS-L2MP) and two universities/consortia (RWTH Aachen, IUNET)PoliMI, UniPD and UniMORE participating for IUNETPurpose: demonstrating the feasibility of non volatile memories based on resistive switching for mass storage
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The EMMA conceptReversible change of resistance within a dielectric material:
Binary metal oxides (NiO, Al2O3, Nb2O5, etc.)Polymer-based materials (CuTCNQ)
Advantages:Resistivity change at the atomic scale promising for high-density and scalabilityBack-end materials 3D cross-point architectures suitable to mass storageTarget: beyond 32-nmCuTCNQ nanowires 100nm2
active cell area feasible
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National project PNRProgramma Nazionale di RicercaPeriod: 36 monthsTwo joint projects: FIRB (basic research) + FAR (industrial research)One company (STMicroelectronics), twouniversities/consortia (IUNET, UniPV), one researchinstitution (CNR)Purpose: assess and develop technologies forNVMs at the 45-32 nm nodes:
Floating-gate cells with high-K as interpoly dielectricsPhase-change memoriesNitride-based memories
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IU.NET scientific achievements
Patents: 4European Projects: 11National Projects: 10Scientific Publications
International Journals: 219International Conferences: 169
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CONCLUSIONSIU.NET has been devised to foster academic research collaboration and promote the participation of academic Partners to large European technology-oriented ProgramsThe goal of IU.NET is to leverage on high quality teams which cover a large spectrum of expertiseIf the funding scheme is successful, IU.NET nodes will define “ad hoc” laboratory facilities