Ge Semiconductor Devices
for
Cryogenic Power Electronics - IV
Electrochemical Society
Seventh International Symposium on Low Temperature Electronics
14 October 2003, Orlando, Florida
2
R. R. Ward, W. J. Dawson, L. Zhu, R. K. Kirschman
GPD Optoelectronics Corp., Salem, New Hampshire
M. J. Hennessy, E. K. Mueller
MTECH Laboratories, Ballston Lake, New York
R. L. Patterson, J. E. Dickman
NASA Glenn Research Center, Cleveland, Ohio
A. Hammoud
QSS Group Inc., Cleveland, Ohio
3
Cryogenic Power Electronics
• Semiconductor Devices (diodes and transistors)
• For Use down to 30 K and Lower
• For Power Management and Actuator Control
• For Spacecraft
• Supported by NASA Glenn Research Center
Why Use Ge?
5
Why Ge Devices?
• Si-Based Circuits Demonstrated, but only > 77 K
• Si Bipolar Devices Cease Operation < ~100 K
• Applications Require Operation < 77 K, to ~30 – 40 K
• Possible Materials for < 77 K are Ge and SiGe
• Ge Devices Can Operate to Lowest Cryogenic
Temperatures (~ 0 K)
• All Device Types – Diodes, Field-Effect Transistors,
Bipolar Transistors
Development Program
7
Development Program• Parameters
– Low power (~10 W) and medium power (~100 W)
– Temperature range 300 K to ~20 K
• Past
– Investigated existing Ge semiconductor devices at cryogenic temperatures (diodes, BJTs, JFETs)
– Designed and fabricated Ge cryogenic power diodes (P--N, 10 A, 300 V)
• Devices under Development
– MISFETs (lateral, vertical implanted, vertical epi)
– JFETs (lateral, vertical)
– BJTs (vertical implanted, vertical epi)
– IGBTs (vertical implanted, vertical epi)
Ge Cryo Power Diodes
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Ge Cryo Power DiodesP- - N Bulk Design
N– ( )
N+ implant
P+ implant Metal
Metal
Guard ring(s)
10
Ge Cryo Power Diodes - Forward Voltage
0
0.5
1
1.5
0.2 A
0.2 A Si
Vf 0.2 A
Vf 0.2 A
Vf (0.2 A)
Vf (0.2 A)
0 40 80 120 160 200 240 280 320
Temperature (K)
Commercial Ge power diodes
Si power diodes
Ge cryo power diodes (2 thick, 2 thin)
If = 0.2 A
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Ge Cryo Power Diodes - Forward Voltage
0
0.5
1
1.5
2
0 40 80 120 160 200 240 280 320
Temperature (K)
Commercial Ge power diodes
Si power diodes
Ge cryo power diodes (thick)
If = 4 A
Ge cryo power diodes (thick)
Ge cryo power diodes (thin)
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Ge Cryo Power Diodes - Forward I-V
13
Ge Cryo Power Diodes - Forward I-V
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Ge Cryo Power Diode – Forward I-V
0 0.2 0.4 0.6 0.8 10
1
2
3
4
Forward Voltage (V)
120 K
300 K
40 K
20 K
4 K80 K
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Ge Power Diodes – Reverse Breakdown
0
100
200
300
400
500
600
0 50 100 150 200 250 300
Temperature (K)
18-1-B2b
18-1-D1d
12-1-Aa
Commercial Ge power diodes
16
-12
-8
-4
0
4
8
12
0 200 400 600 800 1000 1200
Time (ns)
77 K
300 K
18-1-AaJune 2003
Ge Power Diodes – Reverse Recovery
17
-12
-8
-4
0
4
8
12
0 200 400 600 800 1000 1200
Time (ns)
77 K
300 K
18-1-B1cJune 2003
Ge Power Diodes – Reverse Recovery
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0
1
2
3
4
0 2 4 6 8 10 12
Forward Diode Current (A)
77 K
300 K
Ge Power Diodes – Reverse Recovery
19
-12
-8
-4
0
4
8
12
0 200 400 600 800 1000 1200
Time (ns)
77 K
300 K
30-1-C1bJune 2003
Ge Power Diodes – Reverse Recovery
20
-12
-8
-4
0
4
8
12
0 200 400 600 800 1000 1200
Time (ns)
77 K
300 K
30-2-AaJune 2003
Ge Power Diodes – Reverse Recovery
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Ge Cryo Power Diodes - Future
• Improved Guard-Ring Designs and Tailored Implant– Higher Vr
• Schottky Designs– Lower forward voltage
• N--P (compared to P--N)– Possible improvement in Vf and Vr– Possible improvement in speed/reverse recovery– Possible elimination of “backlash” at 4 K– Possible lower reverse leakage
Ge Cryo Power MISFETs
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Ge Cryo Power JFET or MISFET
~1.8 mm
G
S
D
S
G
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Basic Lateral Ge MISFET Design
Substrate
Source Gate
P+ implant
P substrate
Gate dielectric
N+ implant
Drain
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Ge Power MISFET at 300 K
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Ge Power MISFET at 77 K
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Ge Power MISFET at 4 K
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Basic Vertical Ge MISFET Design
Drain
Source Gate
N+ implant
N substrate
P implant
Gate dielectric
N+ implant
Two versions: double-implant (above) and epi
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Basic Vertical Ge MISFET Design
Two versions: double-implant and epi (above)
Drain
Source Gate
P+ implant
P– substrate
P+ implant
Gate dielectric
N epi
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Ge Cryo Power MISFETs - Plans
• Larger-Area and Modified Doping (for Lateral Ge)– Higher I and higher Vbk
• Vertical Designs for Ge– Higher I and higher Vbk
• Reverse Double-Implant Vertical Design for Ge– Better results than present double-implant
design
Ge Cryo Power JFETs
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Ge JFET Cross-Section (n-channel)
S Gf D
N Epitaxial LayerP+ Implant
N+ Implant
Gb
P+ Ge Substrate
Passivation
Au-Sb Ti-Au
Backside Metalization (Au)
33
Power Ge JFET at 300 K
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Power Ge JFET at 77 K
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Power Ge JFET at 4 K
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Another Power Ge JFET at 20 K
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Power JFETs - Plans
• P-Type– Complementary circuits
• Higher I and Vbk
• Vertical (SIT) Design– Higher I and higher Vbk
Ge CryoBipolar Junction Transistors
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Ge Bipolar – Double-Implant
Collector
BaseEmitter
N+ implant
N– substrate
P implant
N+ implant
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Ge Bipolar – Epitaxial
Collector
BaseEmitter
N+ implant
N– substrate
P epi
N+ implant
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Power BJTs - Plans
• Reverse Double-Implant Design for Ge– Better characteristics than present
double-implant design?
• Epitaxial Design for Ge
Ge Cryo IGBTs
43
Basic Ge IGBT Design
Collector
Emitter Gate
P+ implant
N– substrate
P implant
Gate dielectric
N+ implant
Two versions: double-implant (above) and epi
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Basic Ge IGBT Design
Two versions: double-implant and epi (above)
Collector
Emitter Gate
N+ implant
P– substrate
P+ implant
Gate dielectric
N epi
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Summary
• We Have Characterized Commercial Ge Devices
(Diodes and Bipolars) at Cryogenic Temperatures
• In a Separate Development We Have Demonstrated
that Ge JFETs Work Well at Cryogenic Temperatures
• All Types of Ge Devices Can Operate to Deep
Cryogenic Temperatures – to 20 K, as Low as 4 K
• Developed 10-A Ge Cryogenic Power Diodes with
High Reverse Breakdown and Low Forward Voltage
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Summary – cont’d
• Characterized Ge MIS Structures
at Room and Cryogenic Temperatures
• Made Ge Power MISFETs that Operate from Room
Temperature down to 4 K
• Made Ge Power JFETs that Operate from Room
Temperature down to 4 K
• Improved MISFETs and JFETs Are in Progress
• Ge BJT and IGBT Fabrication Is in Progress