Download - Future Prospects for Moore’s Law
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Future Prospects
for Moore’s Law
Future Prospects
for Moore’s Law
Eighth Annual High Performance
Embedded Computing Workshop
Lincoln Laboratory
September 28, 2004
Robert Doering
Texas Instruments, Inc.
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Generalizations of Moore’s LawGeneralizations of Moore’s Law Exponential
trends in:
More functions* per chip
Increased performance
Reduced energy per operation
Decreased cost per function (the principal driver)
* transistors, bits, etc.
'69 '74 '79 '84 '89 '94 '99 '04
Source: DataQuest, Intel
10-2
10 -4
10-6
1
Price per Transistor in MPU ($)
Dollars to Microcents:
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High-Level CMOS Technology Metrics– What are the Limits ?
High-Level CMOS Technology Metrics– What are the Limits ?
Component Diversity (integrated logic, memory, analog, RF, …)
Cost/Component (e.g., μ¢/gate or μ¢/bit in an IC)
Component Density (e.g., gates/cm2 or bits/cm2)
Logic Gate Delay (time for a gate to switch logic states)
Energy Efficiency (energy/switch and energy/time)
Mfg. Cycle Time (determines time-to-market for new designs as well as rate of yield learning)
All of these are limited by multiple factors inter-linked into a complex “tradeoff space.” We can only touch on a few of the issues today !
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State-of-the-Art CMOS in 2004State-of-the-Art CMOS in 2004 ITRS Technology Node: 90 nm (half-pitch of DRAM metal lines)
4T-Gates/cm2: 37x106 (150 million transistors/cm2)
6T-eSRAM bits/cm2: 108 (600 million transistors/cm2)
Cost/Gate (4T): 40 μ¢ (high volume; chip area = 1 cm2)
Cost/eSRAM bit: 10 μ¢ (high volume; chip area = 1 cm2)
Gate Delay 24 ps * (for 2-input, F.O. = 3 NAND)
Switching Energy 0.5 fJ * (for inverter, half-cycle)
Passive Power 6 nW * (per minimum-size transistor)
Min. Mfg. Cycle Time 10 days (or 3 mask levels/day)
* Values at extreme tradeoff for MPU application
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500
350
250
180
130
95 97 99 01 04 07 10 13 16
90
65
45
32
22
95 97 99 01 04 07 10 13 16
Scaling -- Traditional Enabler of Moore’s Law*Scaling -- Traditional Enabler of Moore’s Law*F
eat
ure
Siz
e [
nm
]
Year of Production
ITRS Gate Length
9
return to0.7x/3-yr ?
13
* For Speed, Low-Cost, Low-Power, etc.
ITRS Lithography Half-Pitch (DRAM)
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Can We Extendthe Recent 0.7x/2-year Litho Scaling Trend ?
Can We Extendthe Recent 0.7x/2-year Litho Scaling Trend ?
30002000
15001000
400 350250
180 130
9065
45
500600
101
102
103
104
1980 1990 2000 2010
Year of Production
Abovewavelength
Nearwavelength
Belowwavelength
g-line=436nm
i-line=365nm
DUV=248nm 193
=193nm157
=157nm
32
=EUV 13.5nm
Ha
lf-P
itch
/ W
av
ele
ng
th (
nm
)
i-193‘=133nm
For lithography, it’s a question of cost and control/parametric-yield !
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Com
plex
ity (m
ask,
use
)
Strength of enhancement
Illumination mode
Other (Tool)
Mask
Mask OPC
Resistk
1
0.25
0.5
A “Bag of Tricks” for Optical-ExtensionA “Bag of Tricks” for Optical-Extension
Conventional
Annular
Dipole
Soft Quasar
Custom
Scattering bars
Quasar
Binary Intensity Mask
Attenuated PSM 6%
Attenuated PSM 18%
Alternating PSM
Source: ASML
Serifs
Hammerheads
Line BiasingThick resist
Thin resist
Focus drilling
Phase filters
Double Exposures
Wavelength
NA
Of course : increasing complexity increasing cost !
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Amortization of Mask Cost @ 130nmAmortization of Mask Cost @ 130nm
1
10
100
1000
1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08
Chips Produced
Co
st p
er C
hip
[$]
~ 1 million units required to get within 10% of asymptotic cost !(and getting worse with continued scaling)
Significant motivationfor some form of “mask-less lithography” !
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Of course, overall scaling is limited
by more than just lithography !
Of course, overall scaling is limited
by more than just lithography ! Growing Significance of Non-Ideal Device-Scaling Effects:
ION vs. IOFF tradeoff
unfavorable and L scaling for interconnects
Approaching Limits of Materials Properties Heat removal and temperature tolerance
CMAX vs. leakage tradeoff for gate dielectric
CMIN vs. mechanical-integrity tradeoff for inter-metal dielectric
Increases in Manufacturing Complexity/Control Requirements cost and yield of increasingly complex process flows
metrology and control of LGATE, TOX, doping, etc.
Affordability of R&D Costs development of more complex and “near cliff” technologies
design of more complex circuits with “less ideal” elements
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MP
U C
loc
k (G
Hz)
ITRS Tries to Address Top-Down GoalsITRS Tries to Address Top-Down Goals
2001
2003
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Production Year: 2001 2004 2007 2010 2013 2016
Litho Half-Pitch [nm]: 130 90 65 45 32 22
Overlay Control [nm]: 45 32 23 18 13 9
Gate Length [nm]: 65 37 25 18 13 9
CD Control [nm]: 6.3 3.3* 2.2 1.6 1.2 0.8
TOX (equivalent) [nm]: 1.3-1.6 1.2 0.9 0.7 0.6 0.5
IGATE (LMIN) [µA/µm]: - 0.17 0.23 0.33 1 1.67
ION (NMOS) [µA/µm]: 900 1110 1510 1900 2050 2400
IOFF (NMOS) [µA/µm]: 0.01 0.05 0.07 0.1 0.3 0.5
Interconnect EFF- 3.1-3.6 2.7-3.0 2.3-2.6 2.0-2.4 <2.0
ITRS Highlights Scaling Barriers, e.g.:ITRS Highlights Scaling Barriers, e.g.:
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Surface scattering becomes dominant
p=0 (diffuse scattering)p=1 (specular scattering)
0
1
2
3
4
5
0 100 200 300 400 500
Metal Line Width (nm)
Res
isti
vity
(μΩ
cm) p=0
p=0.5
Another Interconnect-Scaling IssueAnother Interconnect-Scaling Issue
Wire width < mean-free-path of electrons
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2004 LG = 37-nm Transistor2004 LG = 37-nm Transistor
TOX(equiv.) = 1.2 nm
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Can Some Hi-K Dielectric Replace SiON ? Can Some Hi-K Dielectric Replace SiON ?
Source: Intel
Sub-nm SiON:• mobility• uniformity• leakage
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Selective-epi raised source/drainfor shallow junctions & reducedshort-channel effects
P-WELL
STI STISOURCE DRAIN
GATE
Si-Substrate
Halo I2
Etches for new materials that achieve profile, CD control, and selectivity
Metal gate electrode to reduce gate depletion
High- gate dielectric for reducing gate current with thin Tox
Strained channel forimproved mobility
Doping and annealing techniques for shallow abrupt junctions
Ni-silicide process for low resistanceat short gate lengths (near term)
In general, continued transistor scalingrequires new materials, processes, …
In general, continued transistor scalingrequires new materials, processes, …
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Fin
BOx
Tri-Gate FET3 Gates
Fin
BOx/ Ω Gate FET
3+ Gates
Fin
BOx
FinFET2 Gates
ThickDielectric
ActiveGate
… and, eventually new structures… and, eventually new structures
Buried Oxide
Silicon
Si Si
Gate
Buried Oxide
Silicon
Steps toward ideal “coax gate”
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Potential FET Enhancements ?Potential FET Enhancements ?
10
100
1000
500 1000 1500 2000 2500 3000Ion , µA/µm
Ioff
, nA
/µm
HP100
HP90
HP65
HP45
HP32
HP22 Bulk
+Strain
+UTB
SG
+Met.G
+UTB
DG
+Q. B
allis
tic+M
et. J
unc.
High PerformanceITRS 2003 Requirements
10
100
1000
500 1000 1500 2000 2500 3000Ion , µA/µm
Ioff
, nA
/µm
HP100
HP90
HP65
HP45
HP32
HP22 Bulk
+Strain
+UTB
SG
+Met.G
+UTB
DG
+Q. B
allis
tic+M
et. J
unc.
High PerformanceITRS 2003 RequirementsITRS 2003 Requirements
Calculations by T. Skotnicki
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At PQE 2004, Professor Mark Lundstrom
expressed the outlook:
“Sub-10nm MOSFETs will operate, but …
At PQE 2004, Professor Mark Lundstrom
expressed the outlook:
“Sub-10nm MOSFETs will operate, but …
- on-currents will be ~0.5xIballistic, off-currents high,
- 2D electrostatics will be hard to control,
- parasitic resistance will degrade performance,
- device to device variations will be large,
and
- ultra-thin bodies and hyper-abrupt junctions will be essential”
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Logic Device Technologies
Performance Architecture compatible
Stability and
reliability
CMOS compatible
Operate temp
Energy efficiency
Sensitivity parameter)
Scalability
1D Structures
2.3/2.2 2.2/2.9 1.9/1.2 2.3/2.4 2.9/2.9 2.6/2.1 2.6/2.1 2.3/1.6
RSFQ Devices
2.7/3.0 1.9/2.7 2.2/2.8 1.6/2.2 1.1/2.7 1.6/2.3 1.9/2.8 1.0/2.1
Resonant Tunneling Devices
2.6/2.0 2.1/2.2 2.0/1.4 2.3/2.2 2.2/2.4 2.4/2.1 1.4/1.4 2.0/2.0
Molecular Devices
1.7/1.3 1.8/1.4 1.6/1.4 2.0/1.6 2.3/2.4 2.6/1.3 2.0/1.4 2.6/1.3
Spin Transistor
2.2/1.7 1.7/1.6 1.7/1.7 1.9/1.4 1.6/2.0 2.3/2.1 1.4/1.7 2.0/1.4
SETs 1.1/1.2 1.7/1.2 1.3/1.1 2.1/1.4 1.2/1.8 2.6/2.0 1.0/1.0 2.1/1.7
QCA Devices 1.4/1.3 1.2/1.1 1.7/1.8 1.4/1.6 1.2/1.4 2.4/1.7 1.6/1.1 2.0/1.4
ITRS Assessment of Some Current Ideasfor Successors to CMOS Transistors
ITRS Assessment of Some Current Ideasfor Successors to CMOS Transistors
No obvious candidates yet for a CMOS replacement !
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SRC Research Gap Analysis (for <50nm)SRC Research Gap Analysis (for <50nm)
Worldwide Funding ~ $1,386 M
WW Research Gap ~ $1,155M
Industry Funding(Semiconductors + Suppliers)
U.S. $313 M
Japan $142 M
Europe $ 74 M
~ $580 M
Asia-Pac $ 51 M
U.S. $329 M
Europe $249 M
Japan $125 M Government Funding
~ $806 M
Asia-Pacific $103 M
Ongoing Tasks $2,169M
New Tasks $372M
Worldwide Needs ~ $2,541 M
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Extending Moore’s Law via Integrating New Functions onto CMOS
ITRS Emerging Technologies ?
“AnotherDimension”
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Why “Moore’s Law” Is Still a Fun Topic !Why “Moore’s Law” Is Still a Fun Topic !
What makes us think that we can forecast more than
~5 years of future IC technology any better today ?!!
A 1975 IC Technology Roadmap