Download - Fundamentals on ADCs-Part 1.2
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Texas A&M University 1 Spring, 2012
Fundamentals on ADCs: Part I Jose Silva-Martinez
Jose Silva-MartinezAmesp02.tamu.edu/~jsilva
Technological issues
January 2012
Fundamentals oF analoG to dIGItalConVeRteRs: PaRt I.2
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Fundamentals on ADCs: Part I Jose Silva-Martinez
Well-Diffusion Resistor
Example shows two long resistors for K range
Alternatively, serpentine shapes can be used Noise problems from the body
Substrate bias surrounding the well Substrate bias between the parallel strips
Dummies
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Fundamentals on ADCs: Part I Jose Silva-Martinez
Factors affecting accuracy :
Plastic packages cause a large pressure on the die (= 800 Atm.). It determines a variation of
the resistivity.
For material the variation is unisotropic, so the minimum is obtained if the resistancehave a 45o orientation.
Temperature :
Temperature gradient on thechip may produce thermalinduced mismatch.
uncompensated
compensated
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Fundamentals on ADCs: Part I Jose Silva-Martinez
Etching
Wet etching : isotropic (undercut effect)
HF for SiO2 ; H3PO4 for Al
x for polysilicon may be 0.75 - 1 m with
standard deviation 0.1 m.
Reactive ion etching (R.I.E.)(plasma etching
associated to bombardment) : unisotropic.
x for polysilicon is 0.4 m with standard deviation 0.03 m
Boundary :
The etching depends on the
boundary conditions
Use dummy strips
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Fundamentals on ADCs: Part I Jose Silva-Martinez
Side diffusion effect : Contribution of endings
Interdigitized structure :
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Fundamentals on ADCs: Part I Jose Silva-Martinez
First polysilicon resistance
First polysilicon resistance with a
well shielding
Second polysilicon resistance
Second polysilicon resistance with a
well shielding
Poly Resistors
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Fundamentals on ADCs: Part I Jose Silva-Martinez
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TYPES OF INTEGRATED CAPACITORS
Electrodes : metal; polysilicon; diffusion
Insulator : silicon oxide; polysilicon oxide; CVD oxide
222
ox
ox
2
r
r
2
W
W
L
L
t
t
C
C
+
+
+
=
WLt
C
ox
ox
=
TOP VIEW
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8/3/2019 Fundamentals on ADCs-Part 1.2
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Fundamentals on ADCs: Part I Jose Silva-Martinez
Factor affecting accuracy
ox
ox
ox
ox
t
t
W
W;
L
L
Oxide damage
Impurities
Bias condition
Bias history (for CVD)
Stress
Temperature
Etching
Alignment
Grow rate
Poly grain size
222
ox
ox
2
r
r
2
W
W
L
L
t
t
C
C
+
+
+
=
%1.01
C
C
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Poly1 - Poly2 Capacitor
Area is determined by poly2 Problems
undercut effects nonuniform dielectric thickness matching among capacitorsMinimize the rings (inductors)
Poly 2
Poly 1
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Accuracy of integrated capacitors
Perimeter effects led the totalcapacitance:
C = CA A
A = (x-2x)(y- 2y)
= (xy - 2xy - 2yx - 4x y)
Assuming that x = y = e
A = (xy - 2e(x + y) - 42e)
A xy - 2e(x + y)
Ce = - 2e(x + y)
The relative error is
= Ce/C= -2e(x + y) / xy
Then maximize the area and minimize
the perimeter use squares!!!
x
yx
y
CA = capacitance per unit are
Real
Area ofPoly 2
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Unit capacitors are connected in
parallel to form a larger
capacitance
Typically the ratio among
capacitors is what matters
The error in one capacitor isproportional to perimeter-area
ratio
Use dummies for better matching(See Johns & Martin Book, page112)
Common Centroid Capacitor Layout
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Common centroid structures
C1
TC1
C5
TC5
C2
TC2
C3
TC3
C4
TC4
C2 = C1C3 = 2C1C4 = 4C1C5 = 8C1
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Be aware of parasitic capacitors
Polysilicon-Polysilicon: Bottom platecapacitance is comparable (10-30 %)with the poly-poly capacitance
Metal1-Metal2: More clean, butthe capacitance per micrometersquare is smaller. Good option for
very high frequency applications (C~ 0.1-0.3 pF).
C1CP1 CP2
CP2
poly2
poly1
substrate
CP1, CP2 are very small (1-5 % ofC1)CP2 is around 10-50 % of C1
C1
CP1CP2
metal2
metal1
substrate
Thick oxide
C1
CP1CP2
Floating Capacitors
CP2 is very small (1-5 % of C1)
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Design example: Simplest OTA
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Overall amplifier: Have a look on the guard rings and additional deep well
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16BIAS: you may be able to see the dummies, symmetry and S/D connection
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From downstairs
Differential pair
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Details on the P-type current mirrors