Download - Functional Coverage and Clocking Blocks.pdf
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Functional Coverage
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46747**slide
Functional verification requires a large portion of the resources required to design and validate a complex system
To minimize the effort, coverage is used as a guide for directed verification and untested portions of the design
Coverage is defined as the percentage of verification objectives that have been met
Coverage Basics1-4
that have been met
It is used as a metric for evaluating the progress of a verificationproject in order to reduce the number of simulation cycles spentin verifying a design
Functional coverage is very important tool for environments, which run random tests Quality of design verification in aspect of random generation
Test plan closure
You can never say that the design is really checked if you do not have truefunctional coverage
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61182**slide
Verification plan includes all the features that needs to be verified Coverage helps verification engineer to check that sufficient varietyof input stimuli is applied to the DUT
Coverage is a collection of statistics based on sampling events within the simulation
What is Functional Coverage?1-5
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61121**slide
Key aspects of the functional coverage are as follows User-specified and not automatically inferred from the design
Based on design specification and independent of the actual design code
Key Aspects of Functional Coverage1-6
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Functional Coverage
Because it is fully specified by the user, functionalcoverage requires more up-front effort (someone has
to write the coverage model). Functional coverage
also requires a more structured approach to
verification.verification.
Although functional coverage can shorten the overallverification effort and yield higher quality designs, its
shortcomings can impede its adoption.
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46748**slide
covergroup construct encapsulates specification of a coverage model
Each covergroup specification can include the following components Clocking event that synchronizes the sampling of coverage points
Set of coverage points
covergroup
1-9
Set of coverage points
Cross coverage between coverage points
Optional formal arguments
Coverage options
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46750**slide
covergroup can contain one or more coverage points
Coverage point can be a variable or an expression Each coverage point includes a set of bins associated with its sampled
values or its value transitions
The bins can be explicitly defined by the user or automatically created by the tool
Coverage Points1-11
tool
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Sample()
User-defined sample() method is typically used to collect coverage from different variables to the same coverpoint/ covergroup
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Bins construct
The bins construct allows creating a separate bin for each value in the given range list or a single bin for the entire range of values.
To create a separate bin for each value (an To create a separate bin for each value (an array of bins), the square brackets, [], shall follow the bin name.
To create a fixed number of bins for a set of values, a number can be specified inside the square brackets.
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61282**slide
Coverage is a collection of statistics based on sampling events within the simulation
Coverage helps the verification engineer to check that sufficient variety of input stimuli is applied to the DUT
covergroup construct encapsulates specification of a coverage model
Features of Coverage1-43
model
covergroup instance can be created with the new() operator
covergroup can contain one or more coverage points
A coverage point can be a variable or an expression
Each coverpoint has a number of bins associated with it
If the coverage point does not define any bins, SystemVerilog automatically creates state bins
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Coverage Class//coverage class
class coverage;
virtual intf i;
covergroup cg @(i.a,i.b);
A: coverpoint i.a{bins a_bin = {[5:7]};}
B: coverpoint i.b;
S: coverpoint i.s{bins s1 = {0,1};bins s2 = {2,3};}
D: coverpoint i.c;
endgroup
function new (virtual intf i);
this.i = i ;
cg = new;
endfunction
task sample();
cg.sample();
endtask
endclass
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Coverage Class in Env Class
class enviroment;
mailbox #(packet) gen_drv;
mailbox #(packet) drv_sb;
mailbox #(packet) mon_sb;
virtual intf i;
coverage c1;
generator g1;
driver d1;driver d1;
monitor m1;
scoreboard s1;
function new(virtual intf i);
this.i=i;
endfunction
function build;
gen_drv=new();
drv_sb=new();
mon_sb=new();
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Coverage Class in Env Class
g1=new(gen_drv);
d1=new(gen_drv,drv_sb,i);
c1=new(i);
m1=new(mon_sb,i);
s1=new(drv_sb,mon_sb);
endfunction
task run;task run;
g1.run();
c1.sample();
d1.run();
#1 m1.run();
s1.run();
endtask
endclass
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Enhanced File I/0
`timescale 1ns / 1ps
module sp_ram8x16(
input clk,
input [2:0] addr,
input [15:0] d_in,
output [15:0] d_out,
input we
););
parameter ram_width = 16;
parameter ram_addr_bits = 3;
reg [ram_width-1:0] my_ram [(2**ram_addr_bits)-1:0];
always @(posedge clk)
if (we)
my_ram[addr]
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Enhanced File I/0`timescale 1ns / 1ps
module sp_ram8x16_tb;
// Inputs
reg clk;
reg [2:0] addr;
reg [15:0] d_in;reg [15:0] d_in;
reg we;
// Outputs
wire [15:0] d_out;
// Instantiate the Unit Under Test (UUT)
sp_ram8x16 uut (.*);
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Enhanced File I/0initial begin
// Initialize Inputs
clk = 0;
addr = 0;
d_in = 0;
we = 1;
end
always #20 clk = ~clk ;always #20 clk = ~clk ;
`define eof 32'hffff_ffff
/////////////////STEP 1 Declare variables for FILE, RET & CHAR,
///also declare external input file MY_INPUT.txt
integer file, ret, char ;
initial file = $fopen ("my_input.txt", "r" );
////////////////End of STEP 1
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Enhanced File I/0
////////////////STEP 2 write procedural block that extracts data from MY_INPUT.txt, test for EOF
initial begin
char = $fgetc(file);
while (char != `eof)
begin
ret = $ungetc(char, file );ret = $ungetc(char, file );
ret = $fscanf(file, "%h", d_in );
#100 addr = addr + 1 ;
char = $fgetc(file);
end
end
/////////////////End of Step 2
endmodule
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Mailboxes in System Verilog
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Mailboxes A mailbox is a communication mechanism that
allows messages to be exchanged betweenprocesses. Data can be sent to a mailbox byone process and retrieved by another.
Conceptually, mailboxes behave like realmailboxes. When a letter is delivered and putinto the mailbox, one can retrieve the letterinto the mailbox, one can retrieve the letter(and any data stored within).
However, if the letter has not been deliveredwhen one checks the mailbox, one mustchoose whether to wait for the letter orretrieve the letter on subsequent trips to themailbox.
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Mailboxes
Similarly, SystemVerilog's mailboxes provideprocesses to transfer and retrieve data in acontrolled manner.
Mailboxes are created as having either abounded or unbounded queue size.
A bounded mailbox becomes full when it A bounded mailbox becomes full when itcontains the bounded number of messages.
A process that attempts to place a messageinto a full mailbox shall be suspended untilenough room becomes available in the mailboxqueue.
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Methods in Mailboxes
Mailbox is a built-in class that provides the following methods:
Create a mailbox: new() Place a message in a mailbox: put()
Retrieve a message from a mailbox: get() Retrieve a message from a mailbox: get()
Retrieve the number of messages in the
mailbox: num()
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Mailbox Examples
module mailbox_ex;
//PKT CLASS
class pkt;class pkt;
rand bit a;
rand bit b;
endclass
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Generator Class//generator class
class generator;
bit success;
mailbox #(pkt) mb_gen = new();
pkt inst ;
task run();
repeat(5)
begin
inst=new();inst=new();
success = inst.randomize();
mb_gen.put(inst);
$display($time, "Putting packet: a = %d && b = %d", inst.a, inst.b);
#10;
end
endtask
endclass
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Driver Class
// driver class
class driver;
mailbox #(pkt) mb_drv = new();
pkt inst;
task run();
#100;#100;
inst=new();
mb_drv.get(inst);
$display($time,"getting packet from mailbox: a = %d && b = %d",inst.a,inst.b);
endtask
endclass
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Module Execution
generator gen = new();
driver drv = new();
//Module execution starts
initial
begin
forkfork
gen.run();
#50 drv.run();
join
$finish();
end
endmodule
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Mailbox Example 2
module mailbox_ex2();
//PKT CLASS
class random_pkt;
rand bit [2:0] a;rand bit [2:0] a;
rand bit [4:0] b;
endclass
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Generator Classclass generator;
random_pkt inst=new() ;
bit success;
mailbox #(random_pkt) mb_gen = new();
task run();
repeat(5)
begin
inst = new();inst = new();
success = inst.randomize();
mb_gen.put(inst);
$display ($time,"Putting packet: a = %d && b = %d", inst.a, inst.b);
#5;
end
endtask
endclass
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Driver Class
class driver;
random_pkt inst=new();
mailbox #(random_pkt)mb_drv ;
task run();
#25;
$display("mailbox size in driver is =%d",mb_drv.num());
repeat(5)
beginbegin
#5;
mb_drv.get(inst);
$display($time,"getting packet from mailbox: a = %d && b = %d",inst.a,inst.b);
#5;
end
endtask
endclass
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Module Execution
generator gen = new();
driver drv = new();
//Module execution starts
initial
begin
drv.mb_drv = gen.mb_gen;
forkfork
gen.run();
drv.run();
join
$finish();
end
endmodule
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System Verilog Scheduler
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Program Block
The program block serves three basic purposes:
1) It provides an entry point to the execution of testbenches.
2) It creates a scope that encapsulates program-wide data.
3) It provides a syntactic context that specifies scheduling in the
Reactive region.
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Reactive region.
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Program Block
The program construct serves as a clear separator betweendesign and testbench, and, more importantly, it specifies
specialized execution semantics in the Reactive region for all
elements declared within the program.
Together with clocking blocks, the program construct provides
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Together with clocking blocks, the program construct providesfor race-free interaction between the design and the
testbench, and enables cycle and transaction level
abstractions.
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46385**slide
Program block drives the DUT inputs
Program block executes in Reactive region
Programs are instantiated or nested within a testbench Encapsulating all design verification functionality
Testbench can include one or more programs
Each program can call the $exit() method
Program Blocks1-23
Each program can call the $exit() method
When the $exit() method is called, all the threads opened within the program are terminated
When all the programs are done (either by calling the $exit() method or by finishing all the threads), the $finish() system task is called automatically
Programs cannot instantiate modules, but they may have input, output, and inout ports and interfaces like modules
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60941**slide
Program block construct is provided for modeling the testbenchenvironment
The program construct serves as a clear separator between design and testbench
A program block can contain
Data declarations, class definitions, subroutines, and one or more initial and
Program Syntax1-24
Data declarations, class definitions, subroutines, and one or more initial and final procedures
A program block cannot contain always procedures, primitive instances, module instances, interface
instances, or other program instances
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Program Block
The program block serves the following purposes:
Provides an entry point to the execution of testbenches.
Creates a scope that encapsulates program-wide data, tasks, and functions.
Provides a syntactic context that specifies scheduling in the reactive region.
Together with clocking blocks, the program construct provides for race-free interaction between the design and the testbench and enables cycle and transaction-level abstractions.
The abstraction and modeling constructs of SystemVerilog simplify the creation and maintenance of testbenches.
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77291**slide
module ports and interfaces specify the input/output signals
Testbench communicates with these signals
These signals need to be taken care of Timing information
Synchronization requirements
Input sampling
Clocking Block1-29
Input sampling
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46388**slide
Clocking block will allow you to Sample the inputs and drive the outputs to synchronize with a specific clock
Provides immediate ability to specify input and output skew (timing spec) Input skew specifies how long before a "real" clock-edge signal is sampled
Output skew specifies how long after a "real" clock-edge signal is driven
Clocking Block1-30
Output skew specifies how long after a "real" clock-edge signal is driven
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Clocking block between DUT and TB
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Default clocking blocks
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Default clocking blocks
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Clocking Blocks
A clocking block assembles signals that aresynchronous to a particular clock and makes theirtiming explicit.
The clocking block is a key element in a cycle-basedmethodology, which enables users to writetestbenches at a higher level of abstraction.testbenches at a higher level of abstraction.
Rather than focusing on signals and transitions in time,the test can be defined in terms of cycles andtransactions.
Depending on the environment, a testbench cancontain one or more clocking blocks, each containingits own clock plus an arbitrary number of signals.
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46391**slide
Default clocking block One clocking block can be specified as the default for all cycle operations
A default is valid only within the scope of the default clocking specification
Only one default clocking can be specified in a module, interface, program,
or checker
Cycle operator ##
Default Clocking and ## Cycle Delay1-33
Cycle operator ## The ## operator can be used to delay execution by a specified by the
number of clock cycles or clocking events
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Example
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Example for Clocking Blockmodule top;
bit rst, clk;
intf i1(rst, clk);
env e1(i1);
design d1(i1);
initial begin
clk = 0;clk = 0;
forever begin
#5 clk = 1;
#5 clk = 0;
end
end
endmodule
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Interface Declarationinterface intf(input rst, clk);
logic [1:2] select; // operation
logic [1:4] dtoe; // dut to env data
logic [1:4] etod; // env to dut data
wire [1:4] bus; // bidirectional data
modport env (inout bus, modport env (inout bus,
output etod, select,
input dtoe, rst, clk);
modport design (inout bus,
output dtoe,
input etod, select, rst, clk);
endinterface
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Clocking block
program env (intf.env if1);
clocking cb @(posedge if1.clk);
output select = if1.select;
input dtoe = if1.dtoe;
output etod = if1.etod;
inout bus = if1.bus;inout bus = if1.bus;
endclocking
task doit(input logic [1:2] sel, input logic [1:4] toe, bd);
cb.select
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Clocking block
initial begin
cb.etod
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Design modulemodule design (intf.design if1);
wire clk = if1.clk;
wire [1:2] select = if1.select;
reg [1:4] dtoe, busdrv;
assign if1.dtoe = dtoe;
assign if1.bus = busdrv;
always @(posedge clk) begin
dtoe
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Example on Clocking Blocksclocking cb1@(posedge mp_clk);
default output #100;
default input #0;
input stat_xmit_emptyH, stat_rec_dataH, uart_clk, mp_data_from_uart, mp_int_l;
output mp_data_to_uart, mp_addx, sys_rst_l, mp_cs_l, mp_rd_l, mp_wr_l;
endclocking
clocking cb2@(posedge baud_clk)
default input #0;
output uart_REC_dataH;output uart_REC_dataH;
endclocking
clocking cb3@(posedge mp_clk)
input mp_data_from_uart, mp_int_l;
endclocking
modport driver(clocking cb1, clocking cb2);
modport monitor(clocking cb3, input uart_XMIT_dataH, input uart_clk);
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Debug the error if any from the solution for the given
problem
Use the interface & interface tasks to perform write and read operation an RAM
module. The interface has a 8 bit
data/address bus along with (read/write
enable). The read and write are enable). The read and write are
synchronized with posedge of clock
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Interface and Interface Tasks
interface intf;
bit re,we;
bit clk;
bit [7:0] data_in,data_out;
bit [7:0] addr;bit [7:0] addr;
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Interface and Interface Tasksclocking cb_driv @(posedge clk);
output clk,we,re;
output data_in;
output addr;
endclockingendclocking
clocking cb_mon @(posedge clk);
input data_out;
endclocking
modport driv(clocking cb_driv);
modport mon(clocking cb_mon)
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Interface and Interface Taskstask write(input addr, data_in);
cb_driv.addr=addr;
cb_driv.data_in=data_in;
endtask
task read(input addr, output data_out);
cb_driv.addr=addr;
data_out= cb_mon.data_out;
endtask
endinterface
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60979**slide
SystemVerilog verification building blocks are the program block, interfaces, clocking block, and packagesSystemVerilog introduces the program block to separate the testbench and to avoid the race conditions between the design and testbench
The interface construct encapsulates the interconnection and
System Verilog Verification building blocks1-49
The interface construct encapsulates the interconnection and communication between blocks
To restrict the interface access within a module, modport lists the directions declared within the interface
Clocking block is a synchronization part within a module'sinterconnection (interface) or signal drivers (programs andmodules)
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fork-join1-40
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fork-join any1-41
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fork-join_none1-42
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1. What is the purpose of using a program block?
2. What is the SystemVerilog interface construct?
3. What is the clocking block?
FAQ1-48