Application ReportSWCA090–December 2010
Feature Differences Between TPS65950 and TPS65951.....................................................................................................................................................
ABSTRACT
This document shows the differences in features, the ball comparison and, the delta registers between theTPS65950 and TPS65951 devices.
Contents1 Feature Differences Between TPS65950 and TPS65951 ............................................................. 22 Ball Characteristic Comparison ........................................................................................... 33 Register Differences ........................................................................................................ 94 TPS65951 Registers – Accessory and BCI ............................................................................ 16
List of Tables
1 Feature Differences for TPS65950 and TPS65951 .................................................................... 2
2 Ball Characteristic Comparison ........................................................................................... 3
3 Audio Registers ............................................................................................................. 9
4 USB Registers ............................................................................................................. 10
5 Power Registers ........................................................................................................... 12
6 Auxillary Registers......................................................................................................... 14
7 Instance Summary ........................................................................................................ 16
8 ACCESSORY VINTDIG Register Summary ........................................................................... 16
9 AUDIO_CTRL .............................................................................................................. 17
10 BCIA_CTRL ................................................................................................................ 17
11 SPARE1 .................................................................................................................... 18
12 SPARE2 .................................................................................................................... 18
13 FACTDATA0 ............................................................................................................... 18
14 FACTDATA1 ............................................................................................................... 18
15 FACTDATA2 ............................................................................................................... 19
16 FACTDATA3 ............................................................................................................... 19
17 FACTDATA4 ............................................................................................................... 19
18 FACTDATA5 ............................................................................................................... 19
19 FACTDATA6 ............................................................................................................... 20
20 FACTDATA7 ............................................................................................................... 20
21 FACTDATA8 ............................................................................................................... 20
22 FACTDATA9 ............................................................................................................... 20
23 FACTDATA10.............................................................................................................. 21
24 ACC_VPRECH Register Summary ..................................................................................... 22
25 BCC_CTRL................................................................................................................. 23
26 BCC_CTRL2 ............................................................................................................... 23
27 BCC_STS................................................................................................................... 24
28 USB_CHRG_CTRL1 ...................................................................................................... 25
29 USB_CHRG_CTRL2 ...................................................................................................... 26
30 LED_DRIVER_CTRL ..................................................................................................... 26
1SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
Feature Differences Between TPS65950 and TPS65951 www.ti.com
31 FACTCFG0_VPRCH...................................................................................................... 27
32 FACTCFG1_VPRCH...................................................................................................... 28
33 SPARE1_VPRECH........................................................................................................ 28
34 SPARE2_VPRECH........................................................................................................ 28
35 BCIISR1 .................................................................................................................... 29
36 BCIIMR1 .................................................................................................................... 30
37 BCISIR ...................................................................................................................... 30
38 BCIEDR1 ................................................................................................................... 31
39 BCISIHCTRL ............................................................................................................... 32
1 Feature Differences Between TPS65950 and TPS65951
Table 1. Feature Differences for TPS65950 and TPS65951
Module TPS65950 TPS65951 Implication
Power Remove VSIM LDO LDO not available
Cannot control an externalPower RFID.EN ball not present regulator/peripheral
Removed 2nd processor control No multiprocessor support forPower signals - CLKEN2, INT2 and wakeup/sleep, etc.NSLLEP2
Add battery removal detection signalPower Battery removal detection not available Additional feature/flexibility(MANU_BRIX ball)
VMBCH comparator threshold is set to VMBCH comparator threshold is setPower 3.2 V. to 3.1 V.
Device can be restarted by pressing Device can be switched off byPWRON push button for 8 seconds, but pressing PWRON push button for 8this is not default setting at power up, PWRON button functionality will bePower seconds (this is default setting atsoftware needs to program the impacted due to the new feature.power up). STOPON_PWRON is setSTOPON_PWRON bit after the first to 1 at power up and is read-only.power up.
The following detections are enabled at The following wake-up functions are Cannot disable the mentionedPower power up and can be disabled if enabled by default and cannot be wake-up events.required: disabled:
VBUS and VBAT detection, RTC VBUS and VBAT detection, RTCrequest, USB and AC charger insertion, request, USB charger insertion,PWRON button press. PWRON button press.
OTG 1.3 and 2.0 compliancyUSB Compliant with OTG version 1.3 selectable by register access (bit 0 of
OTHER_FUNC_CTRL).
Increased VBUS input voltageVBUS voltage tolerance range is 0 to 7USB tolerance range to –2 V to 20 V inV USB device mode
Improved USB reset logic asUSB N/A described below:
A power down of the USB PHY isperformed by setting thePHY_PWR_CTRL[0] PHYPWD bit to1. It resets the PHY, ULPIstate-machine, and USB interrupts. Itdoes not reset the USB registers.
ULPI bus impedance changed to 50 PCB layout will be impacted asUSB ULPI bus impedance is 90 Ω. Ω. compared to TPS65950.
Added dedicated output for USBCharge pump output was available onUSB charge pump. New ballVBUS pin. VUSBIN.CPOUT
2 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com Ball Characteristic Comparison
Table 1. Feature Differences for TPS65950 and TPS65951 (continued)
Module TPS65950 TPS65951 Implication
Replaced battery charger module withComplete battery charger module state-machine that controls anBCI available for AC and USB charging. external charger. Only USB charger is
supported.
FSM and software charger detectionBCI USB charger detection is present. New USB charger detection module available for detecting USB100 and
USB500 charger type.
Compliant with battery charging Compliant with battery chargingBCI specification ver 1.0 specification ver 1.1
Battery node discharge feature inBCI N/A case of battery removal.
Charger status can be seen fromBCI No charger LED included New charger LED indicator available LED
Digital mic decimator performanceimproved. 0 db PDM inputs involve 0Audio N/A dBFs data output (with default gainsetting: 0dB)
Audio Headset UART functionality available Headset UART functionality removed. Cannot use UART+audio mode
1. Only one stereo digital uplink pathavailableOne digital mic and PCM BT interfaceAudio is removed 2. No Bluetooth® PCM interfaceavailable
Must be master on audio interfaceCan be master or slave when usingAudio because CLK256FS ball removed andaudio interface no FS available for external device
Removed external channels ADCIN4,ADCIN5, and ADCIN6.MADC Removed internal channels ADCIN10,ADCIN11 and ADCIN15.
Acquisition time is programmable within Increased acquisition time from 5 toMADC 5 to 20 µs, default is 12 µs 171 6 µs. Default is 12 µs.
AUX Keypad available Removed keypad No keypad functions
Vibra driver improvement, Ron isAudio Vibra driver: Ron (maximum) = 8 Ω reduced. Ron (maximum) = 5 ΩUSB Carkit feature removed No carkit features
USB VUSB.3P1 output voltage adjustable
2 Ball Characteristic Comparison
Table 2 shows the ball comparison for TPS65950 and TPS65951.
Table 2. Ball Characteristic Comparison
TPS65950 TPS65951
Number of Number ofNetName Ball Name NetName Ball NameBalls Balls
32KCLKOUT N10 1 32KCLKOUT J6 1
32KXIN P16 1 32KXIN L12 1
32KXOUT P15 1 32KXOUT L13 1
ADCIN0 H4 1 ADCIN0 K1 1
ADCIN1 J3 1 ADCIN1 G3 1
ADCIN2 G3 1 ADCIN2 F4 1
AGND N15 1 AGND G7 1
AUXL F1 1 AUXL E1 1
AUXR G1 1 AUXR F3 1
3SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
Ball Characteristic Comparison www.ti.com
Table 2. Ball Characteristic Comparison (continued)
TPS65950 TPS65951
Number of Number ofNetName Ball Name NetName Ball NameBalls Balls
AVSS1 J4 / J6 / J7 / J8 / E5 5 AVSS1 G4 1
AVSS2 R10 1 AVSS2 K7 1
AVSS3 M15 1 AVSS3 K11 1
AVSS4 C7 1 AVSS4 A6 1
BCIAUTO N1 1
BKBAT M14 1 BKBAT J12 1
BOOT0 K11 1 BOOT0 J13 1
BOOT1 J11 1 BOOT1 G10 1
BT.PCM.VDR/ BT.PCM.VDR/C3 1 C3 1GPIO16/DIG.MIC.CLK0 GPIO16/DIG.MIC.CLK0
BT.PCM.VDX/ C5 1GPIO17/DIG.MIC.CLK1
CHRG_DET_N K6 1
CLK256FS D13 1
CLKEN C6 1 CLKEN F6 1
CLKEN2 D7 1
CLKREQ G10 1 CLKREQ B13 1
CP.CAPM T6 1 CP.CAPM N5 1
CP.CAPP T7 1 CP.CAPP N6 1
CP.GND R6 1 CP.GND K5 1
CP.IN R7 1 CP.IN M5 1
CTSI/BERDATA.OUT/ P11 1 ADCIN3 K8 1ADCIN3
DATA0/UART4.TXD K14 1 DATA0/UART4.TXD H11 1
DATA1/UART4.RXD K13 1 DATA1/UART4.RXD H10 1
DATA2/UART4.RTSI J14 1 DATA2 G8 1
DATA3/UART4.CTSO/ J13 1 DATA3/GPIO.12 H9 1GPIO.12
DATA4/GPIO.14 G14 1 DATA4/GPIO.14 F9 1
DATA5/GPIO.3 G13 1 DATA5/GPIO.3 F8 1
DATA6/GPIO.4 F14 1 DATA6/GPIO.4 E10 1
DATA7/GPIO.5 F13 1 DATA7/GPIO.5 E11 1
H13 / H9 / H10 /DGND 4 DGND G11 1H11
DIR/GPIO.10 L13 1 DIR/GPIO.10 J10 1
DN/UART3.TXD T11 1 DN/UART3.TXD J8 1
DP/UART3.RXD T10 1 DP/UART3.RXD J7 1
EAR.M A7 1 EAR.M D6 1
EAR.P A6 1 EAR.P C6 1
GND.LEFT C10 1 GND.LEFT C8 1
GND.LEFT C9 1
GND.RIGHT C11 1 GND.RIGHT C9 1
GND.RIGHT C12 1
GPIO.0/CD1/ GPIO.0/CD1/P12 1 M8 1JTAG.TD0 JTAG.TD0
GPIO.1/CD2/ GPIO.1/CD2/N12 1 L9 1JTAG.TMS JTAG.TMS
4 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com Ball Characteristic Comparison
Table 2. Ball Characteristic Comparison (continued)
TPS65950 TPS65951
Number of Number ofNetName Ball Name NetName Ball NameBalls Balls
GPIO.15/TEST2 P13 1 GPIO.15/TEST2 L10 1
GPIO.2/TEST1 L4 1 GPIO.2/TEST1 J3 1
GPIO.6/CLKOK/ GPIO.6/CLKOK/M4 1 K3 1PWM0/TEST3 PWM0/TEST3
GPIO.7/ GPIO.7/VIBRA.SYNC.PWM1/ N14 1 VIBRA.SYNC.PWM1/ M13 1TEST4 TEST4
HFCLKIN A14 1 HFCLKIN B11 1
HFCLKOUT R12 1 HFCLKOUT N8 1
HSMIC.M F3 1 HSMIC.M E3 1
HSMIC.P E3 1 HSMIC.P E4 1
HSOL B4 1 HSOL C5 1
HSOR B5 1 HSOR A5 1
I2C.CNTL.SCL D5 1 I2C.CNTL.SCL D5 1
I2C.CNTL.SDA D4 1 I2C.CNTL.SDA E5 1
I2S.CLK L3 1 I2S.CLK J4 1
I2S.DIN K4 1 I2S.DIN H3 1
I2S.DOUT K3 1 I2S.DOUT H4 1
I2S.SYNC K6 1 I2S.SYNC K2 1
ICTLAC1 N7 1
ICTLAC2 P2 1
ICTLUSB1 P6 1
ICTLUSB2 P1 1
ID R11 1 ID L8 1
IHF.LEFT.M B10 1 IHF.LEFT.M A8 1
IHF.LEFT.P B9 1 IHF.LEFT.P B8 1
IHF.RIGHT.M B12 1 IHF.RIGHT.M A9 1
IHF.RIGHT.P B11 1 IHF.RIGHT.P B9 1
INT1 F10 1 INT1 B10 1
INT2 F9 1
IO.1P8 C8 1 IO.1P8 E7 1
JTAG.TCK/ JTAG.TCK/B16 1 D11 1BERCLK BERCLK
JTAG.TDI/ JTAG.TDI/A15 1 B12 1BERDATA BERDATA
KPD.C0 G8 1
KPD.C1 H7 1
KPD.C2 G6 1
KPD.C3 F7 1
KPD.C4 G7 1
KPD.C5 F4 1
KPD.C6 H6 1
KPD.C7 G4 1
KPD.R0 K9 1
KPD.R1 K8 1
KPD.R2 L8 1
KPD.R3 K7 1
5SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
Ball Characteristic Comparison www.ti.com
Table 2. Ball Characteristic Comparison (continued)
TPS65950 TPS65951
Number of Number ofNetName Ball Name NetName Ball NameBalls Balls
KPD.R4 L9 1
KPD.R5 J10 1
KPD.R6 K10 1
KPD.R7 L7 1
LEDA/VIBRA.P F15 1 LEDA/VIBRA.P E9 1
LEDB/VIBRA.M G15 1 LEDB/VIBRA.M F11 1
LEDGND F16 1 LEDGND F10 1
LEDSYNC/GPIO.13 G11 1 LEDSYNC/GPIO.13 A12 1
MANU L10 1
MANU_BRIX K9 1
MIC.MAIN.M F2 1 MIC.MAIN.M E2 1
MIC.MAIN.P E2 1 MIC.MAIN.P D2 1
MIC.SUB.M/DIG.MIC.1 H2 1 MIC.SUB.M/DIG.MIC.1 G5 1
MIC.SUB.P/DIG.MIC.0 G2 1 MIC.SUB.P/DIG.MIC.0 F5 1
MICBIAS.GND D3 1 MICBIAS.GND D1 1
MICBIAS1.OUT/VMIC1.OUT D1 1 MICBIAS1.OUT/VMIC1.OUT B1 1
MICBIAS2.OUT/VMIC2.OUT D2 1 MICBIAS2.OUT/VMIC2.OUT C1 1
MSECURE H8 1 MSECURE B7 1
NRESPWRON A13 1 NRESPWRON C10 1
NRESWARM B13 1 NRESWARM A11 1
NSLEEP1 P7 1 NSLEEP1 C11 1
NSLEEP2 G9 1
NXT/GPIO.11 M13 1 NXT/GPIO.11 J11 1
PCHGAC N4 1
PCHGUSB N6 1
PCM.VCK R1 1 PCM.VCK M1 1
PCM.VDR T2 1 PCM.VDR L4 1
PCM.VDX T15 1 PCM.VDX H8 1
PCM.VFS R16 1 PCM.VFS N12 1
PreDriv.LEFT/VMID B7 1 PreDriv.LEFT/VMID E6 1
PreDriv.RIGHT/ADCIN7 B8 1 PreDriv.RIGHT/ADCIN7 D7 1
PWROK1 B14 1
PWROK2/I2C.SR.SDA C4 1 PWROK2/I2C.SR.SDA C4 1
PWRON A11 1 PWRON F7 1
REGEN A10 1 REGEN D8 1
RFID.EN A2 1
RTSO/CLK64K.OUT/ N11 1BERCLK.OUT/ADCIN5
RXAF/ADCIN6 N9 1
START.ADC J9 1 START.ADC L11 1
STP/GPIO.9 L14 1 STP/GPIO.9 K10 1
SYSEN C13 1 SYSEN E8 1
TEST A1 1 TEST A1 1
TEST.RESET T16 1 TEST.RESET N13 1
TESTV1 T1 1 TESTV1 N1 1
TESTV2 A16 1 TESTV2 A13 1
6 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com Ball Characteristic Comparison
Table 2. Ball Characteristic Comparison (continued)
TPS65950 TPS65951
Number of Number ofNetName Ball Name NetName Ball NameBalls Balls
TXAF/ADCIN4 N8 1
UART1.RXD/GPIO.8 D8 1
UART1.TXD B1 1
UCLK L15 1 UCLK J9 1
VAC N5 1
USBCHRG_ENZ J5 1
USBCHRG_STATZ H5 1
VAUX1.OUT M2 1 VAUX1.OUT J2 1
VAUX12S.IN L1 1 VAUX12S.IN H1 1
VAUX2.OUT M3 1 VAUX2.OUT J1 1
VAUX3.OUT G16 1 VAUX3.OUT F12 1
VAUX4.IN B2 1 VAUX4.IN A2 1
VAUX4.OUT B3 1 VAUX4.OUT B3 1
VBAT R5 1 VBAT L5 1
VBAT.LEFT D10 1 VBAT.LEFT A7 1
VBAT.LEFT D9 1
VBAT.RIGHT D11 1 VBAT.RIGHT A10 1
VBAT.RIGHT D12 1
VBAT.USB R9 1 VBAT.USB N7 1
VBATVIBRA D9 1
VBATS P4 1
VBUS R8 1 VBUS H7 1
VCCS P5 1
VDAC.IN K1 1 VDAC.IN G1 1
VDAC.OUT L2 1 VDAC.OUT H2 1
VDD1.GND B15 1 VDD1.GND C12 1
VDD1.GND C15 1 VDD1.GND C13 1
VDD1.GND C16 1
VDD1.IN D14 1 VDD1.IN E12 1
VDD1.IN E14 1 VDD1.IN E13 1
VDD1.IN E15 1
VDD1.L C14 1
VDD1.L D15 1 VDD1.SW (1) D12 1
VDD1.L D16 1 VDD1.SW (1) D13 1
VDD1.OUT E13 1 VDD1.FB (1) D10 1
VDD2.GND R15 1 VDD2.GND M11 1
VDD2.GND T14 1 VDD2.GND N11 1
VDD2.IN P14 1 VDD2.IN M9 1
VDD2.IN R13 1 VDD2.IN N9 1
VDD2.L R14 1 VDD2.SW (1) M10 1
VDD2.L T13 1 VDD2.SW (1) N10 1
VDD2.OUT N13 1 VDD2.FB (1) M12 1
VHSMIC.OUT E4 1 VHSMIC.OUT D3 1
VINT.IN K15 1 VINT.IN H13 1
VINTANA1.OUT H3 1 VINTANA1.OUT F2 1
(1) Different name but same function
7SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
Ball Characteristic Comparison www.ti.com
Table 2. Ball Characteristic Comparison (continued)
TPS65950 TPS65951
Number of Number ofNetName Ball Name NetName Ball NameBalls Balls
VINTANA2.OUT B6 1 VINTANA2.OUT B6 1
VINTANA2.OUT J2 1 VINTANA2.OUT F1 1
VINTDIG.OUT L16 1 VINTDIG.OUT H12 1
VINTUSB1P5.OUT P8 1 VINTUSB1P5.OUT M6 1
VINTUSB1P8.OUT P10 1 VINTUSB1P8.OUT M7 1
VIO.GND R2 1 VIO.GND L3 1
VIO.GND T3 1 VIO.GND M2 1
VIO.GND N2 1
VIO.IN P3 1 VIO.IN M4 1
VIO.IN R4 1 VIO.IN N4 1
VIO.L R3 1 VIO.SW (2) M3 1
VIO.L T4 1 VIO.SW (2) N3 1
VIO.OUT N3 1 VIO.FB (2) L2 1
VMMC1.IN C1 1 VMMC1.IN C2 1
VMMC1.OUT C2 1 VMMC1.OUT B2 1
VMMC2.IN A3 1 VMMC2.IN A4 1
VMMC2.OUT A4 1 VMMC2.OUT B4 1
VMODE1 F8 1
VMODE2/I2C.SR.SCL D6 1 VMODE2/I2C.SR.SCL B5 1
VPLLA3R.IN H15 1 VPLLA3R.IN F13 1
VPPL1.OUT H14 1 VPPL1.OUT G9 1
VPRECH N2 1 VPRECH L1 1
VPROG K4 1
VREF N16 1 VREF K13 1
VREFGND K12 1
VRTC.OUT K16 1 VRTC.OUT G12 1
VSDI.CSI.OUT J15 1 VSDI.CSI.OUT G13 1
VSIM.OUT K2 1
VSL.OUT G2 1
VUSB.3P1 P9 1 VUSB.3P1 L7 1
VUSBIN.CPOUT L6 1
Total number of balls 209 164(2) Different name but same function
8 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com Register Differences
3 Register Differences
Table 3. Audio Registers
Address Register Name TPS65950 TPS65951 Comment
0x82 PIH_ISR_P2 Register is used Register is spare INT2 is removed.
0x87 INTBR_IDCODE_23_16 Value 0x09 Value 0x77 Device IDCODE is different.
0x88 INTBR_IDCODE_31_24 Value 0x10 Value 0x2b Device IDCODE is different.
0x99 GPIODATAIN2 Bit [0] is used Bit [0] is spare GPIO8 is removed.
0x9A GPIODATAIN3 Bit [1] is used Bit [1] is spare GPIO17 is removed.
0x9C GPIODATADIR2 Bit [0] is used Bit [0] is spare GPIO8 is removed.
0x9D GPIODATADIR3 Bit [1] is used Bit [1] is spare GPIO17 is removed.
0x9F GPIODATAOUT2 Bit [0] is used Bit [0] is spare GPIO8 is removed.
0xA0 GPIODATAOUT3 Bit [1] is used Bit [1] is spare GPIO17 is removed.
GPIO_CLEARGPIODATA0xA2 Bit [0] is used Bit [0] is spare GPIO8 is removed.OUT2
GPIO_CLEARGPIODATA0xA3 Bit [1] is used Bit [1] is spare GPIO17 is removed.OUT3
GPIO_SETGPIODATAOU0xA5 Bit [0] is used Bit [0] is spare GPIO8 is removed.T2
GPIO_SETGPIODATAOU0xA6 Bit [1] is used Bit [1] is spare GPIO17 is removed.T3
0xA8 GPIO_DEBEN2 Bit [0] is used Bit [0] is spare GPIO8 is removed.
0xA9 GPIO_DEBEN3 Bit [1] is used Bit [1] is spare GPIO17 is removed.
0xAD GPIOPUPDCTR3 Bits [1:0] used Bits [1:0] spare GPIO8 is removed.
0xAF GPIOPUPDCTR5 Bits [3:2] used Bits [3:2] spare GPIO17 is removed.
0xB2 GPIO_ISR2A Bit [0] is used Bit 0 is spare GPIO8 is removed.
0xB3 GPIO_ISR3A Bit [1] is used Bit 1 is spare GPIO17 is removed.
0xB5 GPIO_IMR2A Bit [0] is used Bit 0 is spare GPIO8 is removed.
0xB6 GPIO_IMR3A Bit [1] is used Bit 1 is spare GPIO17 is removed.
Because INT2 is removed, this0xB7 GPIO_ISR1B Register is used Register is spare register is not used.
Because INT2 is removed, this0xB8 GPIO_ISR2B Register is used Register is spare register is not used.
Because INT2 is removed, this0xB9 GPIO_ISR3B Register is used Register is spare register is not used.
Because INT2 is removed, this0xBA GPIO_IMR1B Register is used Register is spare register is not used.
Because INT2 is removed, this0xBB GPIO_IMR2B Register is used Register is spare register is not used.
Because INT2 is removed, this0xBC GPIO_IMR3B Register is used Register is spare register is not used.
0xC2 GPIO_EDR3 Bits [1:0] used Bits [1:0] spare GPIO8 is removed.
0xC4 GPIO_EDR5 Bits [3:2] used Bits [3:2] spare GPIO17 is removed.
9SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
Register Differences www.ti.com
Table 4. USB Registers
Address Register Name TPS65950 TPS65951 Comment
0x00 PRODUCT_ID_LOW 0x2 0x5 USB ID changed
Bits [6:4] and [0] used0x19 CARKIT_CTRL Bits [6:4] and [0] reserved Feature removedfor audio
Bits [6:4] and [0] used0x1A CARKIT_CTRL_SET Bits [6:4] and [0] reserved Feature removedfor audio
Bits [6:4] and [0] used0x1B CARKIT_CTRL_CLR Bits [6:4] and [0] spare Feature removedfor audio
0x1C CARKIT_INT_DELAY Bits [6:0] used Bits [6:0] spare Feature removed
0x1D CARKIT_INT_EN Bits [4:2] used Bits [4:2] spare Feature removed
0x1E CARKIT_INT_EN_SET Bits [4:2] used Bits [4:2] spare Feature removed
0x1F CARKIT_INT_EN_CLR Bits [4:2] used Bits [4:2] spare Feature removed
0x20 CARKIT_INT_STS Bits [2:1] used Bits [2:1] reserved Feature removed
0x21 CARKIT_INT_LATSH Bits [2:1] used Bits [2:1] reserved Feature removed
0x22 CARKIT_PLS_CTRL Bits [3:0] used Bits [3:0] spare Feature removed
0x23 CARKIT_PLS_CTRL_SET Bits [3:0] used Bits [3:0] spare Feature removed
0x24 CARKIT_PLS_CTRL_CLR Bits [3:0] used Bits [3:0] spare Feature removed
0x25 TRANS_POS_WIDTH Bits [7:0] used Bits [7:0] spare Feature removed
0x26 TRANS_NEG_WIDTH Bits [7:0] used Bits [7:0] spare Feature removed
0x27 RCV_PLTY_RECOVERY Bits [7:0] used Bits [7:0] spare Feature removed
0x30 MCPC_CTRL Bits [7:2] used Bits [7:2] spare Feature removed
0x31 MCPC_CTRL_SET Bits [7:2] used Bits [7:2] spare Feature removed
0x32 MCPC_CTRL_CLR Bits [7:2] used Bits [7:2] spare Feature removed
0x33 MCPC_IO_CTRL Bits [5]/[3]/[2] used Bits [5]/[3]/[2] spare Feature removed
0x34 MCPC_IO_CTRL_SET Bits [5]/[3]/[2] used Bits [5]/[3]/[2] spare Feature removed
0x35 MCPC_IO_CTRL_CLR Bits [5]/[3]/[2] used Bits [5]/[3]/[2] spare Feature removed
New feature added inBits [7:6] and [2] spare, bit TPS65951.0x80 OTHER_FUNC_CTRL Bits [7:6] and [2] used 0 used Bit 0: If 0, then OTG 1.3
and if 1 then OTG 2.0.
0x81 OTHER_FUNC_CTRL_SET Bits [7:6] and [2] used Bits [7:6] and [2] spare Feature removed
0x82 OTHER_FUNC_CTRL_CLR Bits [7:6] and [2] used Bits [7:6] and [2] spare Feature removed
0x83 OTHER_IFC_CTRL Bit [1] used Bit [1] spare Feature removed
0x84 OTHER_IFC_CTRL_SET Bit [1] used Bit [1] spare Feature removed
0x85 OTHER_IFC_CTRL_CLR Bit [1] used Bit [1] spare Feature removed
0x86 OTHER_INT_EN_RISE Bit [1] used Bit [1] spare Feature removed
0x87 OTHER_INT_EN_RISE_SET Bit [1] used Bit [1] spare Feature removed
0x88 OTHER_INT_EN_RISE_CLR Bit [1] used Bit [1] spare Feature removed
0x89 OTHER_INT_EN_FALL Bit [1] used Bit [1] spare Feature removed
0x8A OTHER_INT_EN_FALL_SET Bit [1] used Bit [1] spare Feature removed
0x8B OTHER_INT_EN_FALL_CLR Bit [1] used Bit [1] spare Feature removed
0x8C OTHER_INT_STS Bit [1] used Bit [1] spare Feature removed
0x8D OTHER_INT_LATCH Bit [1] used Bit [1] spare Feature removed
0x97 CARKIT_SM_1_INT_EN Register removed Feature removed
0x98 CARKIT_SM_1_INT_EN_SET Register removed Feature removed
0x99 CARKIT_SM_1_INT_EN_CLR Register removed Feature removed
0x9A CARKIT_SM_1_INT_STS Register removed Feature removed
0x9B CARKIT_SM_1_INT_LATCH Register removed Feature removed
0x9C CARKIT_SM_2_INT_EN Register removed Feature removed
0x9D CARKIT_SM_2_INT_EN_SET Register removed Feature removed
0x9E CARKIT_SM_2_INT_EN_CLR Register removed Feature removed
10 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com Register Differences
Table 4. USB Registers (continued)
0x9F CARKIT_SM_2_INT_STS Register removed Feature removed
0xA0 CARKIT_SM_2_INT_LATCH Register removed Feature removed
0xA1 CARKIT_SM_CTRL Register removed Feature removed
0xA2 CARKIT_SM_CTRL_SET Register removed Feature removed
0xA3 CARKIT_SM_CTRL_CLR Register removed Feature removed
0xA4 CARKIT_SM_CMD Register removed Feature removed
0xA5 CARKIT_SM_CMD_SET Register removed Feature removed
0xA6 CARKIT_SM_CMD_CLR Register removed Feature removed
0xA7 CARKIT_SM_CMD_STS Register removed Feature removed
0xA8 CARKIT_SM_STATUS Register removed Feature removed
0xA9 CARKIT_SM_NEXT_STATUS Register removed Feature removed
0xAA CARKIT_SM_ERR_STATUS Register removed Feature removed
0xAB CARKIT_SM_CTRL_STATE Register removed Feature removed
0xC2 TPH_DP_CON_MIN Register removed Feature removed
New feature added inTPS65951. Addedcontrol for modifying
0xB8 OTHER_FUNC_CTRL2 Bits [7:1] reserved Bits [7:1] used output impedance anddrive strength in HSmode for improvingeye-diagram.
New feature added inTPS65951. Addedcontrol for modifying
0xB9 OTHER_FUNC_CTRL2 Bits [7:1] reserved Bits [7:1] used output impedance anddrive strength in HSmode for improvingeye-diagram.
New feature added inTPS65951. Addedcontrol for modifying
0xBA OTHER_FUNC_CTRL2 Bits [7:1] reserved Bits [7:1] used output impedance anddrive strength in HSmode for improvingeye-diagram.
0xC3 TPH_DP_CON_MAX Register removed Feature removed
0xC4 TCR_DP_CON_MIN Register removed Feature removed
0xC5 TCR_DP_CON_MAX Register removed Feature removed
0xC6 TPH_DP_PD_SHORT Register removed Feature removed
0xC7 TPH_CMD_DLY Register removed Feature removed
0xC8 TPH_DET_RST Register removed Feature removed
0xC9 TPH_AUD_BIAS Register removed Feature removed
0xCA TCR_UART_DET_MIN Register removed Feature removed
0xCB TCR_UART_DET_MAX Register removed Feature removed
0xCD TPH_ID_INT_PW Register removed Feature removed
0xCE TACC_ID_INT_WAIT Register removed Feature removed
0xCF TACC_ID_INT_PW Register removed Feature removed
0xD0 TPH_CMD_WAIT Register removed Feature removed
0xD1 TPH_ACK_WAIT Register removed Feature removed
0xD2 TPH_DP_DISC_DET Register removed Feature removed
0xE0 CARKIT_4W_DEBUG Register removed Feature removed
0xE1 CARKIT_5W_DEBUG Register removed Feature removed
0xF6 PSM_EN_TEST_SET Register removed Feature removed
0xF7 PSM_EN_TEST_CLR Register removed Feature removed
11SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
Register Differences www.ti.com
Table 5. Power Registers
Address Register Name TPS65950 TPS65951 Comment
Bit [5] used for battery presence,Bit [5] unused Bit 5 used hardware pin is MANU_BRIX.0x2E PWR_ISR1 Bit [1] used Bit 1 spare No VAC capability available, so
no CHG_PRES interrupt.
Bit [5] used for battery presence,Bit [5] unused Bit 5 used hardware pin is MANU_BRIX.0x2F PWR_IMR1 Bit [1] used Bit 1 spare No VAC capability available, so
no CHG_PRES interrupt.
0x30 PWR_ISR2 Used Spare INT2 removed
0x31 PWR_IMR2 Used Spare INT2 removed
No VAC capability available, so0x33 PWR_EDR1 Bits [3:2] used Bits [3:2] spare no CHG_PRES interrupt
Used for battery presence,0x34 PWR_EDR2 Bits [5:4] spare Bits [5:4] used hardware pin is MANU_BRIX.
Not possible to mask power-upevents anymore(STARTON_xxx). Bit [7]RO, reset 3F0x36 CFG_P1_TRANSITION R/W, reset 0xFF (SWBUG) power up event isBit 1 spare removed.Bit [1] not used as VACcapability is removed.
Not possible to mask power-upevents anymore(STARTON_xxx). Bit [7]RO, reset 3F0x37 CFG_P2_TRANSITION R/W, reset 0xFF (SWBUG) power-up event isBit 1 spare removed.Bit [1] not used as VACcapability is removed.
Not possible to mask power-upevents anymore(STARTON_xxx). Bit [7]RO, reset 0x7F0x38 CFG_P3_TRANSITION R/W, reset 0xFF (SWBUG) power-up event isBit 1 spare removed.Bit [1] not used as VACcapability is removed.
Because bits [6:0] are RO inTPS65951 it is not possible tochange these features. Refer to
Bits [6:0] R/W, reset detailed description in the0x39 CFG_P123_TRANSITION Bits [6:0] RO, reset 0x2B0x2B register file.*Bit [7] is EEPROM dependant;must take care to set it properlyfor software compatiblity.
BCI module is removed so this0x3D BOOT_BCI Used Spare register is not used.
config_key unlock sequence0x44 PROTECTED_KEY Bits [7:0] Bits [7:0] modified
Refer to register manual.
Internally the two control signalsSLEEP1 and SLEEP2 are tiedtogether. Both of these internalBit [5] Bit [5]0x45 STS_HW_CONDITION signals can be controlled byBit [1] used Bit [1] spare SLEEP1 (available externally).Bit [1] (STS_CHG) always 0 asno VAC.
STOPON_PWRON always on0x46 P1_SW_EVENTS Bit [6] R/W, reset 0 Bit [6] RO, reset 1 (PWRON_8s feature cannot be
disabled)
STOPON_PWRON always on0x47 P2_SW_EVENTS Bit [6] R/W, reset 0 Bit [6] RO, reset 1 (PWRON_8s feature cannot be
disabled)
12 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com Register Differences
Table 5. Power Registers (continued)
Address Register Name TPS65950 TPS65951 Comment
STOPON_PWRON always on0x48 P3_SW_EVENTS Bit [6] R/W, reset 0 Bit [6] RO, reset 1 (PWRON_8s feature cannot be
disabled)
VBUS/ID power-up eventdebounce time increased to 2330x51 RESERVED_E Bits [2:0] reserved Bits [2:0] RW, reset 0x7 ms to disable USB 500 chargerdetection compliancy.
32k drive capability default is 50x68 MISC_CFG Bit [4] reset = 1 Bit [4] reset = 0 pF now (instead of 40 pF)
0x92 VSIM_DEV_GRP Used Spare VSIM removed in TPS65951
0x93 VSIM_TYPE Used Spare VSIM removed in TPS65951
0x94 VSIM_REMAP Used Spare VSIM removed in TPS65951
0x95 VSIM_DEDICATED Used Spare VSIM removed in TPS65951
Bits [7:5]: VSEL, RWBits [7:5]: Reserved Refer to new register descriptionBits [3:2]: USBIN_SW,0xD8 VUSB_DEDICATED1 Bit [3]: SW2VBAT and the specifications for newRW,Bit [2]: SW2VBUS architecture on TPS65951.Reset: 0x1
32k clock resource cannot be0xE9 32KCLKOUT_DEV_GRP Bits [7:5] RW Bits [7:5] RO unassigned to the processors:
always on in ACTIVE state.
32k clock resource active state0xEB 32KCLKOUT_REMAP Bits [3:0] RW Bits [3:0] RO cannot be remap: always on in
ACTIVE state.
Main ref resource cannot be0xEF MAINREF_DEV_GRP Bits [7:5] RW Bits [7:5] RO unassigned to the processors:
always on in ACTIVE state
Main ref resource active state0xF1 MAINREF_REMAP Bits [3:0] RW Bits [3:0] RO cannot be remap: always on in
ACTIVE state.
13SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
Register Differences www.ti.com
Table 6. Auxillary Registers
Address Register Name TPS65950 TPS65951 Comment
External channels ADCIN4,0x02 RTSELECT_LSB Bits [6:4] used Bits [6:4] spare ADCIN5, and ADCIN6 removed
Channel 10 (ICHG), 11 (VCHG),0x3 RTSELECT_M+B43SB Bits [3:2] used Bits [3:2] spare 15 (USBMEAS) removed
External channels ADCIN4-5-60x04 RTAVERAGE_LSB Bits [6:4] used Bits [6:4] spare removed
Channel 10 (ICHG), 11 (VCHG),0x05 RTAVERAGE_MSB Bits [3:2] used Bits [3:2] spare 15 (USBMEAS) removed
External channels ADCIN4,0x06 SW1SELECT_LSB Bits [6:4] used Bits [6:4] spare ADCIN5, and ADCIN6 removed
Channel 10 (ICHG), 11 (VCHG),0x07 SW1SELECT_MSB Bits [3:2] used Bits [3:2] spare 15 (USBMEAS) removed
External channels ADCIN4,0x08 SW1AVERAGE_LSB Bits [6:4] used Bits [6:4] spare ADCIN5, and ADCIN6 removed
Channel 10 (ICHG), 11 (VCHG),0x09 SW1AVERAGE_MSB Bits [3:2] used Bits [3:2] spare 15 (USBMEAS) removed
External channels ADCIN4,0x0A SW2SELECT_LSB Bits [6:4] used Bits [6:4] spare ADCIN5, and ADCIN6 removed
Channel 10 (ICHG), 11 (VCHG),0x0B SW2SELECT_MSB Bits [3:2] used Bits [3:2] spare 15 (USBMEAS) removed
External channels ADCIN4,0x0C SW2AVERAGE_LSB Bits [6:4] used Bits [6:4] spare ADCIN5, and ADCIN6 removed
Channel 10 (ICHG), 11 (VCHG),0x0D SW2AVERAGE_MSB Bits [3:2] used Bits [3:2] spare 15 (USBMEAS) removed
Test register became functionalregister: acquistion time can be0x0F ACQUISITION Bits [7:4] reserved Bits [7:4] used configured in a wider range andapplies to all conversions.
No EOC_BCI as no more BCI0x12 CTRL_SW1 Bit [3] used Bit [3] spare conversion
No EOC_BCI as no more BCI0x13 CTRL_SW2 Bit [3] used Bit [3] spare conversion
External channel ADCIN40x1F RTCH4_LSB Spare removed
External channel ADCIN40x20 RTCH4_MSB Spare removed
External channel ADCIN50x21 RTCH5_LSB Spare removed
External channel ADCIN50x22 RTCH5_MSB Spare removed
External channel ADCIN60x23 RTCH6_LSB Spare removed
External channel ADCIN60x24 RTCH6_MSB Spare removed
0x2B RTCH10_LSB Spare ICHG channel removed
0x2C RTCH10_MSB Spare ICHG channel removed
0x2D RTCH11_LSB Spare VCHG channel removed
0x2E RTCH11_MSB Spare VCHG channel removed
External channel ADCIN40x3F GPCH4_LSB Spare removed
External channel ADCIN40x40 GPCH4_MSB Spare removed
External channel ADCIN50x41 GPCH5_LSB Spare removed
External channel ADCIN50x42 GPCH5_MSB Spare removed
14 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com Register Differences
Table 6. Auxillary Registers (continued)
Address Register Name TPS65950 TPS65951 Comment
External channel ADCIN60x43 GPCH6_LSB Spare removed
External channel ADCIN60x44 GPCH6_MSB Spare removed
0x4B GPCH10_LSB Spare ICHG channel removed
0x4C GPCH10_MSB Spare ICHG channel removed
0x4D GPCH11_LSB Spare VCHG channel removed
0x4E GPCH11_MSB Spare VCHG channel removed
0x57 BCICH0_LSB Spare BCI conversions removed
0x58 BCICH0_MSB Spare BCI conversions removed
0x59 BCICH1_LSB Spare BCI conversions removed
0x5A BCICH1_MSB Spare BCI conversions removed
0x5B BCICH2_LSB Spare BCI conversions removed
0x5C BCICH2_MSB Spare BCI conversions removed
0x5D BCICH3_LSB Spare BCI conversions removed
0x5E BCICH3_MSB Spare BCI conversions removed
0x5F BCICH4_LSB Spare BCI conversions removed
0x60 BCICH4_MSB Spare BCI conversions removed
0x63 MADC_ISR2 Spare INT2 line removed
0x64 MADC_IMR2 Spare INT2 line removed
GAIA BCI removed and0x74 → 0xC6 BCI registers replaced: refer to TPS65951 BCI
register description
0xE5 KEYP_ISR2 Spare INT2 line removed
0xE6 KEYP_IMR2 Spare INT2 line removed
15SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
4 TPS65951 Registers – Accessory and BCI
This section presents a summary of the hardware interface for the TPS65951 product. Each moduleinstance within the design is shown below, together with the module register map and bit definitions foreach bit field.
4.1 Instance Summary
The table below shows the base address and address space for the TPS65951 module instances.
Table 7. Instance Summary
Module Name Base Address Size
ACCESSORY VINTDIG 0x0000 0074 43 bytes
BCC VPRECH 0x0000 00AA 21 bytes
4.2 ACCESSORY VINTDIG
This section provides information on the accessories module instances within this product. Each of theregisters within the module instance is described separately below.
4.2.1 ACCESSORY VINTDIG Register Summary
Table 8. ACCESSORY VINTDIG Register Summary
Register RegisterRegister Name Type Width Address OffsetReset(Bits)
AUDIO_CTRL RW 8 0x00 0x81
BCIA_CTRL RW 8 0x00 0x82
SPARE1 RO 8 0x00 0x8D
SPARE2 RW 8 0x00 0x8E
FACTDATA0 RO 8 0x00 0x8F
FACTDATA1 RO 8 0x00 0x90
FACTDATA2 RO 8 0x00 0x91
FACTDATA3 RO 8 0x00 0x92
FACTDATA4 RO 8 0x00 0x93
FACTDATA5 RO 8 0x00 0x94
FACTDATA6 RO 8 0x00 0x95
FACTDATA7 RO 8 0x00 0x96
FACTDATA8 RO 8 0x00 0x97
FACTDATA9 RO 8 0x00 0x98
FACTDATA10 RO 8 0x00 0x99
16 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com TPS65951 Registers – Accessory and BCI
4.2.2 ACCESSORY VINTDIG Register Description
Table 9. AUDIO_CTRL
Address Offset 0x81
Description
Type RW
7 6 5 4 3 2 1 0
RESERVED RX2TX_PATH_EN
RX
2TX
_LO
OP
_EN
Bits Field Name Description Type Reset
7:4 RESERVED RO 0x0
R returns0s
3:1 RX2TX_PATH_EN Audio loop path selection. Only available if RX2TX_LOOP_EN bit is set RW 0x0to 1.
0x0: Audio Left path 1 is root.
0x1: Audio Right path 1 is root.
0x2: Audio Left path 2 is root.
0x3: Audio Right path 2 is root.
0x4: Voice path is root.
0 RX2TX_LOOP_EN Audio loop path defined in RX2TX_PATH_SEL register is set when this RW 0bit is set to 1.
Table 10. BCIA_CTRL
Address Offset 0x82
Description
Type RW
7 6 5 4 3 2 1 0
RESERVED BTEMP_EN RESERVED MESBAT_EN
Bits Field Name Description Type Reset
7:3 RESERVED RO 0x00R returns
0s
2 BTEMP_EN Must be set to 1 before TEMP measure through MADC RW 0
1 RESERVED RO 0R returns
0s
0 MESBAT_EN Must be set to 1 before battery measure through MADC RW 0
17SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
Table 11. SPARE1
Address Offset 0x8D
Description
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
Table 12. SPARE2
Address Offset 0x8E
Description
Type RW
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RW 0X00
Table 13. FACTDATA0
Address Offset 0x8F
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
Table 14. FACTDATA1
Address Offset 0x90
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
18 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com TPS65951 Registers – Accessory and BCI
Table 15. FACTDATA2
Address Offset 0x91
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
Table 16. FACTDATA3
Address Offset 0x92
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
Table 17. FACTDATA4
Address Offset 0x93
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
Table 18. FACTDATA5
Address Offset 0x94
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
19SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
Table 19. FACTDATA6
Address Offset 0x95
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
Table 20. FACTDATA7
Address Offset 0x96
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
R returns0s
Table 21. FACTDATA8
Address Offset 0x97
Description EEPROM register bits
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
R returns0s
Table 22. FACTDATA9
Address Offset 0x98
Description
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
R returns0s
20 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com TPS65951 Registers – Accessory and BCI
Table 23. FACTDATA10
Address Offset 0x99
Description
Type RO
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RO 0X00
R returns0s
21SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
4.3 Battery Charger Control VPRECH – Battery Charger Controller (VPRECH Domain)
This section provides information on the BCC Module Instance within this product. Each of the registerswithin the Module Instance is described separately below.
4.3.1 BCC VPRECH Register Summary
Table 24. ACC_VPRECH Register Summary
Register RegisterRegister Name Type Width Physical AddressReset(Bits)
BCC_CTRL RW 8 0x04 0xAA
BCC_CTRL2 RW 8 0x00 0xAB
BCC_STS RO 8 0x20 0xAC
USB_CHRG_CTRL1 RW 8 0x00 0xAD
USB_CHRG_CTRL2 RW 8 0x00 0xAE
LED_DRIVER_CTRL RW 8 0x02 0xAF
FACTCFG0_VPRCH RW 8 0x40 0xB3
FACTCFG1_VPRCH RW 8 0x00 0xB4
SPARE1_VPRECH RW 8 0x00 0xB5
SPARE2_VPRECH RO 8 0x00 0xB6
BCIISR1 RW 8 0x00 0xB9
BCIIMR1 RW 8 0x7F 0xBA
BCISIR RW 8 0x00 0xBD
BCIEDR1 RW 8 0x66 0xBE
BCISIHCTRL RW 8 0x00 0xC0
22 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com TPS65951 Registers – Accessory and BCI
4.3.2 ACC_VRPECH Register Descriptions
Table 25. BCC_CTRL
Address Offset 0xAA
Description Battery charger controller (BCC) enable and status bits.
Type RW
7 6 5 4 3 2 1 0
RESERVED SW_CHRGOFF
WA
TC
HD
OG
_RS
T
WA
TC
HD
OG
_MA
X_C
HG
EN
_TIM
E
Bits Field Name Description Type Reset
7:4 RESERVED RO 0x0R returns0s
3:2 WATCHDOG_MAX_ Set the value of watchdog maximum charger enable time RW 0x1CHGEN_TIME when CHGMODE_SW is set to 1.
00: Counter maximum value set to 16 seconds.
01: Counter maximum value set to 32 seconds.
10: Counter maximum value set to 64 seconds.
11: Counter maximum value set to 127 seconds.
1 WATCHDOG_RST 0: Normal operation mode RW 0W Toggle1: Watchdog is reset. Maximum counter value is load.
Set automatically to 0. Value 1 is not available on OCPread access.
0 SW_CHRGOFF 0: Normal operation mode RW 0W Toggle1: Reset all charger logic and enable signals
Software reset of all charger logic and control signals.
Clear of the reset is done by writing 0 in the register.
Table 26. BCC_CTRL2
Address Offset 0xAB
Description Battery charger controller (BCC) software control register.
Type RW
7 6 5 4 3 2 1 0
RESERVED RESERVED
CH
GM
OD
E_S
W
SW
_US
B_D
ET
_EN
SW
_VA
CC
HR
G_E
N
SW
_US
BC
HA
RG
_EN
23SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
Bits Field Name Description Type Reset
7:5 RESERVED RO 0x0
4 SW_USB_DET_EN SW enable of USB detection. Enable charger detection RW 0(used to enable CHGD IBIAS block).
3 SW_CHRG_DET SelectUSB charger driven current . Only active when RW 0CHMODE_SW is set to 1. Set CHRG_DET signal.
Status of CHRG_EN signal when CHMODE_SW is setto 0.
0: 100-mA charger type
1: 500-mA charger type
2 RESERVED RO 0x0
1 SW_USBCHRG_EN Only active when CHMODE_SW is set to 1. Set RW 0USBCHRG_EN signal.
0: USBCHRG_EN signal is 0 (USB charger is disabled).
1: USBCHRG_EN signal is 1 (USB charger is enabled).
Status of USBCHRG_EN signal when CHMODE_SW isset to 0.
Read 0: USBCHRG_EN signal is 0 (USB charger isdisabled).
Read 1: USBCHRG_EN signal is 1 (USB charger isenabled).
This bit is reset to 0 wheh the BATTERY_PRESENCEsignal is 0 (battery pack is removed).
0 CHGMODE_SW When set to 1, software directly controls enable signals. RW 0FSM control is bypass and FSM is reset.
0: Software control is disabled.
1: Software control is enabled.
Cannot be set to 0 by software access.
Table 27. BCC_STS
Address Offset 0xAC
Description Battery charger controller (BCC) status bits.
Type RO
7 6 5 4 3 2 1 0
RESERVED VPRECH_STS RESERVED USB_P_STS USB_DET_STS
BA
TT
ER
Y_P
RE
SE
NC
E_S
TS
Bits Field Name Description Type Reset
7:6 RESERVED RO 0x0
5 VPRECH_STS Asserted when VPRECH supply is present. RO 1
Read 0: VPRECH not present or under reset
Read 1: VPRECH present
4 BATTERY_PRESENCE_ Status of battery presence. RO 0STS
0: Battery not present
24 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com TPS65951 Registers – Accessory and BCI
Bits Field Name Description Type Reset
1: Battery present
3 RESERVED RO 0
2 USB_P_STS Status of USBVBUS_PRES signal with 30 ms RO 0debounce time.
When set to 1, FSM is active(according toCHGMODE_SW)
1:0 USB_DET_STS Status of USB charger presence and USB charger RO 0x0type.
Read 0x0: 00 => No USB charger detected
Read 0x1: 01 => 100-mA charger detected
Read 0x2: 10 => 500-mA charger detected
Read 0x3: 11 => Undefined
Table 28. USB_CHRG_CTRL1
Address Offset 0xAD
Description
Type RW
7 6 5 4 3 2 1 0
VB
US
OV
_PR
EC
H
CH
GD
_VD
X_L
OW
V
US
B_S
W_C
TR
L_E
N
CH
GD
_SE
RX
_DP
_LO
WV
CH
GD
_SE
RX
_EN
_LO
WV
CH
GD
_SE
RX
_DM
_LO
WV
CH
GD
_ID
X_S
RC
_EN
_LO
WV
CH
GD
_VD
X_S
RC
_EN
_LO
WV
Bits Field Name Description Type Reset
7 VBUSOV_PRECH Status of VBUSOVPRECH RO 0
6 CHGD_SERX_DM_ Dedicated CHGD SERX DM comparator output used in RO 0LOWV contact detect if DPDM_SWAP EEPROM bit is 1
5 CHGD_SERX_DP_ Dedicated CHGD SERX DP comparator output used in RO 0LOWV contact detect if DPDM_SWAP EEPROM bit is 0
4 CHGD_VDX_LOWV VDAT_REF DM comparator output used in charger RO 0detect if DPDM_SWAP EEPROM bit is 0.
VDAT_REF DP comparator output used in chargerdetect if DPDM_SWAP EEPROM bit is 1.
3 CHGD_SERX_EN_ Enable SERX comparators on DP and DM RW 0LOWV
2 CHGD_VDX_SRC_ Enable VDP_SRC buffer, IDM_SINK, and RW 0EN_LOWV VDAT_REF_DM comp if DPDM_SWAP EEPROM bit is
0.
Enable VDM_SRC buffer, IDP_SINK, andVDAT_REF_DP comp if DPDM_SWAP EEPROM bit is1.
1 CHGD_IDX_SRC_ Enable IDP_SRC and RDM_DWN if DPDM_SWAP RW 0EN_LOWV EEPROM bit is 0.
Enable IDM_SRC and RDP_DWN if DPDM_SWAPEEPROM bit is 1.
0 USB_SW_CTRL_EN Let the software control USB current sources and RW 0comparator outputs directly through register.
25SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
Bits Field Name Description Type Reset
USB dedicated FSM for detection is bypassed if this bitis set to 1.
Table 29. USB_CHRG_CTRL2
Address Offset 0xAE
Description
Type RW
7 6 5 4 3 2 1 0
RESERVED USB_500 USB_100
Bits Field Name Description Type Reset
7:2 RESERVED RO 0x00R returns 0s
1 USB_500 Sets the USB500_P signal. This bit can be written when the RW 0USB_SW_CTRL_EN bit is set to 1.
0: USB500_P signal is 0.
1: USB500_P signal is 1.
Status of FSM USB500_P signal when USB_SW_CTRL_EN bitis set to 0. In this case, a write to this bit has no effect.
0 USB_100 Sets the USB100_P signal. This bit can be written when the RW 0USB_SW_CTRL_EN bit is set to 1.
0: USB100_P signal is 0.
1: USB100_P signal is 1.
Status of FSM USB100_P signal when USB_SW_CTRL_EN bitis set to 0. In this case, a write to this bit has no effect.
Table 30. LED_DRIVER_CTRL
Address Offset 0xAF
Description
Type RW
7 6 5 4 3 2 1 0
RESERVED LEDC_PLS_WIDTH LEDC_SW_EN LEDCCTRL
LED
C_S
WM
OD
E
Bits Field Name Description Type Reset
7 RESERVED RO 0R returns 0s
6:5 LEDC_PLS_WIDTH Select pulse width modulation of LED flashing RW 0x0
00: LED always on
01: 1.0 sec
10: 1.5 sec
11: 2.0 sec
4 LEDC_SW_EN Enable LED driver feature managed by software RW 0
0: LED is disabled.
1: LED is enabled.
26 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com TPS65951 Registers – Accessory and BCI
Bits Field Name Description Type Reset
3 LEDC_SWMODE Enable switch between hardware LED driver controller RW 0mode and SW LED driver control mode
0: LED enable is controlled by the hardware LED drivercontroller.
1: LED enable is controlled with LEDC_SW_EN.
2:0 LEDCCTRL Defined current of LED driver RW 0x2
000: 3.5 mA
001: 0.875 mA
010: 1.75 mA
011: 7 mA
100: 14 mA
Other codes: 0 mA
Table 31. FACTCFG0_VPRCH
Address Offset 0xB3
Description EEPROM bits for VPRECH calibration. Can be written only during test mode.
Type RW
7 6 5 4 3 2 1 0
DPDM_SWAP DATACON_EN IPRECH_TRIM
CH
RG
_DE
T_C
FG
WA
TC
HD
OG
16_3
2
Bits Field Name Description Type Reset
7 DPDM_SWAP EEPROM register. Reset value set by EEPROM. RW 0SWAP DP/DM for charger detection.
6 CHRG_DET_CFG Reset value set by EEPROM bit RW 1
CHG_DET_CFG default value given by EEPROM andis equal to 1.
0: CHRG_DET_N output = CHRG_DET signal
1: CHRG_DET_N output = Not CHRG_DET signal
5 DATACON_EN Reset value set by EEPROM RW 1
Default value of DATACON_EN given by EEPROMmust be 1.
Data connection state of USB charger detectionstate-machine
0: Bypass
1: Normal mode
4 WATCHDOG16_32 EEPROM reset value. Default value of DATACON_EN RW 0given by EEPROM must be 1.
0: 32 minutes when HW control.
1: 16 minutes when HW control.
3:0 IPRECH_TRIM RW 0x0
27SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
Table 32. FACTCFG1_VPRCH
Address Offset 0xB4
Description EEPROM bits for VPRECH calibration. Can be written only during test mode.
Type RW
7 6 5 4 3 2 1 0
RESERVED
Bits Field Name Description Type Reset
7:0 RESERVED RW 0x00
Table 33. SPARE1_VPRECH
Address Offset 0xB5
Description Spare register.
Type RW
7 6 5 4 3 2 1 0
RESERVED NEWBITFIELD1
Bits Field Name Description Type Reset
7:4 RESERVED RO 0x0R returns 0s
3:0 NEWBITFIELD1 BCI dedicated spare bits. RW 0x0
Table 34. SPARE2_VPRECH
Address Offset 0xB6
Description Spare register.
Type RO
7 6 5 4 3 2 1 0
RESERVED NEWBITFIELD1
Bits Field Name Description Type Reset
7:4 RESERVED RO 0x0R returns 0s
3:0 NEWBITFIELD1 BCI dedicated spare bits. RO 0x0
28 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com TPS65951 Registers – Accessory and BCI
Table 35. BCIISR1
Address Offset 0xB9
Description The INTERRUPT STATUS ISR1 register is used to determine which monitoring function interrupt triggered theinterrupt line PO_BCI_SIH_INT1_N request. When a bit in this register is set to 1, it indicates that thecorresponding monitoring function is requesting the interrupt.However, the user cannot generate an interrupt by writing 1 to the INTERRUPT STATUS ISR1 register.When a bit in this register is set to 1, then the corresponding interrupt line is released. If the user writes a 0 to abit in this register, the value remains unchanged.The INTERRUPT STATUS ISR1 register is synchronous with the interface OCP clock.
Type RW
7 6 5 4 3 2 1 0
RESERVED
US
B_E
RR
OR
_IS
R1
US
B_C
HG
ST
OP
_IS
R1
US
B_C
HG
ST
AR
T_I
SR
1
WA
TC
HD
OG
_TIM
EO
UT
_IS
R1
Bits Field Name Description Type Reset
7:4 RESERVED RO 0x0R returns 0s
3 USB_CHGSTOP_ Write 0: No impact. Register keeps its value. RW 0ISR1 Read 0: No interrupt set
Read 1: Interrupt set
Write 1: When set to 1, the corresponding interruptline is released.
2 USB_CHGSTART_ Write 0: No impact. Register keeps its value. RW 0ISR1 Read 0: No interrupt set
Read 1: Interrupt set
Write 1: When set to 1, the corresponding interruptline is released.
1 USB_ERROR_ Write 0: No impact. Register keeps its value. RW 0ISR1 Read 0: No interrupt set
Read 1: Interrupt set
Write 1: When set to 1, the corresponding interruptline is released.
0 WATCHDOG_ Write 0: No impact. Register keeps its value. RW 0TIMEOUT_ISR1 Read 0: No interrupt set
Read 1: Interrupt set
Write 1: When set to 1, the corresponding interruptline is released.
29SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
Table 36. BCIIMR1
Address Offset 0xBA
Description The INTERRUPT MASK IMR1 REGISTER allows the user to mask the expected transition on end of sequencefrom generating an interrupt request on PO_BCI_SIH_INT1_N.The interrupt mask registers are programmed synchronously with the interface OCP clock.
Type RW
7 6 5 4 3 2 1 0
RESERVED
US
B_E
RR
OR
_IM
R1
US
B_C
HG
ST
OP
_IM
R1
US
B_C
HG
ST
AR
T_I
SR
1
WA
TC
HD
OG
_TIM
EO
UT
_IM
R1
Bits Field Name Description Type Reset
7:4 RESERVED RO 0
3 USB_CHGSTOP_IMR1 0: Interrupt is not masked. RW 1
1: Interrupt is masked.
2 USB_CHGSTART_IMR1 0: Interrupt is not masked. RW 1
1: Interrupt is masked.
1 USB_ERROR_IMR1 0: Interrupt is not masked. RW 1
1: Interrupt is masked.
0 WATCHDOG_TIMEOUT_ 0: Interrupt is not masked. RW 1IMR1 1: Interrupt is masked.
Table 37. BCISIR
Address Offset 0xBD
Description For test purposes, the BCI SOFTWARE INTERRUPT register allows generating an interrupt event on thePO_BCI_SIH_INT1_N or PO_BCI_SIH_INT2_N request line by writing 1 to the targeted SIR bit in a specific testmode.An interrupt is generated if the corresponding BCI_EDR bit is set to edge (falling or rising) sensitive.External interrupt requests and internal software requests are merged before being sent to the PIH.
Type RW
7 6 5 4 3 2 1 0
RESERVED
US
B_E
RR
OR
_SIR
US
B_C
HG
ST
OP
_SIR
US
B_C
HG
ST
AR
T_S
IR
WA
TC
HD
OG
_TIM
EO
UT
_SIR
30 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
www.ti.com TPS65951 Registers – Accessory and BCI
Bits Field Name Description Type Reset
7:4 RESERVED RO 0
3 USB_CHGSTOP_SIR 0: Software interrupt not set RW 0
1: Software interrupt set
2 USB_CHGSTART_SIR 0: Software interrupt not set RW 0
1: Software interrupt set
1 USB_ERROR_SIR 0: Software interrupt not set RW 0
1: Software interrupt set
0 WATCHDOG_TIMEOUT_ 0: Software interrupt not set RW 0SIR 1: Software interrupt set
Table 38. BCIEDR1
Address Offset 0xBE
Description The INTERRUPT EDGE DETECTION register bit BCI_EDR allows the user to define, for all incoming interruptlines, the expected edge to trigger an interrupt request.The interrupt request can be generated either from a high-to-low transition (bits are 01), a low-to-high transition(bits are 10), or both transitions (bits are 11) accruing.To disable the edge detection capability, the relevant bits must be reset (00).
Type RW
7 6 5 4 3 2 1 0U
SB
_ER
RO
R_E
DR
RIS
ING
US
B_E
RR
OR
_ED
RF
ALL
ING
US
B_C
HG
ST
OP
_ED
RR
ISIN
G
US
B_C
HG
ST
AR
T_E
DR
RIS
ING
US
B_C
HG
ST
OP
_ED
RF
ALL
ING
US
B_C
HG
ST
AR
T_E
DR
FA
LLIN
G
WA
TC
HD
OG
_TIM
EO
UT
_ED
RR
ISIN
G
WA
TC
HD
OG
_TIM
EO
UT
_ED
RF
ALL
ING
Bits Field Name Description Type Reset
7 USB_CHGSTOP_EDRRISING 0: Rising detection disabled RW 0
1: Rising detection enabled
6 USB_CHGSTOP_EDRFALLING 0: Falling detection disabled RW 1
1: Falling detection enabled
5 USB_CHGSTART_EDRRISING 0: Rising detection disabled RW 1
1: Rising detection enabled
4 USB_CHGSTART_ 0: Falling detection disabled RW 0EDRFALLING 1: Falling detection enabled
3 USB_ERROR_EDRRISING 0: Rising detection disabled RW 1
1: Rising detection enabled
2 USB_ERROR_EDRFALLING 0: Falling detection disabled RW 0
1: Falling detection enabled
1 WATCHDOG_TIMEOUT_ 0: Rising detection disabled RW 1EDRRISING 1: Rising detection enabled
0 WATCHDOG_TIMEOUT_ 0: Falling detection disabled RW 0EDRFALLING 1: Falling detection enabled
31SWCA090–December 2010 Feature Differences Between TPS65950 and TPS65951Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
TPS65951 Registers – Accessory and BCI www.ti.com
Table 39. BCISIHCTRL
Address Offset 0xC0
Description The BCI SIH control register allows the user to disable a pending event incoming during SW interrupt latency byprogramming 1 in the PENDDIS bit.By writing 0 in the EXCLEN bit, the user disables the exclusivity between the interrupt request linePO_BCI_SIH_INT1_N and PO_BCI_SIH_INT2_N.The ClearOnRead bit enables the clear-on-read feature. This means that any read access to the ISR clears thisregister and releases the associated interrupt line (default value).If disabled a read access to a specific address value will clear all ISR within the SIH.
Type RW
7 6 5 4 3 2 1 0
RESERVED COR PENDDIS EXCLEN
Bits Field Name Description Type Reset
7:3 RESERVED RO 0x00R returns 0s
2 COR 0: Clear ISR on write RW 0
1: Clear ISR specific bit field when read access
1 PENDDIS 0: Pending event enabled RW 0
1: Pending event disabled
0 EXCLEN 0: Exclusivity disabled RW 0
1: Exclusivity enabled
32 Feature Differences Between TPS65950 and TPS65951 SWCA090–December 2010Submit Documentation Feedback
© 2010, Texas Instruments Incorporated
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is notresponsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DLP® Products www.dlp.com Communications and www.ti.com/communicationsTelecom
DSP dsp.ti.com Computers and www.ti.com/computersPeripherals
Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps
Interface interface.ti.com Energy www.ti.com/energy
Logic logic.ti.com Industrial www.ti.com/industrial
Power Mgmt power.ti.com Medical www.ti.com/medical
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Space, Avionics & www.ti.com/space-avionics-defenseDefense
RF/IF and ZigBee® Solutions www.ti.com/lprf Video and Imaging www.ti.com/video
Wireless www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2010, Texas Instruments Incorporated