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Wire Modeling
João Canas Ferreira
Universidade do PortoFaculdade de Engenharia
April 2016
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Topics
1 Interconnect Structure
2 Capacitance
3 Resistance
4 Propagation delay
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On-chip interconnects
Schematic Physical
I Real interconnects have a 3D structure
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Interconnect usage
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Example of 3D interconnect structure
Source: [unknown]
I Metal 1 - metal 4I Vias
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Global vs. local interconnect
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Topics
1 Interconnect Structure
2 Capacitance
3 Resistance
4 Propagation delay
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Interconnect capacitance
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Parallel plates
Cint =εditdi
WL
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Relative permittivity of typical dielectrics
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Fringe capacitance
Capacitance per length unit (approximation):
Cwire = Cpp + Cfringe =εdiwtdi
+2πεdi
log(2 tdi/H + 1)w = W –
H2
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Influence of fringe capacitance
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Capacitance between wires
Source: [Rabaey03]
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Impact of interwire capacitance
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Interwire capacitance for a 0.25 µm CMOS process
Source: [Rabaey03]
Areas in aF/µm2, lengths in aF/µm (fringe capacitance, in gray).
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Topics
1 Interconnect Structure
2 Capacitance
3 Resistance
4 Propagation delay
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Resistance of a single wire
Source: [Rabaey03]
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Resistivity of different materials
Source: [Rabaey03]
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Polycide gate
Reducing polysilicon resistivity by a factor of 8–10:
Silicides: WSi2, TiSi2, PtSi2 and TaSi
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Typical sheet resistance
Source: [Rabaey03]
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Example: Intel 0.25 µm process
Source: [Rabaey03]
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Topics
1 Interconnect Structure
2 Capacitance
3 Resistance
4 Propagation delay
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Lumped parameter model
Source: [Rabaey03]
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Elmore delay
Source: [Rabaey03]
à There is just one resistive path between r and any node i (Rii).à Shared path resistance between the paths from r to nodes i and j (Rij):
Rik =∑
Rj where Rj ∈ [path(r→ i) ∩ path(r→ k)]
à Equivalent time constant (dominant pole):
τri =N∑
k=1
CkRik
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Special case: the RC chain
τ =N∑
i=1
Ci
i∑j=1
Rj =N∑
i=1
CiRii
In this case, the path resistance and the shared path resistance are the same.
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Interconnect model by segments
à Consider a line of length L composed of N equal segments
τ =(
LN
)2(rc + 2rc + · · · + Nrc) =
(rcL2
) N(N + 1)
2N2 = RCN + 12N
with
R = rL C = cL
à For large N:
τ =RC2
=rcL2
2
à This is the same result that would be obtained by treating the wire as atransmission line.
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Response of RC wire to a voltage step
Source: [Rabaey03]
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Intermediate RC models
Source: [Rabaey03]
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Distributed RC line
τ = RSCW +RWCW
2= RSCW + 0.5rwcwL2
tp = 0.69RSCW + 0.38RWCW
Practical rule: use a distributed line model only if tpRC ≥ tgate.
Criterion for critical wire length:
Lcrit =
√tpgate
0.38rc
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References
à Some of the figures used come from:
Rabaey03 J. M. Rabaey et al, Digital Integrated Circuits, 2nd edition,Prentice Hall, 2003.http://bwrc.eecs.berkeley.edu/icbook/
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