![Page 1: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/1.jpg)
Explicit Gate Delay Model for Timing Evaluation
Muzhou Shao : University of Texas at Austin
D.F.Wong : U. of Illinois at Urbana- Champaign
Huijing Cao : Motorola, Inc.
Youxin Gao : Synopsys, Inc.,
Li-Pen Yuan : Synopsys, Inc.,
Li-Da Huang : University of Texas at Austin
Seokjin Lee : University of Texas at Austin
![Page 2: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/2.jpg)
• One part of stage delay
• Crucial in timing synthesis/optimization
Value of Gate Modeling
![Page 3: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/3.jpg)
• Switch-resistor model
• k-factor functions
• Lookup table model
Previous Gate Delay Model
![Page 4: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/4.jpg)
Previous Gate Delay Model – cont.
• k-factor functions Delay/transition are functions of input signal
and gate load.
• Lookup table model Delay/transition is tabulated for each input,
load pair.
![Page 5: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/5.jpg)
Previous Gate Delay Model – cont.
• Switch-resistor model Structure:
• step voltage source
• linear driver resistance Advantages:
• Simple
• Stage delay
![Page 6: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/6.jpg)
Trends in DSM
• The increasing of resistive shielding of interconnect.
• The output impedance of gate reduces relatively.
![Page 7: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/7.jpg)
Trends in DSM – cont.
• Step input --> piecewise
• C_eff is needed in gate modeling.
![Page 8: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/8.jpg)
Our New Approach
• Gate modeling work independent of its load.
• Can be easily integrated into timing analysis.
• Concise circuit structure.
![Page 9: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/9.jpg)
Based on a second-order circuit.
Structure of Explicit Gate Model
![Page 10: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/10.jpg)
Parameters of Gate Model
• Totally 5 unknown parameters
4 unknown parameters in the model circuit.• R1 , R2, C1, C2
1 unknown parameters in the input signal.•
![Page 11: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/11.jpg)
• With two operating points, two poles are obtained.
Parameters of Gate Model – cont.
![Page 12: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/12.jpg)
• Another two operating points, another two poles.
Parameters of Gate Model – cont.
![Page 13: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/13.jpg)
Parameters of Gate Model – cont.
![Page 14: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/14.jpg)
Obtain Operating Points
There are four operating points of the gate output needed in the deduction.
- Run SPICE twice to obtain the two groups of (vi, ti).
- Obtained from k-factor functions
![Page 15: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/15.jpg)
• The gate intrinsic delay and signal regenerating ability.
is defined as tp tr .
Another Parameter
![Page 16: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/16.jpg)
Another Parameter – cont.
![Page 17: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/17.jpg)
• Choose an operating point of 50% power supply as (50%VDD, t50%).
Another Parameter – cont.
![Page 18: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/18.jpg)
Two Ways to Set up the Model
• Solving nonlinear equations.
• “optimize” function of transit analysis in HSPICE.
![Page 19: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/19.jpg)
Focus of the Experimental Results
• Can be pre-computed.
• The saving of runtime is obvious.
• The accuracy issue is focused on.
![Page 20: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/20.jpg)
• 36 gates of different types and technologies.
• The gate load is randomly generated.
• The input signal is also randomly chosen.• 3,600 experimental results all together.
• MOS transistor model level is from 13 to 49.
Experimental Results
![Page 21: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/21.jpg)
• Statistic results of computation errors in gate delay model.
Experimental Results– cont.
![Page 22: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/22.jpg)
Waveforms obtained from HSPICE simulations
Waveform Comparisons (Driving Pin)
![Page 23: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/23.jpg)
Waveforms obtained at the fan-out point.
Waveform Comparisons (Sink Pin)
![Page 24: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/24.jpg)
• The test results on the clock tree of a commercial IC .
Another Test Case
![Page 25: Explicit Gate Delay Model for Timing Evaluation Muzhou Shao : University of Texas at Austin D.F.Wong : U. of Illinois at Urbana- Champaign Huijing Cao](https://reader035.vdocuments.us/reader035/viewer/2022070306/5519b80b5503465b578b4886/html5/thumbnails/25.jpg)
Conclusion
• Independent of gate load.
• Can be pre-characterized.
• No effective capacitance iteration.
• Compatible with interconnect timing analysis.