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ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics
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Lecture Outline
! Review: Symmetric CMOS Inverter Design ! Inverter Power ! Dynamic Characteristics
" Delay
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3
Kenneth R. Laker, University of
Pennsylvania, updated 12Feb15
V th− VT0p
V th− VT0n
V th
V th V DD
-1
-1
V ILV IH
Vout = Vin - VT0p
Vout = Vin - VT0n
-VT0n
Review: CMOS Inverter: Visual VTC
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4
V th− VT0p
V th− VT0n
V th
V th V DD
-1
-1
V ILV IH
Vout = Vin - VT0p
Vout = Vin - VT0n
-VT0n
Review: CMOS Inverter: Visual VTC
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5
Kenneth R. Laker, University of
Pennsylvania, updated 12Feb15
If Vth is set to ideal case:
If, also
ideal Vth
k R symetric= 1
Important design Eq. for CMOS inverter VTC.
Review: CMOS Inverter: Design/Sizing
Vth =VT 0n +
1kR
VDD +VT 0 p( )
1+ 1kR
Vth =12VDD
kR =VDD +VT 0 p −VthVth −VT 0n
"
#$
%
&'
2
kR =VDD +VT 0 p −1 2VDD1 2VDD −VT 0n
"
#$
%
&'
2
=1 2VDD +VT 0 p1 2VDD −VT 0n
"
#$
%
&'
2
If VT0n= -VT0p= -VT0 (symmetric CMOS)
kR =VDD +VT 0 p −1 2VDD1 2VDD −VT 0n
"
#$
%
&'
2
=1 2VDD +VT 01 2VDD +VT 0
"
#$
%
&'
2
=1 1= µnWn
µpWp
⇒Wp
Wn
=µn
µp
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Review: Noise Margin Example
6
Kenneth R. Laker, University of
Pennsylvania, updated 12Feb15
Compute the noise margins for a symmetric CMOS inverter has been designed to achieve Vth = VDD/2, where VDD = 5 V and VT0n = - VT0p = 1 V.
NMH = NML = 2.5 V > VDD/2
RECALL (with VDD = 5 V) 1.
2.
1.
Ideal NM =>
1. NMH, NML > VDD/4 = 1.25 V
NMH = NML = 2.125
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Inverter Power
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Power
! P = I×V
! Tricky part: " Understanding I " (pairing with correct V)
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Static Current
! P = Istatic×VDD
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Switching Currents
! Dynamic current flow:
! If both transistor on: " Current path from Vdd
to Gnd " Short circuit current
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Currents Summary
! I changes over time ! At least two components
" Istatic – no switching " Iswitch – when switching
" Idyn and Isc
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Currents Summary
! I changes over time ! At least two components
" Istatic – no switching " Iswitch – when switching
" Idyn and Isc
12
VRAMP
CLK
φ
ramp_enable
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Switching
Dynamic Power
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Switching Currents
! Iswitch(t) = Isc(t) + Idyn(t)
! I(t) = Istatic(t)+Iswitch(t)
14
Isc
Istatic
Idyn
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Charging
! Idyn(t) " Ids = f(Vds,Vgs) " and Vgs, Vds changing
15
IDS =kn22 VGS −VT( )VDS −VDS2"# $%
IDS =kn2VGS −VT( )2
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Switching Energy – focus on Idyn(t)
16
Isc
Istatic
Idyn
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Switching Energy – focus on Idyn(t)
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
17
Idyn
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Switching Energy
18
! Do we know what this is?
Idyn
Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
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Switching Energy
19
! Do we know what this is?
Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
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Switching Energy
20
! Do we know what this is?
! What is Q? Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
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Switching Energy
21
! Do we know what this is?
! What is Q? Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
€
Q = CV = I(t)dt∫
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Switching Energy
22
! Do we know what this is?
! What is Q? Idyn
Q = Idyn (t)dt∫
E = P(t)dt∫= I(t)Vdd dt∫=Vdd I(t)dt∫
€
Q = CV = I(t)dt∫
€
E = CVdd2
Capacitor charging energy
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Switching Power
! Every time output switches 0#1 pay: " E = CV2
! Pdyn = (# 0#1 trans) × CV2 / time
! # 0#1 trans = ½ # of transitions
! Pdyn = (# trans) × ½CV2 / time
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Switching
24
Short Circuit Power
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Short Circuit Power
! Between VTN and Vdd - VTP
" Both N and P devices conducting
! Roughly:
25
Isc
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Peak Current
! Ipeak around Vdd/2 " If |VTN|=|VTP| and sized equal rise/fall
26
IDS =kn2VGS −VT( )2
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Peak Current
! Ipeak around Vdd/2 " If |VTN|=|VTP| and sized equal rise/fall
27
€
I(t)dt∫ ≈ Ipeak × tsc ×12%
& ' (
) *
IDS =kn2VGS −VT( )2
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Peak Current
! Ipeak around Vdd/2 " If |VTN|=|VTP| and sized equal rise/fall
28
€
I(t)dt∫ ≈ Ipeak × tsc ×12%
& ' (
) *
€
E =Vdd × Ipeak × tsc ×12#
$ % &
' (
IDS =kn2VGS −VT( )2
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Dynamic Characteristics
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Inverter Delay
! Caused by charging and discharging the capacitive load " What is the load?
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Inverter Delay
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Inverter Delay
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Inverter Delay
33
Cload = C#dbn + C#
dbp + C#gdn + C#
gdp + Cint + Cgb
Cgb = Cgbn+ Cgbp
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Inverter Delay
34
Cload ≈ C#dbn + C#
dbp + Cint + Cgb
Usually Cdb >> Cgd Csb >> Cgs
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35
Cload ≈ Cdbn + Cdbp + Cint + nCgb
n = fan-out ≥ 1
Inverter Delay
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Propogation Delay Definitions
36
VDD
0 t
VDD
0
V50% = VDD/2 Penn ESE 570 Spring 2016 – Khanna
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Propogation Delay Definitions
37
t
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Propogation Delay Definitions
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Rise/Fall Times
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MOS Inverter Dynamic Performance
! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays
! DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
40
METHODS: 1. Average Current Model
Assume Vin ideal
τ PHL ≈ CloadΔVHLIavg,HL
=CloadVOH −V50%Iavg,HL
τ PLH ≈ CloadΔVLHIavg,LH
=CloadV50% −VOLIavg,LH
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MOS Inverter Dynamic Performance
! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays
! DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
41
METHODS: 2. Differential Equation Model
Assume Vin ideal
iC =CloaddVoutdt
⇒ dt∫ =CloaddVoutiC
∫dt ≈ τ PHL or τ PLH
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MOS Inverter Dynamic Performance
! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and Cload, estimate (or measure) the propagation delays
! DESIGN: For given specs for the propagation delays and Cload*,
determine the MOS inverter schematic
42
METHODS: 3. 1st Order RC delay Model
Assume Vin ideal
τ PHL ≈ 0.69 ⋅Cload ⋅Rnτ PLH ≈ 0.69 ⋅Cload ⋅Rp
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Method 1
Average Current Model
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Calculation of Propagation Delays
44
τ PHL ≈ CloadΔVHLIavg,HL
=CloadVOH −V50%Iavg,HL
τ PLH ≈ CloadΔVLHIavg,LH
=CloadV50% −VOLIavg,LH
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Calculation of Propagation Delays
45
τ PHL ≈ CloadΔVHLIavg,HL
=CloadVOH −V50%Iavg,HL
τ PLH ≈ CloadΔVLHIavg,LH
=CloadV50% −VOLIavg,LH
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Calculation of Propagation Delays
46
τ PHL ≈ CloadΔVHLIavg,HL
=CloadVOH −V50%Iavg,HL
τ PLH ≈ CloadΔVLHIavg,LH
=CloadV50% −VOLIavg,LH
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Calculation of Rise/Fall Times
47
τ fall ≈ CloadΔV90%−10%Iavg,90%−10%
=CloadV90% −V10%Iavg,90%−10%
τ rise ≈ CloadΔV10%−90%Iavg,10%−90%
=CloadV90% −V10%Iavg,10%−90%
Penn ESE 570 Spring 2016 – Khanna
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Calculation of Rise/Fall Times
48 Penn ESE 570 Spring 2016 – Khanna
τ fall ≈ CloadΔV90%−10%Iavg,90%−10%
=CloadV90% −V10%Iavg,90%−10%
τ rise ≈ CloadΔV10%−90%Iavg,10%−90%
=CloadV90% −V10%Iavg,10%−90%
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Calculation of Rise/Fall Times
49 Penn ESE 570 Spring 2016 – Khanna
τ fall ≈ CloadΔV90%−10%Iavg,90%−10%
=CloadV90% −V10%Iavg,90%−10%
τ rise ≈ CloadΔV10%−90%Iavg,10%−90%
=CloadV90% −V10%Iavg,10%−90%
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Method 2
Differential Equation Model
Penn ESE 570 Spring 2016 – Khanna
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Calculating Propagation Delays
51
Two Cases 1. Vin abruptly rises => Vout falls => 2. Vin abruptly falls => Vout rises =>
Assume Vin is an ideal step-input
iDP - iDn
τ PHLτ PLH
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Case 1: Vin Abruptly Rises - τPHL
52 Penn ESE 570 Spring 2016 – Khanna
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Case 1: Vin Abruptly Rises - τPHL
53 Penn ESE 570 Spring 2016 – Khanna
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Case 1: Vin Abruptly Rises - τPHL
54
≈
≈
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Case 1: Vin Abruptly Rises - τPHL
55
≈
≈
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Case 1: Vin Abruptly Rises - τPHL
56
V out= V DD− V T0n
≈
≈
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57
V th− VT0p
V th− VT0n
V th
V th V DD
-1
-1
V ILV IH
Vout = Vin - VT0p
Vout = Vin - VT0n
-VT0n
Recall: CMOS Inverter: Visual VTC
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Case 1: Vin Abruptly Rises - τPHL
58
V out= V DD− V T0n
≈
CloaddVoutdt
≈ −iDn
dt =Cload−dVoutiDn
τ PHL = dtt=t0
t=t50%∫ =Cload−1iDn
$
%&
'
()
Vout=VDD
Vout=VDD /2∫ dVout
τ PHL =Cload−1iDn
$
%&
'
()
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
$
%&
'
()
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50% Penn ESE 570 Spring 2016 – Khanna
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Case 1: Vin Abruptly Rises - τPHL
59
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
saturation: iDn =kn2(Vin −VT 0n )
2
τ PHL,sat =Cload−1
kn2(VDD −VT 0n )
2
"
#
$$$
%
&
'''
VDD
VDD−VT 0n∫ dVout
τ PHL,sat =−Cload
kn2(VDD −VT 0n )
2dVoutVDD
VDD−VT 0n∫
τ PHL,sat =2CloadVT 0n
kn (VDD −VT 0n )2
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Case 1: Vin Abruptly Rises - τPHL
60
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
linear: iDn =kn2(Vin −VT 0n )Vout −V
2out( )
τ PHL,lin =Cload−1
kn22(VDD −VT 0n )Vout −V
2out( )
"
#
$$$
%
&
'''
VDD−VT 0n
VDD /2∫ dVout
τ PHL,lin =2Cload
kn
−12(VDD −VT 0n )Vout −V
2out( )
"
#$$
%
&''VDD−VT 0n
VDD /2∫ dVout
τ PHL,lin =2Cload
kn⋅
−12(VDD −VT 0n )
ln Vout2(VDD −VT 0n )−Vout( )
"
#$$
%
&''Vout=VDD−VT 0n
Vout=VDD /2
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Case 1: Vin Abruptly Rises - τPHL
61
τ PHL,lin =2Cload
kn⋅
−12(VDD −VT 0n )
ln Vout2(VDD −VT 0n )−Vout( )
#
$%%
&
'((Vout=VDD−VT 0n
Vout=VDD /2
τ PHL,lin =Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2#
$%
&
'(
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Case 1: Vin Abruptly Rises - τPHL
62
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
τ PHL,sat =2CloadVT 0n
kn (VDD −VT 0n )2
τ PHL = 2CloadVT 0n
kn (VDD −VT 0n )2 +Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL,lin =Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
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Case 1: Vin Abruptly Rises - τPHL
63
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
τ PHL,sat =2CloadVT 0n
kn (VDD −VT 0n )2 τ PHL,lin =
Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL = 2CloadVT 0n
kn (VDD −VT 0n )2 +Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
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Case 1: Vin Abruptly Rises - τPHL
64
V out= V DD− V T0n
τ PHL =Cload−1iDn
"
#$
%
&'
VDD
VDD−VT 0n∫ dVout +Cload−1iDn
"
#$
%
&'
VDD−VT 0n
VDD /2∫ dVout
t0#t1 t1#t50%
saturation linear
τ PHL,sat =2CloadVT 0n
kn (VDD −VT 0n )2
τ PHL = 2CloadVT 0n
kn (VDD −VT 0n )2 +Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL,lin =Cload
kn (VDD −VT 0n )ln 2(VDD −VT 0n )−VDD 2
VDD 2"
#$
%
&'
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Rn
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65
Recall from static CMOS Inverter:
(1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp DESIGN:
τ PHL =Cload ⋅1
kn (VDD −VT 0n )2VT 0n
(VDD −VT 0n )+ ln 2(VDD −VT 0n )
VDD 2−1
#
$%
&
'(
)
*+
,
-.
Vth =VT 0n +
1kR
VDD +VT 0 p( )
1+ 1kR
kR =VDD +VT 0 p −VthVth −VT 0n
"
#$
%
&'
2
Case 1: Vin Abruptly Rises - τPHL
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Idea
! Ptot = Pstatic + Pdyn+ Psc
" Can’t ignore Static Power (aka. Leakage power)
! Propogation Delay " Average Current Model " Differential Equation Model " 1st Order Model
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Admin
! HW 4 due Thursday, 2/18 " If you submit online and in-class only the online one will
be graded.
! Tania Office Hours on Wednesday 2-4pm
! Journal Thursday " Gregory Fredeman, et. al., A 14 nm 1.1 Mb Embedded
DRAM Macro With 1 ns Access, pp 230 - 239
67 Penn ESE 570 Spring 2016 – Khanna