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Politecnico di Torino - ICT School
Analog and Telecommunication Electronics
A1 – MOS and Bipolar transistor
» MOS structure and characteristic
» BJT structure and characteristic
» Large signal models
» Small signal model
AY 2015-16
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Lesson A1: MOS and BJT devices
• A refresh lesson!
• MOS and BJT structures and characteristic – Comparison of structure, parameters, models
– Emphasis on similarities
• Operating regions
• Large signal models
• Small signal model
• Difference MOS/BJT
– Some drawings from:» F. Fiori: Introduction to CMOS Analog Circuits.
» F. Bonani: High speed Electron Devices slides
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Structure of N- and P-MOS devices
• N-MOS
• P-MOS
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Symbols fom MOS devices
• Correspondence with BJT: SE; GB; DC
• Current flowing in arrow direction
• N-MOS: (npn BJT)
• P-MOS: (pnp BJT)
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Structure of NPN and PNP devices
• NPN(N-MOS)
• PNP(P-MOS)
– (real devices use mostly planar structures)
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Correspondence MOS/BJT devices
• SE; GB; DC
• Current can flow in arrow direction
• N-MOS npn BJT
• P-MOS: pnp BJT
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MOS output characteristics
• Operating regions– Triode Low VDS
– Saturation Const. Id(“active” region in BJT)
– (cutoff)
VGS
VDS
ID[mA]
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BJT output characteristic
• Operating regions
– Saturation Low VCE
– Active Constant Ic
– (cutoff)
IB
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Switch or amplifier?
• Use as amplifier
– BJT: Active regionMOS: Saturation
• Switch ON– BJT: Saturation
MOS: Resistive
• Switch OFF– Cutoff
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Operation in a circuit
• A LOAD LINEmodels the external circuit
• Operating points must be on load line AND on device I(V) LOAD
LINE
OPERATING POINT
Vcc
Vcc/Rc
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BJT input characteristic and model
• BE junction:– Emitter current (approx.)
– VBE ≈ 0.6 V
• Single model fitsall operating regions
• Strong temperature dependence
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MOS models
• Model depends on operating point
– Low Vgs(sub-threshold):
» Exponential
– Medium Vgs:» Square law
– High Vgs:» Linear
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MOS transcharacteristic
• No unique Id(Vgs) relation
– Weak inversion:exponential
– Strong inversion:quadratic
iD
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MOS Triode region
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MOS as variable resistor
• MOS with low VDS rDS = dVDS/dID depends on VGS
• BJT has fixed dVCE/dIC not good as variable resistor
MOS BJT
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Channel pinch-off
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MOS Channel lenght modulation
• Id depends on Vds
• Model in saturation region must include an equivalent output resistance rO
• Similar to Early effect in BJT
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BJT Early effect
• As VCE increases base region width decreases– In the active region, IC depends on VCE
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BJT Early voltage
• rO in small signal model
• Similar to channel lenghtmodulation in MOS
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MOS large signal model (saturation)
PowerMOS-FET
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BJT Ebers-Moll model
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MOS small-signal model
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MOS gm in triode and saturation regions
• Key parameter: W/L
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BJT small-signal model
• If VBE >> VT
• Linear approximantion(tangent) near an operating point (VBE0, IB0)
• Simplified models– Hibrid
– Transconductance
gm vBE
vBE
B C
E
IC
VBE
VBE0
IC0 VBE0, IB0
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BJT simplified models
1) Simplified model for bias point analysis (active area)
2) Simplified model for small signal analysis, CE configuration.Parameters:hfe iB or gm vBE
gm = IC/VT
hie = VT * hfe/IC
B C
E
IB IB
gm vBE
vBE
B C
E
hOE
hfe iB
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MOS simplified models
1) Bias point analysis with nonlinear model• Define the parameters to be used for small-signal analysis
• Use Id(Vgs) equation (order 2 or better model)
2) Simplified model for small signal analysis (similar to BJT), CS configuration.Parameters: gm , rD
gm = ….(II ord)
rD = dVDS/dID
gm vGS
vGS
B D
ES
G
rD
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MOS parasitic capacitances
• C3 CGS
• C4 CGD
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BJT Parasitic capacitances
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HF small signal models (π)
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Summary of MOS and BJT models
• Small signal– BJT, MOS, MOS-FET
– Same linear model (gm or hybrid)
• Large signal: same method, different models– BJT: exponential large signal model (rather simple)
– MOS: lin/exp/quadratic large signal model (complex !)
– Analytic model for BJT
– Analytic or heuristic models for MOS
– Similar effects and countermeasures» Distortion, harmonics, gain compression, …
» Feedback, tuned circuits, ….
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Operating limits: Safe Operating Area
Ohmic region (MOS: a low-value resistor)
Too high current
Too high V x I (power)
Toohigh voltage
Active & SafeOperatingArea (SOA)
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Evaluation of PDMAX
• Bipolar device:– PD = IC VCE; VCE = VCC – IC RC
– Max PD for d(PD)/dIC = 0 VCE = VCC/2
– PDMAX = …
• MOS device – same approach:– PD = ID VDS; VDS = VDE – ID RD
– Max PD for … VDS = VDD/2
– PDMAX = ….
• In both cases PD has parabolic shape– PD = 0 at cutoff (I = 0) and saturation (V ≈ 0)
– Max at the mid-point
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PD vs operating point
• PD has parabolic shape– PD = 0 at cutoff (I = 0)
and saturation (V ≈ 0)
– Max at the mid-point
• Critical parameters must be verified for PDMAX
– VCE = VCC – IC RC
– PDMAX = (ICmax /2) * (VCEmax /2);
• Same shape for MOS– Parameters ID, VDS
IC
PDMAX
PD
ICmax VCE
VCEmaxVCEmax/2
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:
Lesson A1 – final test
• Draw the static Id(Vds) characteristic of a MOS transistor. Compare with corresponding Ic(Vce) characteristic of BJT.
• Describe the difference between n-channel and p-channel devices.
• Describe a small signal model for MOS and BJT and related parameters.
• Which are the limits of small signal models?
• Draw small signal models for MOS and BJT with parasitic capacitances.
• Compare large signal models for MOS and BJT.
• Describe the difference between analytical and heuristic models.
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