EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 1
EE382V:Embedded System Design and Modeling
Andreas GerstlauerElectrical and Computer Engineering
University of Texas at [email protected]
Lecture 1 – Introduction
EE382V: Embedded Sys Dsgn and Modeling, Lecture 1 © 2014 A. Gerstlauer 2
Lecture 1: Outline
• Introduction• Embedded systems
• System-level design
• Course information• Topics
• Logistics
• Projects
• Design methodology• System-level design flow
• Models and methodologies
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 2
• System-in-a-system
• Application-specific
• Tightly constrained
• Ubiquitous
• Far bigger market than general-purpose computing (PCs, servers)
– 98% of all processors sold[Turley02, embedded.com]
• Exponentially growing complexities
• Application demands & technological advances
Increasingly networked and programmable
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Embedded Systems
EE382V: Embedded Sys Dsgn and Modeling, Lecture 1 © 2014 A. Gerstlauer 4
Cyber-Physical Systems (CPS)
• Not transformative
• Output = F(Input) Procedural/batch processing
• But reactive
• Continuous interaction with environment Sense and act on the physical world
Concurrency and time (order)
TransformativeSystem
Input Output
ReactiveSystem
Inputs Outputs
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Lecture 1
(c) 2014 A. Gerstlauer 3
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General-Purpose Computing
• We are reaching physical limits of technology scaling
• Dark silicon: power/utilization/… walls
• Mobile devices and no leap in battery technology
Efficiency is the new performance
Opportunity and need for specialization
Heterogeneous multi-core /Asynchronous CMP Big/little architectures
GP-GPUs
Flexibility vs. specialization Right mix of cores?
How to “program”?
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Source: T. Noll, RWTH Aachen, via R. Leupers, “From ASIP to MPSoC”, Computer Engineering Colloquium, TU Delft, 2006
Implementation Options
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 4
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Multi-Processor System-on-Chip (MPSoC)
Frontside Bus
SystemMemory
Local Bus
Local RAM
Bridge
SharedRAM
DSP Bus
DSP RAM
MemoryController GPU
DSP
HardwareAccelerator
CPU
HardwareAccelerator
VideoFront End
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Design Challenges
Applications
ProgrammingModel?
• Reactivity
• Concurrency & time
• Safety, reliability, robustness
• Heterogeneity
• Of components– Processors, memories, busses
• Of design tasks– Architecture, mapping, scheduling
Complexity
• High degree of parallelism
• High degree of design freedom
• Multiple optimization objectives& design constraints
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 5
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Complexity Trends
Capability of Technology2x/18 Months
Gates/ChipGates/Day
SoftwareProductivity2x/5 years
log
time
1981
1985
1989
1993
1997
2001
2005
2009
LoC SW/Chip
Average HW + SW Design Productivity
LoC/Day
Additional SW required for HW2x all 10 months
SystemDesign Gap
HW DesignGap
HW DesignProductivity1.6x/18 Months
Source: W. Ecker, W. Müller, R. Dömer, Hardware-dependent Software - Principles and Practice, Springer 2009.
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System levelSystem level
Abstraction Levels
• Move to higher levels of abstraction [ITRS07, itrs.net]
Electronic system-level (ESL) design
1E0
1E1
1E2
1E3
1E4
1E5
1E6
1E7
Number of componentsLevel
Gate
RTL
Algorithm
Transistor
Ab
stra
ctio
n
Acc
ura
cy
Source: R. Doemer, UC Irvine
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 6
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System-Level Design
• From specification• Functionality, behavior
– Concurrency, order– Constraints
• To implementation• Architecture
– Spatial and temporal order– Components and connectivity
Design automation• Modeling • Exploration• Synthesis
Proc
Proc
Proc
Proc
Proc
Requirements, constraints
Implementation (HW/SW synthesis)
Mapping & exploration
DCT
TX
ARM
M1Ctrl
I/O4
HW
DSP
MBUS
BUS1 (AHB) BUS2 (DSP)
Arb
iter
1
IP Bridge
DCTBus
I/O3I/O2I/O1
DMA
M1
Enc DecJpeg
Codebk
stripe
SI BO BI SO
DCT
MP3
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System-On-Chip Environment (SCE)
ArchnArchnTLMn
Impln
Spec
ImplnImpln
Synthesize target HW/SW
Compile onto platform
Commercial derivative for Japanese Aerospace Exploration Agency
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Lecture 1
(c) 2014 A. Gerstlauer 7
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Bri
dg
e
CPU Mem
HW IP
Arb
ite
r
v1
C1
B1 B2
B3 B4
C2
CommunicationComputation &
System-LevelDesign
Software / HardwareSynthesis
Co
mp
ilati
on
Hig
h-L
evel Syn
thesis
Software Object Code
Hardware VHDL/Verilog
Functionality
System-Level Models
Architecture
UT ECE Courses
EE382V: Embedded System Design & Modeling
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Lecture 1: Outline
Introduction Embedded systems
System-level design
• Course information• Topics
• Logistics
• Projects
• Design methodology• System-level design flow
• Models and methodologies
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 8
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Course Topics
• System-level design• Methodologies and languages: SpecC, SystemC
• Specification modeling• Formal Models of Computation (MoC)
– Parallel programming models, threads, dataflow, process networks– Hierarchical and concurrent finite state machine (FSM) models
• System synthesis• Design space exploration and optimization
– Mapping and scheduling algorithms, exploration heuristics– System-level design tools: SCE
• Architecture modeling• Implementation and simulation (virtual prototyping) models
– Host-compiled OS and processor models for computation– Transaction-level modeling of communication
Prerequisites Software: C/C++ (algorithms and data structures) Hardware: VHDL/Verilog (digital design) Embedded systems and embedded software
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Class Administration
• Schedule• Lectures: TTh 11:00am-12:30pm, WEL 3.402
• Instructor• Prof. Andreas Gerstlauer <[email protected]>
– Office hours: ACE 6.118, TW 2-3pm, or after class/by appt.
• Teaching Assistant• Parisa Razaghi <[email protected]>
– Office hours: MF 3-4pm, ENS 110
• Information• Web page: http://www.ece.utexas.edu/~gerstl/ee382v_s14• Announcements, assignments, grades: Blackboard• Questions, discussions: Blackboard
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 9
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Textbooks (1)
• Recommended
• D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Springer, 2009 (“orange book”)
• Optional
• E. A Lee, S. Seshia, Introduction to Embedded Systems: A Cyber-Physical Systems Approach, 2011
– Models of computation (MoCs)
– http://leeseshia.org
This image cannot currently be displayed.
This image cannot currently be displayed.
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Textbooks (2)
• Background material
• A. Gerstlauer, R. Doemer, J. Peng, D. Gajski, System Design: A Practical Guide with SpecC, Kluwer, 2001 (“yellow book”)
– Practical, example-driven introduction using SpecC
– Electronic copy of selected chapters on Blackboard
• T. Groetker, S. Liao, G. Martin, S. Swan,System Design with SystemC, Kluwer, 2002 (“black book")
– Reference for SystemC language and methodology
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
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Policies
• Grading• Homeworks: 20%• Labs: 20% • Midterm: 25% • Project: 35% No late submissions!
• Academic dishonesty• Homeworks are independent
– Discuss questions and problems with others– Turn in own, independently developed solution
• Labs and project are teamwork– Teams of up to 3 students– One report and presentation
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Homeworks and Labs
• Two to three homeworks and one exam
• Cover theoretical aspects of system design– Languages
– Models
– Exploration and optimization
• Some practical implementation– Exposure to general language and modeling concepts
• Two to three labs
• Real-world system design– Design example using SpecC and System-on-Chip Environment (SCE)
• From specification to implementation– Modeling
– Design space exploration
– Hardware/software synthesis
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Lecture 1
(c) 2014 A. Gerstlauer 11
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Project
• Two options
• Research project– System design research problem
– Literature survey on system design research area
• Implementation project– Non-trivial system design example/case study
– Specification, exploration, implementation
• Project timeline (tentative)
• Abstract: March 4 (email)
• Proposal, literature survey: March 18
• Presentations: last week of classes (Apr. 29 & May 1)
• Report: finals week (May 8)
Final report and presentation in publishable quality
EE382V: Embedded Sys Dsgn and Modeling, Lecture 1 © 2014 A. Gerstlauer 22
Some Possible Projects• Design projects
• (Embedded) system design example– Specify, model, simulate, explore, synthesize using SCE
» Existing examples: MP3 Decoder, AC3 Decoder, Jpeg Encoder, GSM Vocoder» Backend synthesis down to ARM+FPGA prototyping board
• Research projects• Modeling
– Specification modeling» Develop/modify a language or MoC: data parallel extensions of SpecC/SystemC» Translation between MoCs & languages: from Matlab/SDF/… to SpecC/SystemC
– Architecture modeling» Component modeling: QEMU-SpecC/SystemC integration, bus modeling» Automatic model generation: generate bus TLMs from abstract protocol descriptions» OS modeling: OS-internal timing estimation and back-annotation» Performance estimation and modeling (timing, power, reliability, …): statistical simulation,
parallel or hardware/software co-simulation of functional & performance models» Assertion-based verification in a TLM environment
• Synthesis– Pick an implementation problem and solve it
» Decision making: machine learning for optimization (allocation, partitioning, scheduling), design space exploration for dataflow models/signal processing systems
» OS scheduling for power, performance, reliability» Hardware or software synthesis for new OS/processors: targeting Linux in SCE
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 12
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Successful Past Projects
• Modeling
• A. Abdel-Hadi, J. Michel, "Real-Time Optimization of Video Transmission in a Network of AAVs," VTC 2011.
• A. Pedram, C. Craven, T. Amimeur, “Modeling Cache Effects at the Transaction Level,” IESS 2009 (best paper runner-up)
• A. Banerjee, “Transaction Level Modeling of Best Effort Channels for Networked Embedded Devices”, IESS 2009.
• Exploration and synthesis
• J. Lin, A. Srivatsa, “Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems,” ICASSP 2011.
• S. Lee, K. Saleem, J. Li, "Fine Grain Word Length Optimization for Dynamic Precision Scaling in DSP Systems," VLSI-SoC 2013 (best paper candidate)
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Lecture 1: Outline
Introduction Embedded systems
System-level design
Course information Topics
Logistics
Projects
• Design methodology• System-level design flow
• Models and methodologies
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Lecture 1
(c) 2014 A. Gerstlauer 13
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Evolution of Design Flows
Specs
Algorithms
Capture & Simulate
Specs
Algorithms
Describe & Synthesize
Executable Spec
Algorithms
Specify, Explore & Refine
Architecture
Network
SW/HW
Logic
Physical
SW? SW?
Design
Logic
Physical
Design
Logic
Physical
Manufacturing Manufacturing Manufacturing
1960's 1980's 2000's
Functionality
Simulate Simulate
Describe
Algorithms
Connectivity
Protocols
Performance
Timing
System Gap
Source: D. Gajski, UC Irvine
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system design
hardwaredevelopment
softwaredevelopment
integration & verification
Classical System Design Flow
(semi)automaticmanual
System requirement specification
System architecture design
Modeling
Hardware design
Software development
System
Integration & Verification
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 14
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Classical Design Cycle
Time
Task
Specification Fixes in specification
HW design Fixes in hardware
HW verification
SW design Fixes in software
SW verification
Integration & verification
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system design
hardwaredevelopment
softwaredevelopment
integration & verification
Electronic System-Level (ESL) Design Flow
(semi)automaticmanual
System requirement specification
High-level model
Hardware design Software development
System implementation
Integration & Verification
System-level design
Architecture model
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Lecture 1
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New ESL Design Cycle
Time
Task
Specification(high-level & arch. models) Fixes in specification
HW design Fixes in hardware
HW verification
SW design Fixes in software
SW verification
Integration & verification
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Design Methodology
Formalization of a design flow
• Break into well-defined, repeatable steps– Set of models and transformations between them
– Manual or automated
• Models
• Design representations– Specification and documentation at interface between steps
• Transformations
• Design decisions– Refine input model into an output model reflecting decisions
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Lecture 1
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Y-Chart
Behavior(Function)
Structure (Netlist)
Physical (Layout)
Logic
Circuit
Processor
System
RTL
Gates
Transistors
PE,Bus
Specification
Algorithm
Boolean logic
Transfer
(a v b)
Mod
els
of C
ompu
tatio
n (M
oCs) M
odels of Structure (M
oSs)
Source: D. Gajski, UC Irvine
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Processor Synthesis
Algorithm model (program) Microarchitecture model (RTL)
B1
B2
ALU Memory
RF / Scratch pad
MUL
B3
AG
PC
CW
Sta
tus
...const
offset
status
address
CMemIF
IF
BB1
BB2 BB3
Y
YN
N
• Software processor• Compilation and linking
• Hardware processor• High-level synthesis
Source: D. Gajski, UC Irvine
EE382V: Embedded Sys Dsgn and Modeling
Lecture 1
(c) 2014 A. Gerstlauer 17
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System Synthesis
• Structure• Partitioning, mapping
• Timing• Scheduling
C1
P5
P3
P4
dP1
P2
d
C2
Bri
dg
e
P1 P3
CPU Mem
HW IP
P5
C1, C2
Arb
iter
P4P2
C1, C2CPU Bus IP Bus
Source: D. Gajski, UC Irvine
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Bottom-Up Methodology
• Each level generates library for the next higher level
• Circuit: Standard cells for logic level
• Logic: RTL components for processor level
• Processor: Processing and communication components for system level
• System: System platforms for different applications
• Floorplanning and layout on each level
Behavior(Function)
Structure(Netlist)
Physical(Layout)
Logic
Circuit
Processor
System
Start
RTL
Gates
Transistors
PE,Bus
Source: D. Gajski, UC Irvine
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Lecture 1
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Top-down Methodology
• Functional description is converted into component netlist on each level
• Each component function is decomposed further on the next abstraction level
• Layout is given only for transistor components
Source: D. Gajski, UC Irvine
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Meet-in-the-Middle Methodology
• Gate netlist is hand-off• Three levels of synthesis
• System is synthesized with processor components
• Processor components are synthesized with RTL library
• RTL components are synthesized with standard cells
• Two levels of layout• System layout is performed
with standard cells• Standard cells layout with
transistors
Source: D. Gajski, UC Irvine
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Lecture 1
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Platform-Based Design
• Meet-in-the-middle at the system level
• System platform with standard components
• System design reduced to mapping of specification onto pre-defined platform
Behavior(Function)
Structure(Netlist)
Physical(Layout)
Logic
Circuit
Processor
System
Start
RTL
Gates
Transistors
Platform
Source: D. Gajski, UC Irvine
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Lecture 1: Summary
Introduction Embedded systems
System-level design
Course information Topics
Logistics
Projects
Design methodology System-level design flow
Models and methodologies