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EE 501 Analog IC Design• Instructor Contact Information
– Name: Degang Chen– Office: 2134 Coover Hall– Email: [email protected]– Phone: 294-6277– Office Hour: MWF 12:00 – 2:00 pm
Or any other time convenient to you
– Please include "EE501" in the subject line in all email communications to avoid auto-deleting or junk-filtering
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EE 501 Analog IC Design• TA Contact Information
– Main TA:• Name: Tao Zeng• Office: 2135 Coover Hall• Phone: 515-708-3389• Email: [email protected],
– Helping TA:• Name: Jingbo Duan• Office: 2135 Coover Hall• Phone: 515-203-1784• Email: [email protected],
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EE 501 Analog IC Design• Student Introduction
– Contact information• For me to contact you
– Brief intro• Name
• Advisor
• Area
• Interest
• IC design experience
• Cadence experience
– Study / lab partners
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Class Webpage• http://class.ece.iastate.edu/djchen/ee501/2008
• Please check the page for– Any announcement– Class notes– HW assignments– Lab assignments– Project requirements– Class policy and other info
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Student behavior expectations• Full attendance except with prior-notified
excuses• On-time arrival• Active participation
– Ask questions– Answer questions from instructor or students
• Be cordial and considerate to other students and TA
• Help each other• Promptly report/share problems/issues
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Prohibited behaviors
• Any foul language or gesture
• Comments to other students that are discriminatory in any form
• Any harassments as defined by the university
• Academic dishonesty
• No alcohol, drugs, or any other illegal / improper substances
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Accommodation/Assistance• Please let me know if you
– Have any special needs– Have disability in any form– Have any medical/mental/emergency conditions– Have field trips / interviews– Have special requests– Want me to adjust lecture contents/pace
• Can also consult me if you – Would like to seek advice on any professional or
personal issues– Would like to have certain confidential discussions
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Course Description • Design techniques for analog and mixed-signal
VLSI circuits. • Amplifiers: operational amplifiers,
transconductance amplifiers, finite gain amplifiers and current amplifiers.
• Linear building block: differential amplifiers, current mirrors, references, cascoding and buffering.
• Performance characterization of linear integrated circuits: offset, noise, sensitivity and stability.
• Layout considerations, simulation, yield and modeling for high-performance linear integrated circuits.
• CAD tools: Cadence.
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Final Grade Weighting • Laboratory: 25%• Design projects: 15% each• Homework: 15%• Midterm Exam: 10%• Final exam: 15%• Classroom participation: 5%
• Bonus for original creative work (publishable/patentable work)
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Fabrication Privilege• Circuit fabrication is not required for the course• It is offered free as a privilege• Requirements for this privilege
– Detailed simulation results demonstrating that circuit is highly likely to work
– Sufficient testing plan (what to measure and how)– Promise to test (availability and commitment of time)– Register in ee599CD and submit a report to MOSIS
• Benefits:– Valuable experience– Increased marketability– Get one credit for fabrication and testing
• Limits: max two submissions per student
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Two Alternative Ways to Get A
• Successful design of both projects– Both show A-level performance in schematic
and post layout simulation, as well as well-thought-out layout
– At least one project successfully fabricated and satisfactorily tested
• Nontrivial originally contribution– Accepted technical paper to a decent
conference and/or journal– Paper deemed at similar level by Instructor
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Text Book
• Allen and Holberg, CMOS Analog Circuit Design, 2nd Edition, Oxford, 2002
• Hastings, The Art of Analog Layout, Prentice Hall, 2nd ed
• Available at Amazon– Significant discounts vs bookstore– Links in a previous email
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References• Gray, et al, Analysis and Design of Analog Integrated Circuits, 4th Ed.,
Wiley, 2001• William Liu, Mosfet Models for Spice Simulation, Including BSIM3v3 and
BSIM4, Wiley-IEEE, 2001• Daniel P. Foty, MOSFET Modeling With SPICE: Principles and Practice,
Prentice Hall, 1996• Yannis Tsividis, Operation and Modeling of the MOS Transistor, Oxford
University Press; 2nd edition (May 1, 2003) • Laker and Sansen, Design of Analog Integrated Circuits, McGraw Hill, 1994• David Johns & Ken Martin , Analog Integrated Circuit Design, John Wiley &
Sons, Inc. 1997• Behzad Razavi, Design of Analog CMOS Integrated, CircuitsMcGraw-Hill,
1999 • Geiger, et al, VLSI Design Techniques for Analog and Digital Circuit,
McGraw Hill, 1990
• Baker, CMOS Circuit Design, Layout and Simulation, IEEE Press, 1997• Alan B. Grebene, Bipolar and MOS Analog Integrated Circuit Design (Wiley
Classics Library), 2001
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Lab 0VDD
Vin-
Vo
Vin+
CL
M1 M2
M3 M4
M5M0
M1,2: 15/1.5M3,4: 45/1.5M5: 30/1.5M0: 3/1.5CL: 5 pFIB: 10 uA
IB
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MOSIS links
• MOSIS web site
• FAQ from comp.lsi.cad
• MOSIS scalable design rules
• MOSIS Pads directory.
• Process description: TSMC 0.25, AMI 0.5
• SPICE model parameters: TSMC 0.25, AMI 0.5
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Links for information sources
• IEEE IEL
• Science Citation Index / ISI Web of Knowledge
• U.S. Patent Office
• International Technology Roadmap for Semiconductors
• Semiconductor Research Corporation
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Links for technical writing
• Things to think about while writing papers
• A nuts and bolts guide to college writing
• The Barleby refence site
• William Shrunk's "Elements of Style"
• Dictionary.com
• Visual Thesaurus
• Latex style files for IEEE journals
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“E source” “G source”
“H source”“F source”
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Polycrystalline
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Furnaces
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Ingot
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Slicing
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Lapping
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Polishing
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CloserViewOfPolishing
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125 - 300
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BASIC FABRTICATION PROCESSES
• Oxide growth
• Thermal diffusion
• Ion implantation
• Deposition
• Etching
• Photolithography
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Oxidation• The process of growing a layer of silicon
dioxide (SiO2)on the surface of a silicon wafer.
• Uses:Provide isolation between two layersProtect underlying material from contaminationVery thin oxides (100 to 1000 Å) are grown using
dry-oxidation techniques. Thicker oxides (>1000 Å) are grown using wet
oxidation techniques.
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(Thickness of SiO2 grossly exaggerated.)
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DiffusionMovement of impurity atoms at the surface of the
silicon into the bulk of the silicon
- From higher concentration to lower concentration.
- Done at high temperatures: 800 to 1400 C.
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Infinite-source diffusion
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Finite-source diffusion
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Ion ImplantationThe process by which impurity ions
are accelerated to a high velocity and physically lodged into the target.
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• Require anneal to repair damage
• Can implant through surface layers
• Can achieve unique doping profile
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Deposition• Chemical-vapor deposition (CVD)• Low-pressure chemical-vapor
deposition• Plasma-assisted chemical-vapor
deposition• Sputter deposition
• Materials deposited– Silicon nitride (Si3N4)– Silicon dioxide (SiO2)– Aluminum– Polysilicon
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Etching• To selectively remove a layer of material• But may remove portions or all of
– The desired material– The underlying layer– The masking layer
• Two basic types of etches:– Wet etch, uses chemicals– Dry etch, uses chemically active ionized
gasses.
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Wet Etching
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• Selectivity:
• Anisotropy:
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Photolithography
• Components– Photoresist material– Photomask– Material to be patterned (e.g., SiO2)
• Positive photoresist-– Areas exposed to UV light are soluble in the
developer
• Negative photoresist-– Areas not exposed to UV light are soluble in the
developer
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Steps:
1. Apply photoresist
2. Soft bake
3. Expose the photoresist to UV light through photomask
4. Develop (remove unwanted photoresist)
5. Hard bake
6. Etch the exposed layer
7. Remove photoresist
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Expose:
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After Developing
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After Etching
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After Removing Photoresist