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ECE680: Physical VLSI DesignECE680: Physical VLSI DesignECE680: Physical VLSI DesignECE680: Physical VLSI Design
Chapter Chapter VV
Implementation Strategies forImplementation Strategies forDigital ICsDigital ICsDigital ICsDigital ICs
(Ch t(Ch t 8 i T tb k)8 i T tb k)(Chapter (Chapter 8 in Textbook)8 in Textbook)
110/(02 ‐ 09)/2008 GMU, ECE 680 Physical VLSI Design
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The Design Productivity Challenge(K
)
nth)
1 000 000
10,000,000
10 000 000
100,000,000
10m T i t /St ff M th
Logic Transistors/Chip
58%/Yr. compoundComplexity growth rate
s pe
r Chi
p (
s./S
taff-
Mon
10 000
100,000
1,000,000
100 000
1,000,000
10,000,000
35m
.10m Transistor/Staff Month
Tran
sist
ors
tivity
(Tra
ns
100
1,000
10,000
X XX
1,000
10,000
100,000.35m
21%/Yr. compoundProductivity growth rate
10Logi
c T
Pro
duct
1
X XX X
Xx100
10
2.5m
A growing gap between design complexity and design productivity
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
Source: sematech97
10/(02 ‐ 09)/2008 2GMU, ECE 680 Physical VLSI Design
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A Simple Processorp
MEMORY
T
CONTROL
UT/OUTPUT
DATAPATHINPUT-OUTPUT
INPU
10/(02 ‐ 09)/2008 3GMU, ECE 680 Physical VLSI Design
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A System‐on‐a‐Chip: Example
Courtesy: Philips
10/(02 ‐ 09)/2008 4GMU, ECE 680 Physical VLSI Design
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Impact of Implementation Choices
100‐1000
ocessor
PS/m
W) 10‐100
ain‐specific pro
DSP)
rocessor
cien
cy (in MOP
1‐10
red custom
eterizable Dom
a(e.g. D
edde
d micropr
Energy Effic
0.1‐1
Hardw
ir
urable/Param
e
Embe
FlexibilityNone FullySomewhat
Configu
(or application scope)flexibleflexible
10/(02 ‐ 09)/2008 5GMU, ECE 680 Physical VLSI Design
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Design Methodology
• Design process traverses iteratively between three abstractions:behavior structure and geometrybehavior, structure, and geometry• More and more automation for each of these steps
10/(02 ‐ 09)/2008 6GMU, ECE 680 Physical VLSI Design
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Implementation ChoicesImplementation Choices
Digital Circuit Implementation Approaches
Custom
Cell‐based Array‐based
Semicustom
Standard CellsCompiled Cells Macro Cells
Cell based
Pre‐diffused(Gate Arrays)
Pre‐wired(FPGA's)
Array based
Compiled Cells (Gate Arrays) (FPGA's)
10/(02 ‐ 09)/2008 7GMU, ECE 680 Physical VLSI Design
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The Custom Approach
Intel 4004
Courtesy Intel10/(02 ‐ 09)/2008 8GMU, ECE 680 Physical VLSI Design
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Transition to Automation and Regular Structures
Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085
Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel10/(02 ‐ 09)/2008 9GMU, ECE 680 Physical VLSI Design
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Cell‐based Design (or standard cells)
Logic cellFeedthrough cell
Routingchannel
s of
cel
ls
Routing channel requirements arereduced by presence
Functionalmodule(RAM
Row
s
of more interconnectlayers
(RAM,multiplier, …)
10/(02 ‐ 09)/2008 10GMU, ECE 680 Physical VLSI Design
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Standard Cell — Example
[Brodersen92]
10/(02 ‐ 09)/2008 11GMU, ECE 680 Physical VLSI Design
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Standard Cell – The New Generation
Cell‐structurehidden underinterconnect layers
10/(02 ‐ 09)/2008 12GMU, ECE 680 Physical VLSI Design
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Standard Cell ‐ Example
3‐input NAND cell(from ST Microelectronics):(from ST Microelectronics):C = Load capacitanceT = input rise/fall time
10/(02 ‐ 09)/2008 13GMU, ECE 680 Physical VLSI Design
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Automatic Cell Generation
Initial transistorgeometries
Placedtransistors
Routedcell
Compactedcell
Finishedcell
Courtesy Acadabra10/(02 ‐ 09)/2008 14GMU, ECE 680 Physical VLSI Design
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A Historical Perspective: the PLA
Product terms
ANDplane
x0x1
x2 ORplaneplane plane
f0 f1
x0 x1 x2
0 1
10/(02 ‐ 09)/2008 15GMU, ECE 680 Physical VLSI Design
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Two‐Level LogicgEvery logic function can beexpressed in sum‐of‐productsexpressed in sum of productsformat (AND‐OR)
minterm
Inverting format (NOR‐NOR) more effective
10/(02 ‐ 09)/2008 16GMU, ECE 680 Physical VLSI Design
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PLA Layout – Exploiting Regularity
VDD GNDφAnd‐Plane Or‐Plane
f0 f1x0 x0 x1 x1 x2 x2Pull-up devices Pull-up devices
10/(02 ‐ 09)/2008 17GMU, ECE 680 Physical VLSI Design
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Breathing Some New Life in PLAsRiver PLAs• A cascade of multiple‐output PLAs.• Adjacent PLAs are connected via river routing.
E-C
HA
RG
E
BU
FFER
PRE-CHARGE
PRE
BUFFER
B
PRE-CHARGE
PRE-
CH
AR
GE
BUFFERB
UFF
ER
PRE-CHARGE
PRE-
CH
AR
GE
BUFFER
BU
FFER
PRE CHARGEBUFFER
PRE-CHARGE
PRE-
CH
AR
GE
BUFFER
BU
FFER • No placement and routing needed.
• Output buffers and the input buffers of the next stage are sharedthe next stage are shared.
Courtesy B. Brayton10/(02 ‐ 09)/2008 18GMU, ECE 680 Physical VLSI Design
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Experimental Results1.4
dela
y
Area:
1
Area: RPLAs (2 layers) 1.23 SCs (3 layers) ‐ 1.00, NPLAs (4 layers) 1.31 DelayRPLAs 1.04
0.6SCs 1.00 NPLAs 1.09 Synthesis time: for RPLA , synthesis time equals design time; SCs and NPLAs still need P&R.
Also: RPLAs are regular and predictable
Layout of C2670
0.20 2 4 6 area
SC NPLA RPLA
g p
Network of PLAs, 4 layers OTC
River PLA,2 layers no additional routing
Standard cell, 2 layers channel routing
Standard cell,3 layers OTC
10/(02 ‐ 09)/2008 19GMU, ECE 680 Physical VLSI Design
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MacroModules
256×32 (or 8192 bit) SRAMGenerated by hard‐macro module generator
10/(02 ‐ 09)/2008 20GMU, ECE 680 Physical VLSI Design
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“Soft” MacroModulesSoft MacroModules
Synopsys DesignCompiler
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“Intellectual Property”p y
A Protocol Processor for Wireless
10/(02 ‐ 09)/2008 22GMU, ECE 680 Physical VLSI Design
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Semicustom Design FlowBehavioralBehavioralDesign Capture
HDLHDL
Logic SynthesisLogic Synthesis
Pre‐Layout SimulationPre‐Layout Simulation StructuralStructural
tion
tion
g yg y
FloorplanningFloorplanning
Design Itera
Design Itera
PlacementPlacement
Post‐Layout SimulationPost‐Layout Simulation
PhysicalPhysical
DD
RoutingRouting
Tape out
Circuit ExtractionCircuit Extraction
Tape‐out
10/(02 ‐ 09)/2008 23GMU, ECE 680 Physical VLSI Design
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The “Design Closure” Problemg
Iterative Removal of Timing Violations (white lines)
Courtesy Synopsys
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Integrating Synthesis with Physical Design
RTL (Timing) Constraints
Physical SynthesisPhysical Synthesis
RTL (Timing) Constraints
Physical SynthesisPhysical Synthesis
Netlist withMacromodules Netlist with Place‐and‐Route Info
MacromodulesFixed netlists
Place‐and‐RouteOptimization
Place‐and‐RouteOptimization
Artwork10/(02 ‐ 09)/2008 25GMU, ECE 680 Physical VLSI Design
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Late‐Binding Implementationg p
Array‐based
Pre‐diffused(Gate Arrays)
Pre‐wired(FPGA's)
10/(02 ‐ 09)/2008 26GMU, ECE 680 Physical VLSI Design
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Gate Array — Sea‐of‐gatesy g
rows of
VDD
polysilicon
metalUncommitedrows of
cellsuncommitted
GND possiblecontact
UncommitedCell
routing channel
In1 In2 In3 In4
C itt dchannel
O t
CommittedCell(4‐input NOR)
Out
10/(02 ‐ 09)/2008 27GMU, ECE 680 Physical VLSI Design
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Sea‐of‐gate Primitive Cells
Oxide-isolation
PMOS
PMOS
PMOS
NMOS
NMOSNMOS
Using oxide‐isolation Using gate‐isolation
10/(02 ‐ 09)/2008 28GMU, ECE 680 Physical VLSI Design
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Example: Base Cell of Gate‐Isolated GA
4321VDD
87654
continuousp-diff strip
n-well131211109
llcontinuous
1716151413
m1polyp-diffn-diffp-well
t t f
continuousn-diff strip
contact
21GND201918 m2
m1contact forisolator
From Smith9710/(02 ‐ 09)/2008 29GMU, ECE 680 Physical VLSI Design
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Example: Flip‐Flop in Gate‐Isolated GA
VDD
Q
CLR
CLKQ
D
GND
From Smith9710/(02 ‐ 09)/2008 30GMU, ECE 680 Physical VLSI Design
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Sea‐of‐gates
Random Logic
MemorySubsystem
LSI Logic LEA300K(0.6 μm CMOS)μ
Courtesy LSI Logic10/(02 ‐ 09)/2008 31GMU, ECE 680 Physical VLSI Design
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The return of gate arrays?Via programmable gate array
(VPGA)
blVia‐programmable cross‐point
metal‐5 metal‐6
programmable via
E l it l it f i t t
[Pileggi02]
Exploits regularity of interconnect
10/(02 ‐ 09)/2008 32GMU, ECE 680 Physical VLSI Design
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Prewired ArraysClassification of prewired arrays (or field‐programmable devices):• Based on Programming Technique
– Fuse‐based (program‐once)– Non‐volatile EPROM based
RAM b d– RAM based• Programmable Logic Style
– Array‐Based– Look‐up Table
• Programmable Interconnect Style– Channel‐routing– Mesh networks
10/(02 ‐ 09)/2008 33GMU, ECE 680 Physical VLSI Design
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Fuse‐Based FPGAFuse Based FPGA
antifuse polysilicon ONO dielectric
n+ antifuse diffusion
2 l2 l
Open by default, closed by applying current pulse
From Smith9710/(02 ‐ 09)/2008 34GMU, ECE 680 Physical VLSI Design
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Array‐Based Programmable Logic
I5 I 4 I 3 I 2 I 1 I 0 ProgrammableOR array I 5 I 4 I 3 I 2 I 1 I 0 Fi d OR
I 3 I 2 I 1 I 0 ProgrammableOR
y I 5 I 4 I 3 I 2 I 1 I 0 Fixed OR arrayOR array
Programmable AND array P bl ANDFixed AND array
PLA PROM PAL
O 0O 1O 2O 3
g y
O 0O 1O 2O 3
Programmable AND arrayO0O1O2O3
Fixed AND array
Indicates programmable connection
Indicates fixed connection
10/(02 ‐ 09)/2008 35GMU, ECE 680 Physical VLSI Design
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Programming a PROM1 X 2 X 1 X 0
f0f1NANA
: programmed node
01
10/(02 ‐ 09)/2008 36GMU, ECE 680 Physical VLSI Design
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More Complex PALpprogrammable AND array (2 i 3 jk ) k macrocells
j -wide OR array
productterms1
jD Q
OUT
macrocellj
CLKA B C i i inputs
i inputs, j minterms/macrocell, k macrocells
From Smith9710/(02 ‐ 09)/2008 37GMU, ECE 680 Physical VLSI Design
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2‐input mux bl l i bl kas programmable logic block
Configuration
A B S F=
0 0 0 0
FA 0
B 1
0 X 1 X0 Y 1 Y0 Y X XYX 0 Y XYB
S
1 X 0 YY 0 XY 1 X X 1 Y1 0 X1 0 Y
XYXY
XY1 0 Y
1 1 1 1Y
10/(02 ‐ 09)/2008 38GMU, ECE 680 Physical VLSI Design
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Logic Cell of Actel Fuse‐Based FPGALogic Cell of Actel Fuse Based FPGA
A
B 1B
SA Y
1
C1
C
D
SB
1
SBS0S1
10/(02 ‐ 09)/2008 39GMU, ECE 680 Physical VLSI Design
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Look‐up Table Based Logic CellLook up Table Based Logic Cellry In Out
Out
Mem
o
00 00
01 1
10 1
11 0
ln1 ln2
10/(02 ‐ 09)/2008 40GMU, ECE 680 Physical VLSI Design
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LUT‐Based Logic Cell Figure must be gC1....C 4
xx
4
xxxx xxxx xxxx
updated
D 4
D 3
D 2
Logicfunction
of
xxxxxxxx
xxxx xxxx xxxx
Bitscontrol
x xxx xx
xxxx
2
D 1
F
xxx
Logicfunction
ofxxx
xxx
xx
xx xx
F 4
F 3
F 2
F 1
Logicfunction
ofxxx
xxxxxxxx
Bitscontrol xx
xxxx
x xxx
xxxxxx
1
HP
Multiplexer Controlledby Configuration Program
x x
xx xx
Xili 4000 S i
Courtesy Xilinx
by Configuration ProgramXilinx 4000 Series
10/(02 ‐ 09)/2008 41GMU, ECE 680 Physical VLSI Design
![Page 42: ECE680: Physical VLSI Designmason.gmu.edu/~qli6/ECE680/chapter5 Implementation strategies.pdf · Impact of Implementation Choices 100‐1000 o cessor P S/mW) 10‐100 a in ‐ specific](https://reader034.vdocuments.us/reader034/viewer/2022042806/5f6a478a0e41be2af9304b96/html5/thumbnails/42.jpg)
Array‐Based Programmable Wiring
InterconnectPoint
M
Input/output pinProgrammed interconnection
M
Cell
Horizontaltracks
Vertical tracks
10/(02 ‐ 09)/2008 42GMU, ECE 680 Physical VLSI Design
![Page 43: ECE680: Physical VLSI Designmason.gmu.edu/~qli6/ECE680/chapter5 Implementation strategies.pdf · Impact of Implementation Choices 100‐1000 o cessor P S/mW) 10‐100 a in ‐ specific](https://reader034.vdocuments.us/reader034/viewer/2022042806/5f6a478a0e41be2af9304b96/html5/thumbnails/43.jpg)
Mesh‐based Interconnect NetworkhSwitch Box
Connect Box
InterconnectInterconnectPoint
Courtesy Dehon and Wawrzyniek10/(02 ‐ 09)/2008 43GMU, ECE 680 Physical VLSI Design
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Transistor Implementation of Mesh
Courtesy Dehon and Wawrzyniek10/(02 ‐ 09)/2008 44GMU, ECE 680 Physical VLSI Design
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Hierarchical Mesh Network
Use overlayed mesht t l tito support longer connections
Reduced fanout and reduced resistance
Courtesy Dehon and Wawrzyniek10/(02 ‐ 09)/2008 45GMU, ECE 680 Physical VLSI Design
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EPLD Block Diagram
MacrocellPrimary inputs
Courtesy Altera10/(02 ‐ 09)/2008 46GMU, ECE 680 Physical VLSI Design
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Altera MAX
From Smith9710/(02 ‐ 09)/2008 47GMU, ECE 680 Physical VLSI Design
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Altera MAX Interconnect Architecture
tPIA
row channelcolumn channel
LAB2LAB1
tPIA
PIA
LAB
LAB6tPIA
Array‐based(MAX 3000‐7000)
Mesh‐based(MAX 9000)
Courtesy Altera10/(02 ‐ 09)/2008 48GMU, ECE 680 Physical VLSI Design
![Page 49: ECE680: Physical VLSI Designmason.gmu.edu/~qli6/ECE680/chapter5 Implementation strategies.pdf · Impact of Implementation Choices 100‐1000 o cessor P S/mW) 10‐100 a in ‐ specific](https://reader034.vdocuments.us/reader034/viewer/2022042806/5f6a478a0e41be2af9304b96/html5/thumbnails/49.jpg)
Field‐Programmable Gate Arraysb dFuse‐based
I/O B ffI/O Buffers
Program/Test/Diagnostics
Vertical routes
fers
ffers
Standard‐cell likefloorplan
I/O B
uff
I/O B
uff
I/O Buffers
Rows of logic modulesRouting channels
I/O Buffers
10/(02 ‐ 09)/2008 49GMU, ECE 680 Physical VLSI Design
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Xilinx 4000 Interconnect Architecture
12
8
Quad
Single
4
3
Double
Long
2
3
CLBDirectConnect
Long
28 4 8 4
DirectConnect
Quad Long GlobalClock
Long Double Single GlobalClock
CarryChain
12 4 4
Courtesy Xilinx10/(02 ‐ 09)/2008 50GMU, ECE 680 Physical VLSI Design
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RAM‐based FPGA
Xilinx XC4000ex
Courtesy Xilinx10/(02 ‐ 09)/2008 51GMU, ECE 680 Physical VLSI Design
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A Low‐Energy FPGA (UC Berkeley)
Array Size: 8x8 (2 x 4 LUT)
Power Supply: 1.5V & 0.8V
Configuration: Mapped as RAM
Toggle Frequency: 125MHz
Area: 3mm x 3mm
10/(02 ‐ 09)/2008 52GMU, ECE 680 Physical VLSI Design
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Larger Granularity FPGAs
1‐mm 2‐metal
PADDI‐2 (UC Berkeley)
CMOS tech
1.2 x 1.2 mm2
600k transistors
208‐pin PGA
fclock = 50 MHz
P = 3.6 W@ 5Vav 3.6 W @ 5V
Basic Module: Datapath
10/(02 ‐ 09)/2008 53GMU, ECE 680 Physical VLSI Design
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Design at a crossroad
S t ChiSystem‐on‐a‐Chip
500 k Gates FPGA+ 1 Gbit DRAM
Multi-Spectral lo
g
Embedded applications where cost,performance, and energy are the real
RAM + 1 Gbit DRAMPreprocessing
SpectralImager
μC
Ana
l
64 SIMD Processor
issues!
DSP and control intensive
Mixed‐modeμC
system+2 GbitDRAM
Array + SRAM
Image Conditioning
Combines programmable and application‐specific modules
Software plays crucial roleDRAMRecog-nition
g g100 GOPS
10/(02 ‐ 09)/2008 54GMU, ECE 680 Physical VLSI Design
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Addressing the Design Complexity IssueArchitecture ReuseArchitecture Reuse
Reuse comes in generationsReuse comes in generationsGeneration Reuse element Status
1st Standard cells Well established
2nd IP blocks Being introduced
3rd Architecture Emerging
4th IC Early research
Source: Theo Claasen (Philips) – DAC 00
10/(02 ‐ 09)/2008 55GMU, ECE 680 Physical VLSI Design
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Architecture ReUse
• Silicon System Platform– Flexible architecture for hardware and softwareFlexible architecture for hardware and software
– Specific (programmable) components
– Network architecture
– Software modulesSoftware modules
– Rules and guidelines for design of HW and SW
• Has been successful in PC’sDominance of a few players who specify and control architecture– Dominance of a few players who specify and control architecture
• Application‐domain specific (difference in constraints)– Speed (compute power)
Di i ti– Dissipation
– Costs
– Real / non‐real time data
10/(02 ‐ 09)/2008 56GMU, ECE 680 Physical VLSI Design
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Platform‐Based Design
“Only the consumer gets freedom of choice;“Only the consumer gets freedom of choice;designers need freedomdesigners need freedom fromfrom choice”choice”
(Orfali, et al, 1996, p.522)(Orfali, et al, 1996, p.522)
• A platform is a restriction on the space of possible implementation choices, providing a well‐defined abstraction of the underlying technology for the application developer
• New platforms will be defined at the architecture‐micro‐architecture boundary
• They will be component‐based, and will provide a range of choices from structured custom to fully programmable implementationsstructured‐custom to fully programmable implementations
• Key to such approaches is the representation of communication in the platform model
Source:R.Newton10/(02 ‐ 09)/2008 57GMU, ECE 680 Physical VLSI Design
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Berkeley Pleiades Processor
• 0.25um 6-level metal CMOS
• 5.2mm x 6.7mm
1 2 Milli t i t
FPGA
• 1.2 Million transistors
• 40 MHz at 1V
• 2 extra supplies: 0.4V, 1.5VReconfigurable pp ,
• 1.5~2 mW power dissipation
Interface
Reconfigurable
Data‐path
ARM8 Core
10/(02 ‐ 09)/2008 58GMU, ECE 680 Physical VLSI Design
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Heterogeneous Programmable PlatformsFPGA Fabric
Embedded PowerPcEmbedded memories
Hardwired multipliersHardwired multipliers
Xilinx Vertex‐II Pro
Courtesy Xilinx
High‐speed I/O
10/(02 ‐ 09)/2008 59GMU, ECE 680 Physical VLSI Design
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Summary
• Digital CMOS Design is kicking and healthyS j h ll d h d d b• Some major challenges down the road caused by Deep Sub‐micron– Super GHz designp g– Power consumption!!!!– Reliability – making it workSome new circuit solutions are bound to emergeSome new circuit solutions are bound to emerge
• Who can afford design in the years to come? Some major design methodology change in the
ki !making!
10/(02 ‐ 09)/2008 60GMU, ECE 680 Physical VLSI Design
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Sequential Logic
OutputsInputsCOMBINATIONAL
LOGIC
Outputs
C rrent State
Inputs
RegistersNext state
Q D
Current State
CLK
2 storage mechanisms
• positive feedback
• charge based• charge‐based
10/(02 ‐ 09)/2008 61GMU, ECE 680 Physical VLSI Design